--- v4
+++ v10
@@ -1,138 +1,232 @@
From: Stefan Chulski <stefanc@marvell.com>
-RXQ non occupied descriptor threshold would be used by
-Flow Control Firmware feature to move to the XOFF mode.
-RXQ non occupied threshold would change interrupt cause
-that polled by CM3 Firmware.
-Actual non occupied interrupt masked and won't trigger interrupt.
+This patch adds RXQ flow control configurations.
+Flow control disabled by default.
+Minimum ring size limited to 1024 descriptors.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
---
- drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 3 ++
- drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 46 +++++++++++++++++---
- 2 files changed, 42 insertions(+), 7 deletions(-)
+ drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 35 +++++-
+ drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 116 ++++++++++++++++++++
+ 2 files changed, 150 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-index 73f087c..9d8993f 100644
+index 8945fb9..0010a3e9 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-@@ -295,6 +295,8 @@
- #define MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK 0x3fc00000
- #define MVPP2_PON_CAUSE_MISC_SUM_MASK BIT(31)
- #define MVPP2_ISR_MISC_CAUSE_REG 0x55b0
-+#define MVPP2_ISR_RX_ERR_CAUSE_REG(port) (0x5520 + 4 * (port))
-+#define MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK 0x00ff
-
- /* Buffer Manager registers */
- #define MVPP2_BM_POOL_BASE_REG(pool) (0x6000 + ((pool) * 4))
-@@ -764,6 +766,7 @@
- #define MSS_SRAM_SIZE 0x800
- #define FC_QUANTA 0xFFFF
- #define FC_CLK_DIVIDER 100
+@@ -765,9 +765,36 @@
+ /* MSS Flow control */
+ #define MSS_FC_COM_REG 0
+ #define FLOW_CONTROL_ENABLE_BIT BIT(0)
++#define FLOW_CONTROL_UPDATE_COMMAND_BIT BIT(31)
+ #define FC_QUANTA 0xFFFF
+ #define FC_CLK_DIVIDER 100
+-#define MSS_THRESHOLD_STOP 768
++
++#define MSS_RXQ_TRESH_BASE 0x200
++#define MSS_RXQ_TRESH_OFFS 4
++#define MSS_RXQ_TRESH_REG(q, fq) (MSS_RXQ_TRESH_BASE + (((q) + (fq)) \
++ * MSS_RXQ_TRESH_OFFS))
++
++#define MSS_RXQ_TRESH_START_MASK 0xFFFF
++#define MSS_RXQ_TRESH_STOP_MASK (0xFFFF << MSS_RXQ_TRESH_STOP_OFFS)
++#define MSS_RXQ_TRESH_STOP_OFFS 16
++
++#define MSS_RXQ_ASS_BASE 0x80
++#define MSS_RXQ_ASS_OFFS 4
++#define MSS_RXQ_ASS_PER_REG 4
++#define MSS_RXQ_ASS_PER_OFFS 8
++#define MSS_RXQ_ASS_PORTID_OFFS 0
++#define MSS_RXQ_ASS_PORTID_MASK 0x3
++#define MSS_RXQ_ASS_HOSTID_OFFS 2
++#define MSS_RXQ_ASS_HOSTID_MASK 0x3F
++
++#define MSS_RXQ_ASS_Q_BASE(q, fq) ((((q) + (fq)) % MSS_RXQ_ASS_PER_REG) \
++ * MSS_RXQ_ASS_PER_OFFS)
++#define MSS_RXQ_ASS_PQ_BASE(q, fq) ((((q) + (fq)) / MSS_RXQ_ASS_PER_REG) \
++ * MSS_RXQ_ASS_OFFS)
++#define MSS_RXQ_ASS_REG(q, fq) (MSS_RXQ_ASS_BASE + MSS_RXQ_ASS_PQ_BASE(q, fq))
++
+#define MSS_THRESHOLD_STOP 768
++#define MSS_THRESHOLD_START 1024
/* RX buffer constants */
#define MVPP2_SKB_SHINFO_SIZE \
+@@ -1022,6 +1049,9 @@ struct mvpp2 {
+
+ /* Global TX Flow Control config */
+ bool global_tx_fc;
++
++ /* Spinlocks for CM3 shared memory configuration */
++ spinlock_t mss_spinlock;
+ };
+
+ struct mvpp2_pcpu_stats {
+@@ -1184,6 +1214,9 @@ struct mvpp2_port {
+ bool rx_hwtstamp;
+ enum hwtstamp_tx_types tx_hwtstamp_type;
+ struct mvpp2_hwtstamp_queue tx_hwtstamp_queue[2];
++
++ /* Firmware TX flow control */
++ bool tx_fc;
+ };
+
+ /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-index 8f40293a..a4933c4 100644
+index 027101b..f1770e5 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-@@ -1144,14 +1144,19 @@ static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)
- static void mvpp2_interrupts_mask(void *arg)
- {
- struct mvpp2_port *port = arg;
-+ int cpu = smp_processor_id();
-+ u32 thread;
-
- /* If the thread isn't used, don't do anything */
-- if (smp_processor_id() > port->priv->nthreads)
-+ if (cpu >= port->priv->nthreads)
- return;
-
-- mvpp2_thread_write(port->priv,
-- mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
-+ thread = mvpp2_cpu_to_thread(port->priv, cpu);
-+
-+ mvpp2_thread_write(port->priv, thread,
- MVPP2_ISR_RX_TX_MASK_REG(port->id), 0);
-+ mvpp2_thread_write(port->priv, thread,
-+ MVPP2_ISR_RX_ERR_CAUSE_REG(port->id), 0);
+@@ -741,6 +741,110 @@ static void *mvpp2_buf_alloc(struct mvpp2_port *port,
+ return data;
}
- /* Unmask the current thread's Rx/Tx interrupts.
-@@ -1161,20 +1166,25 @@ static void mvpp2_interrupts_mask(void *arg)
- static void mvpp2_interrupts_unmask(void *arg)
- {
- struct mvpp2_port *port = arg;
-- u32 val;
-+ int cpu = smp_processor_id();
-+ u32 val, thread;
-
- /* If the thread isn't used, don't do anything */
-- if (smp_processor_id() > port->priv->nthreads)
-+ if (cpu >= port->priv->nthreads)
- return;
-
-+ thread = mvpp2_cpu_to_thread(port->priv, cpu);
-+
- val = MVPP2_CAUSE_MISC_SUM_MASK |
- MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);
- if (port->has_tx_irqs)
- val |= MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;
-
-- mvpp2_thread_write(port->priv,
-- mvpp2_cpu_to_thread(port->priv, smp_processor_id()),
-+ mvpp2_thread_write(port->priv, thread,
- MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
-+ mvpp2_thread_write(port->priv, thread,
-+ MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
-+ MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
++/* Routine enable flow control for RXQs condition */
++static void mvpp2_rxq_enable_fc(struct mvpp2_port *port)
++{
++ int val, cm3_state, host_id, q;
++ int fq = port->first_rxq;
++ unsigned long flags;
++
++ spin_lock_irqsave(&port->priv->mss_spinlock, flags);
++
++ /* Remove Flow control enable bit to prevent race between FW and Kernel
++ * If Flow control was enabled, it would be re-enabled.
++ */
++ val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
++ cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
++ val &= ~FLOW_CONTROL_ENABLE_BIT;
++ mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
++
++ /* Set same Flow control for all RXQs */
++ for (q = 0; q < port->nrxqs; q++) {
++ /* Set stop and start Flow control RXQ thresholds */
++ val = MSS_THRESHOLD_START;
++ val |= (MSS_THRESHOLD_STOP << MSS_RXQ_TRESH_STOP_OFFS);
++ mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
++
++ val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
++ /* Set RXQ port ID */
++ val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
++ val |= (port->id << MSS_RXQ_ASS_Q_BASE(q, fq));
++ val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
++ + MSS_RXQ_ASS_HOSTID_OFFS));
++
++ /* Calculate RXQ host ID:
++ * In Single queue mode: Host ID equal to Host ID used for
++ * shared RX interrupt
++ * In Multi queue mode: Host ID equal to number of
++ * RXQ ID / number of CoS queues
++ * In Single resource mode: Host ID always equal to 0
++ */
++ if (queue_mode == MVPP2_QDIST_SINGLE_MODE)
++ host_id = port->nqvecs;
++ else if (queue_mode == MVPP2_QDIST_MULTI_MODE)
++ host_id = q;
++ else
++ host_id = 0;
++
++ /* Set RXQ host ID */
++ val |= (host_id << (MSS_RXQ_ASS_Q_BASE(q, fq)
++ + MSS_RXQ_ASS_HOSTID_OFFS));
++
++ mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val);
++ }
++
++ /* Notify Firmware that Flow control config space ready for update */
++ val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
++ val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
++ val |= cm3_state;
++ mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
++
++ spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
++}
++
++/* Routine disable flow control for RXQs condition */
++static void mvpp2_rxq_disable_fc(struct mvpp2_port *port)
++{
++ int val, cm3_state, q;
++ unsigned long flags;
++ int fq = port->first_rxq;
++
++ spin_lock_irqsave(&port->priv->mss_spinlock, flags);
++
++ /* Remove Flow control enable bit to prevent race between FW and Kernel
++ * If Flow control was enabled, it would be re-enabled.
++ */
++ val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
++ cm3_state = (val & FLOW_CONTROL_ENABLE_BIT);
++ val &= ~FLOW_CONTROL_ENABLE_BIT;
++ mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
++
++ /* Disable Flow control for all RXQs */
++ for (q = 0; q < port->nrxqs; q++) {
++ /* Set threshold 0 to disable Flow control */
++ val = 0;
++ val |= (0 << MSS_RXQ_TRESH_STOP_OFFS);
++ mvpp2_cm3_write(port->priv, MSS_RXQ_TRESH_REG(q, fq), val);
++
++ val = mvpp2_cm3_read(port->priv, MSS_RXQ_ASS_REG(q, fq));
++
++ val &= ~(MSS_RXQ_ASS_PORTID_MASK << MSS_RXQ_ASS_Q_BASE(q, fq));
++
++ val &= ~(MSS_RXQ_ASS_HOSTID_MASK << (MSS_RXQ_ASS_Q_BASE(q, fq)
++ + MSS_RXQ_ASS_HOSTID_OFFS));
++
++ mvpp2_cm3_write(port->priv, MSS_RXQ_ASS_REG(q, fq), val);
++ }
++
++ /* Notify Firmware that Flow control config space ready for update */
++ val = mvpp2_cm3_read(port->priv, MSS_FC_COM_REG);
++ val |= FLOW_CONTROL_UPDATE_COMMAND_BIT;
++ val |= cm3_state;
++ mvpp2_cm3_write(port->priv, MSS_FC_COM_REG, val);
++
++ spin_unlock_irqrestore(&port->priv->mss_spinlock, flags);
++}
++
+ /* Release buffer to BM */
+ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
+ dma_addr_t buf_dma_addr,
+@@ -3005,6 +3109,9 @@ static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
+
+ for (queue = 0; queue < port->nrxqs; queue++)
+ mvpp2_rxq_deinit(port, port->rxqs[queue]);
++
++ if (port->tx_fc)
++ mvpp2_rxq_disable_fc(port);
}
- static void
-@@ -1199,6 +1209,9 @@ static void mvpp2_interrupts_unmask(void *arg)
-
- mvpp2_thread_write(port->priv, v->sw_thread_id,
- MVPP2_ISR_RX_TX_MASK_REG(port->id), val);
-+ mvpp2_thread_write(port->priv, v->sw_thread_id,
-+ MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),
-+ MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);
+ /* Init all Rx queues for port */
+@@ -3017,6 +3124,10 @@ static int mvpp2_setup_rxqs(struct mvpp2_port *port)
+ if (err)
+ goto err_cleanup;
}
- }
-
-@@ -2404,6 +2417,22 @@ static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)
++
++ if (port->tx_fc)
++ mvpp2_rxq_enable_fc(port);
++
+ return 0;
+
+ err_cleanup:
+@@ -4316,6 +4427,8 @@ static int mvpp2_check_ringparam_valid(struct net_device *dev,
+
+ if (ring->rx_pending > MVPP2_MAX_RXD_MAX)
+ new_rx_pending = MVPP2_MAX_RXD_MAX;
++ else if (ring->rx_pending < MSS_THRESHOLD_START)
++ new_rx_pending = MSS_THRESHOLD_START;
+ else if (!IS_ALIGNED(ring->rx_pending, 16))
+ new_rx_pending = ALIGN(ring->rx_pending, 16);
+
+@@ -7148,6 +7261,9 @@ static int mvpp2_probe(struct platform_device *pdev)
+ priv->hw_version = MVPP23;
}
- }
-
-+/* Routine set the number of non-occupied descriptors threshold that change
-+ * interrupt error cause polled by FW Flow Control
-+ */
-+static void mvpp2_set_rxq_free_tresh(struct mvpp2_port *port,
-+ struct mvpp2_rx_queue *rxq)
-+{
-+ u32 val;
-+
-+ mvpp2_write(port->priv, MVPP2_RXQ_NUM_REG, rxq->id);
-+
-+ val = mvpp2_read(port->priv, MVPP2_RXQ_THRESH_REG);
-+ val &= ~MVPP2_RXQ_NON_OCCUPIED_MASK;
-+ val |= MSS_THRESHOLD_STOP << MVPP2_RXQ_NON_OCCUPIED_OFFSET;
-+ mvpp2_write(port->priv, MVPP2_RXQ_THRESH_REG, val);
-+}
-+
- /* Set the number of packets that will be received before Rx interrupt
- * will be generated by HW.
- */
-@@ -2659,6 +2688,9 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,
- mvpp2_rx_pkts_coal_set(port, rxq);
- mvpp2_rx_time_coal_set(port, rxq);
-
-+ /* Set the number of non occupied descriptors threshold */
-+ mvpp2_set_rxq_free_tresh(port, rxq);
-+
- /* Add number of descriptors ready for receiving packets */
- mvpp2_rxq_status_update(port, rxq->id, 0, rxq->size);
-
+
++ /* Init mss lock */
++ spin_lock_init(&priv->mss_spinlock);
++
+ /* Initialize network controller */
+ err = mvpp2_init(pdev, priv);
+ if (err < 0) {
--
1.9.1