--- v2
+++ vrfc
@@ -1,27 +1,154 @@
From: Stefan Chulski <stefanc@marvell.com>
-This patch fix GMAC TX flow control autoneg.
-Flow control autoneg wrongly were disabled with enabled TX
-flow control.
+New FIFO flow control feature were added in PPv23.
+PPv2 FIFO polled by HW and trigger pause frame if FIFO
+fill level is below threshold.
+FIFO HW flow control enabled with CM3 RXQ&BM flow
+control with ethtool.
+Current FIFO thresholds is:
+9KB for port with maximum speed 10Gb/s port
+4KB for port with maximum speed 5Gb/s port
+2KB for port with maximum speed 1Gb/s port
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
---
- drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
+ drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 16 +++++-
+ drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 55 ++++++++++++++++++++
+ 2 files changed, 70 insertions(+), 1 deletion(-)
+diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+index 27aa593..3451618 100644
+--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+@@ -770,6 +770,18 @@
+ #define MVPP2_TX_FIFO_THRESHOLD(kb) \
+ ((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
+
++/* RX FIFO threshold in 1KB granularity */
++#define MVPP23_PORT0_FIFO_TRSH (9 * 1024)
++#define MVPP23_PORT1_FIFO_TRSH (4 * 1024)
++#define MVPP23_PORT2_FIFO_TRSH (2 * 1024)
++
++/* RX Flow Control Registers */
++#define MVPP2_RX_FC_REG(port) (0x150 + 4 * (port))
++#define MVPP2_RX_FC_EN BIT(24)
++#define MVPP2_RX_FC_TRSH_OFFS 16
++#define MVPP2_RX_FC_TRSH_MASK (0xFF << MVPP2_RX_FC_TRSH_OFFS)
++#define MVPP2_RX_FC_TRSH_UNIT 256
++
+ /* MSS Flow control */
+ #define MSS_SRAM_SIZE 0x800
+ #define MSS_FC_COM_REG 0
+@@ -818,7 +830,6 @@
+ #define MSS_THRESHOLD_STOP 768
+ #define MSS_THRESHOLD_START 1024
+
+-
+ /* RX buffer constants */
+ #define MVPP2_SKB_SHINFO_SIZE \
+ SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
+@@ -1505,6 +1516,8 @@ struct mvpp2_bm_pool {
+
+ void mvpp2_dbgfs_cleanup(struct mvpp2 *priv);
+
++void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en);
++
+ #ifdef CONFIG_MVPP2_PTP
+ int mvpp22_tai_probe(struct device *dev, struct mvpp2 *priv);
+ void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp,
+@@ -1537,4 +1550,5 @@ static inline bool mvpp22_rx_hwtstamping(struct mvpp2_port *port)
+ {
+ return IS_ENABLED(CONFIG_MVPP2_PTP) && port->rx_hwtstamp;
+ }
++
+ #endif
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-index ee4f1ff..03a4b36 100644
+index 8827f52..757dfe0 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-@@ -6283,7 +6283,7 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
- old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
+@@ -5448,6 +5448,8 @@ static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
+ mvpp2_bm_pool_update_fc(port, port->pool_long, true);
+ mvpp2_bm_pool_update_fc(port, port->pool_short, true);
+ }
++ if (port->priv->hw_version == MVPP23)
++ mvpp23_rx_fifo_fc_en(port->priv, port->id, true);
- ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
-- ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK);
-+ ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_FLOW_CTRL_MASK);
+ } else if (port->priv->global_tx_fc) {
+ port->tx_fc = false;
+@@ -5459,6 +5461,8 @@ static int mvpp2_ethtool_set_pause_param(struct net_device *dev,
+ mvpp2_bm_pool_update_fc(port, port->pool_long, false);
+ mvpp2_bm_pool_update_fc(port, port->pool_short, false);
+ }
++ if (port->priv->hw_version == MVPP23)
++ mvpp23_rx_fifo_fc_en(port->priv, port->id, false);
+ }
- /* Configure port type */
- if (phy_interface_mode_is_8023z(state->interface)) {
+ if (!port->phylink)
+@@ -7022,6 +7026,55 @@ static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
+ mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
+ }
+
++/* Configure Rx FIFO Flow control thresholds */
++static void mvpp23_rx_fifo_fc_set_tresh(struct mvpp2 *priv)
++{
++ int port, val;
++
++ /* Port 0: maximum speed -10Gb/s port
++ * required by spec RX FIFO threshold 9KB
++ * Port 1: maximum speed -5Gb/s port
++ * required by spec RX FIFO threshold 4KB
++ * Port 2: maximum speed -1Gb/s port
++ * required by spec RX FIFO threshold 2KB
++ */
++
++ /* Without loopback port */
++ for (port = 0; port < (MVPP2_MAX_PORTS - 1); port++) {
++ if (port == 0) {
++ val = (MVPP23_PORT0_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
++ << MVPP2_RX_FC_TRSH_OFFS;
++ val &= MVPP2_RX_FC_TRSH_MASK;
++ mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
++ } else if (port == 1) {
++ val = (MVPP23_PORT1_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
++ << MVPP2_RX_FC_TRSH_OFFS;
++ val &= MVPP2_RX_FC_TRSH_MASK;
++ mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
++ } else {
++ val = (MVPP23_PORT2_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
++ << MVPP2_RX_FC_TRSH_OFFS;
++ val &= MVPP2_RX_FC_TRSH_MASK;
++ mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
++ }
++ }
++}
++
++/* Configure Rx FIFO Flow control thresholds */
++void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en)
++{
++ int val;
++
++ val = mvpp2_read(priv, MVPP2_RX_FC_REG(port));
++
++ if (en)
++ val |= MVPP2_RX_FC_EN;
++ else
++ val &= ~MVPP2_RX_FC_EN;
++
++ mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
++}
++
+ static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size)
+ {
+ int threshold = MVPP2_TX_FIFO_THRESHOLD(size);
+@@ -7173,6 +7226,8 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
+ } else {
+ mvpp22_rx_fifo_init(priv);
+ mvpp22_tx_fifo_init(priv);
++ if (priv->hw_version == MVPP23)
++ mvpp23_rx_fifo_fc_set_tresh(priv);
+ }
+
+ if (priv->hw_version == MVPP21)
--
1.9.1