--- v2
+++ v7
@@ -1,120 +1,27 @@
From: Stefan Chulski <stefanc@marvell.com>
-Feature double size of BPPI by decreasing number of pools from 16 to 8.
-Increasing of BPPI size protect BM drop from BPPI underrun.
-Underrun could occurred due to stress on DDR and as result slow buffer
-transition from BPPE to BPPI.
-New BPPI threshold recommended by spec is:
-BPPI low threshold - 640 buffers
-BPPI high threshold - 832 buffers
-Supported only in PPv23.
+This patch fix GMAC TX flow control autoneg.
+Flow control autoneg wrongly were disabled with enabled TX
+flow control.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
---
- drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 8 +++++
- drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 35 +++++++++++++++++++-
- 2 files changed, 42 insertions(+), 1 deletion(-)
+ drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-index feac64c..1db8245 100644
---- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-@@ -324,6 +324,10 @@
- #define MVPP2_BM_HIGH_THRESH_MASK 0x7f0000
- #define MVPP2_BM_HIGH_THRESH_VALUE(val) ((val) << \
- MVPP2_BM_HIGH_THRESH_OFFS)
-+#define MVPP2_BM_BPPI_HIGH_THRESH 0x1E
-+#define MVPP2_BM_BPPI_LOW_THRESH 0x1C
-+#define MVPP23_BM_BPPI_HIGH_THRESH 0x34
-+#define MVPP23_BM_BPPI_LOW_THRESH 0x28
- #define MVPP2_BM_INTR_CAUSE_REG(pool) (0x6240 + ((pool) * 4))
- #define MVPP2_BM_RELEASED_DELAY_MASK BIT(0)
- #define MVPP2_BM_ALLOC_FAILED_MASK BIT(1)
-@@ -352,6 +356,10 @@
- #define MVPP2_OVERRUN_ETH_DROP 0x7000
- #define MVPP2_CLS_ETH_DROP 0x7020
-
-+#define MVPP22_BM_POOL_BASE_ADDR_HIGH_REG 0x6310
-+#define MVPP22_BM_POOL_BASE_ADDR_HIGH_MASK 0xff
-+#define MVPP23_BM_8POOL_MODE BIT(8)
-+
- /* Hit counters registers */
- #define MVPP2_CTRS_IDX 0x7040
- #define MVPP22_CTRS_TX_CTR(port, txq) ((txq) | ((port) << 3) | BIT(7))
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-index 20157b5..da387dd2 100644
+index 06d3239..98849b0 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-@@ -70,6 +70,11 @@ enum mvpp2_bm_pool_log_num {
- module_param(queue_mode, int, 0444);
- MODULE_PARM_DESC(queue_mode, "Set queue_mode (single=0, multi=1)");
+@@ -6284,7 +6284,7 @@ static void mvpp2_gmac_config(struct mvpp2_port *port, unsigned int mode,
+ old_ctrl4 = ctrl4 = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
-+static int bm_underrun_protect = 1;
-+
-+module_param(bm_underrun_protect, int, 0444);
-+MODULE_PARM_DESC(bm_underrun_protect, "Set BM underrun protect feature (0-1), def=1");
-+
- /* Utility/helper methods */
+ ctrl0 &= ~MVPP2_GMAC_PORT_TYPE_MASK;
+- ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK);
++ ctrl2 &= ~(MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK | MVPP2_GMAC_FLOW_CTRL_MASK);
- void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data)
-@@ -426,6 +431,21 @@ static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv,
-
- val = mvpp2_read(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id));
- val |= MVPP2_BM_START_MASK;
-+
-+ val &= ~MVPP2_BM_LOW_THRESH_MASK;
-+ val &= ~MVPP2_BM_HIGH_THRESH_MASK;
-+
-+ /* Set 8 Pools BPPI threshold if BM underrun protection feature
-+ * were enabled
-+ */
-+ if (priv->hw_version == MVPP23 && bm_underrun_protect) {
-+ val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP23_BM_BPPI_LOW_THRESH);
-+ val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP23_BM_BPPI_HIGH_THRESH);
-+ } else {
-+ val |= MVPP2_BM_LOW_THRESH_VALUE(MVPP2_BM_BPPI_LOW_THRESH);
-+ val |= MVPP2_BM_HIGH_THRESH_VALUE(MVPP2_BM_BPPI_HIGH_THRESH);
-+ }
-+
- mvpp2_write(priv, MVPP2_BM_POOL_CTRL_REG(bm_pool->id), val);
-
- bm_pool->size = size;
-@@ -594,6 +614,16 @@ static int mvpp2_bm_pools_init(struct device *dev, struct mvpp2 *priv)
- return err;
- }
-
-+/* Routine enable PPv23 8 pool mode */
-+static void mvpp23_bm_set_8pool_mode(struct mvpp2 *priv)
-+{
-+ int val;
-+
-+ val = mvpp2_read(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG);
-+ val |= MVPP23_BM_8POOL_MODE;
-+ mvpp2_write(priv, MVPP22_BM_POOL_BASE_ADDR_HIGH_REG, val);
-+}
-+
- static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
- {
- enum dma_data_direction dma_dir = DMA_FROM_DEVICE;
-@@ -647,6 +677,9 @@ static int mvpp2_bm_init(struct device *dev, struct mvpp2 *priv)
- if (!priv->bm_pools)
- return -ENOMEM;
-
-+ if (priv->hw_version == MVPP23 && bm_underrun_protect)
-+ mvpp23_bm_set_8pool_mode(priv);
-+
- err = mvpp2_bm_pools_init(dev, priv);
- if (err < 0)
- return err;
-@@ -6490,7 +6523,7 @@ static void mvpp2_mac_link_up(struct phylink_config *config,
- val);
- }
-
-- if (tx_pause && port->priv->global_tx_fc) {
-+ if (tx_pause && port->priv->global_tx_fc && bm_underrun_protect) {
- port->tx_fc = true;
- mvpp2_rxq_enable_fc(port);
- if (port->priv->percpu_pools) {
+ /* Configure port type */
+ if (phy_interface_mode_is_8023z(state->interface)) {
--
1.9.1