--- v12
+++ v3
@@ -1,45 +1,182 @@
From: Stefan Chulski <stefanc@marvell.com>
-BM pool and RXQ size increased to support Firmware Flow Control.
-Minimum depletion thresholds to support FC are 1024 buffers.
-BM pool size increased to 2048 to have some 1024 buffers
-space between depletion thresholds and BM pool size.
+Currently we have PP2v1 and PP2v2 hw-versions, with some different
+handlers depending upon condition hw_version = MVPP21/MVPP22.
+In a future there will be also PP2v3. Let's use now the generic
+"if equal/notEqual MVPP21" for all cases instead of "if MVPP22".
-Jumbo frames require a 9888B buffer, so memory requirements
-for data buffers increased from 7MB to 24MB.
+This patch does not change any functionality.
+It is not intended to introduce PP2v3.
+It just modifies MVPP21/MVPP22 check-condition
+bringing it to generic and unified form correct for new-code
+introducing and PP2v3 net-next generation.
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
-Acked-by: Marcin Wojtas <mw@semihalf.com>
---
- drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
+ drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 36 ++++++++++----------
+ 1 file changed, 18 insertions(+), 18 deletions(-)
-diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-index ce08086..e7bbf0a 100644
---- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-@@ -715,8 +715,8 @@
- #define MVPP2_PORT_MAX_RXQ 32
+diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+index 4f482ad..409ca64 100644
+--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+@@ -330,7 +330,7 @@ static int mvpp2_get_nrxqs(struct mvpp2 *priv)
+ {
+ unsigned int nrxqs;
- /* Max number of Rx descriptors */
--#define MVPP2_MAX_RXD_MAX 1024
--#define MVPP2_MAX_RXD_DFLT 128
-+#define MVPP2_MAX_RXD_MAX 2048
-+#define MVPP2_MAX_RXD_DFLT 1024
+- if (priv->hw_version == MVPP22 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
++ if (priv->hw_version != MVPP21 && queue_mode == MVPP2_QDIST_SINGLE_MODE)
+ return 1;
- /* Max number of Tx descriptors */
- #define MVPP2_MAX_TXD_MAX 2048
-@@ -848,8 +848,8 @@ enum mvpp22_ptp_packet_format {
- #define MVPP22_PTP_TIMESTAMPQUEUESELECT BIT(18)
+ /* According to the PPv2.2 datasheet and our experiments on
+@@ -457,7 +457,7 @@ static void mvpp2_bm_bufs_get_addrs(struct device *dev, struct mvpp2 *priv,
+ MVPP2_BM_PHY_ALLOC_REG(bm_pool->id));
+ *phys_addr = mvpp2_thread_read(priv, thread, MVPP2_BM_VIRT_ALLOC_REG);
- /* BM constants */
--#define MVPP2_BM_JUMBO_BUF_NUM 512
--#define MVPP2_BM_LONG_BUF_NUM 1024
-+#define MVPP2_BM_JUMBO_BUF_NUM 2048
-+#define MVPP2_BM_LONG_BUF_NUM 2048
- #define MVPP2_BM_SHORT_BUF_NUM 2048
- #define MVPP2_BM_POOL_SIZE_MAX (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
- #define MVPP2_BM_POOL_PTR_ALIGN 128
+- if (priv->hw_version == MVPP22) {
++ if (priv->hw_version != MVPP21) {
+ u32 val;
+ u32 dma_addr_highbits, phys_addr_highbits;
+
+@@ -753,7 +753,7 @@ static inline void mvpp2_bm_pool_put(struct mvpp2_port *port, int pool,
+ if (test_bit(thread, &port->priv->lock_map))
+ spin_lock_irqsave(&port->bm_lock[thread], flags);
+
+- if (port->priv->hw_version == MVPP22) {
++ if (port->priv->hw_version != MVPP21) {
+ u32 val = 0;
+
+ if (sizeof(dma_addr_t) == 8)
+@@ -1210,7 +1210,7 @@ static bool mvpp2_port_supports_xlg(struct mvpp2_port *port)
+
+ static bool mvpp2_port_supports_rgmii(struct mvpp2_port *port)
+ {
+- return !(port->priv->hw_version == MVPP22 && port->gop_id == 0);
++ return !(port->priv->hw_version != MVPP21 && port->gop_id == 0);
+ }
+
+ /* Port configuration routines */
+@@ -1828,7 +1828,7 @@ static void mvpp2_mac_reset_assert(struct mvpp2_port *port)
+ MVPP2_GMAC_PORT_RESET_MASK;
+ writel(val, port->base + MVPP2_GMAC_CTRL_2_REG);
+
+- if (port->priv->hw_version == MVPP22 && port->gop_id == 0) {
++ if (port->priv->hw_version != MVPP21 && port->gop_id == 0) {
+ val = readl(port->base + MVPP22_XLG_CTRL0_REG) &
+ ~MVPP22_XLG_CTRL0_MAC_RESET_DIS;
+ writel(val, port->base + MVPP22_XLG_CTRL0_REG);
+@@ -1841,7 +1841,7 @@ static void mvpp22_pcs_reset_assert(struct mvpp2_port *port)
+ void __iomem *mpcs, *xpcs;
+ u32 val;
+
+- if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
++ if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
+ return;
+
+ mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
+@@ -1862,7 +1862,7 @@ static void mvpp22_pcs_reset_deassert(struct mvpp2_port *port)
+ void __iomem *mpcs, *xpcs;
+ u32 val;
+
+- if (port->priv->hw_version != MVPP22 || port->gop_id != 0)
++ if (port->priv->hw_version == MVPP21 || port->gop_id != 0)
+ return;
+
+ mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
+@@ -4199,7 +4199,7 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
+ /* Enable interrupts on all threads */
+ mvpp2_interrupts_enable(port);
+
+- if (port->priv->hw_version == MVPP22)
++ if (port->priv->hw_version != MVPP21)
+ mvpp22_mode_reconfigure(port);
+
+ if (port->phylink) {
+@@ -4415,7 +4415,7 @@ static int mvpp2_open(struct net_device *dev)
+ valid = true;
+ }
+
+- if (priv->hw_version == MVPP22 && port->port_irq) {
++ if (priv->hw_version != MVPP21 && port->port_irq) {
+ err = request_irq(port->port_irq, mvpp2_port_isr, 0,
+ dev->name, port);
+ if (err) {
+@@ -6063,7 +6063,7 @@ static int mvpp2__mac_prepare(struct phylink_config *config, unsigned int mode,
+ MVPP2_GMAC_PORT_RESET_MASK,
+ MVPP2_GMAC_PORT_RESET_MASK);
+
+- if (port->priv->hw_version == MVPP22) {
++ if (port->priv->hw_version != MVPP21) {
+ mvpp22_gop_mask_irq(port);
+
+ phy_power_off(port->comphy);
+@@ -6117,7 +6117,7 @@ static int mvpp2_mac_finish(struct phylink_config *config, unsigned int mode,
+ {
+ struct mvpp2_port *port = mvpp2_phylink_to_port(config);
+
+- if (port->priv->hw_version == MVPP22 &&
++ if (port->priv->hw_version != MVPP21 &&
+ port->phy_interface != interface) {
+ port->phy_interface = interface;
+
+@@ -6797,7 +6797,7 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
+ if (dram_target_info)
+ mvpp2_conf_mbus_windows(dram_target_info, priv);
+
+- if (priv->hw_version == MVPP22)
++ if (priv->hw_version != MVPP21)
+ mvpp2_axi_init(priv);
+
+ /* Disable HW PHY polling */
+@@ -6960,7 +6960,7 @@ static int mvpp2_probe(struct platform_device *pdev)
+ dev_warn(&pdev->dev, "Fail to alloc CM3 SRAM\n");
+ }
+
+- if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
++ if (priv->hw_version != MVPP21 && dev_of_node(&pdev->dev)) {
+ priv->sysctrl_base =
+ syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "marvell,system-controller");
+@@ -6973,7 +6973,7 @@ static int mvpp2_probe(struct platform_device *pdev)
+ priv->sysctrl_base = NULL;
+ }
+
+- if (priv->hw_version == MVPP22 &&
++ if (priv->hw_version != MVPP21 &&
+ mvpp2_get_nrxqs(priv) * 2 <= MVPP2_BM_MAX_POOLS)
+ priv->percpu_pools = 1;
+
+@@ -7020,7 +7020,7 @@ static int mvpp2_probe(struct platform_device *pdev)
+ if (err < 0)
+ goto err_pp_clk;
+
+- if (priv->hw_version == MVPP22) {
++ if (priv->hw_version != MVPP21) {
+ priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
+ if (IS_ERR(priv->mg_clk)) {
+ err = PTR_ERR(priv->mg_clk);
+@@ -7061,7 +7061,7 @@ static int mvpp2_probe(struct platform_device *pdev)
+ return -EINVAL;
+ }
+
+- if (priv->hw_version == MVPP22) {
++ if (priv->hw_version != MVPP21) {
+ err = dma_set_mask(&pdev->dev, MVPP2_DESC_DMA_MASK);
+ if (err)
+ goto err_axi_clk;
+@@ -7141,10 +7141,10 @@ static int mvpp2_probe(struct platform_device *pdev)
+ clk_disable_unprepare(priv->axi_clk);
+
+ err_mg_core_clk:
+- if (priv->hw_version == MVPP22)
++ if (priv->hw_version != MVPP21)
+ clk_disable_unprepare(priv->mg_core_clk);
+ err_mg_clk:
+- if (priv->hw_version == MVPP22)
++ if (priv->hw_version != MVPP21)
+ clk_disable_unprepare(priv->mg_clk);
+ err_gop_clk:
+ clk_disable_unprepare(priv->gop_clk);
--
1.9.1