--- vrfc
+++ v10
@@ -1,54 +1,137 @@
From: Stefan Chulski <stefanc@marvell.com>
-This patch add RXQ flow control configurations.
-Patch do not enable flow control itself, flow control
-disabled by default.
+New FIFO flow control feature was added in PPv23.
+PPv2 FIFO polled by HW and trigger pause frame if FIFO
+fill level is below threshold.
+FIFO HW flow control enabled with CM3 RXQ&BM flow
+control with ethtool.
+Current FIFO thresholds is:
+9KB for port with maximum speed 10Gb/s port
+4KB for port with maximum speed 5Gb/s port
+2KB for port with maximum speed 1Gb/s port
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
---
- drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 3 +++
- drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 7 +++++++
- 2 files changed, 10 insertions(+)
+ drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 15 ++++++
+ drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 53 ++++++++++++++++++++
+ 2 files changed, 68 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-index e6bab52..57f7bbc 100644
+index 9b525b60..b61a1ba 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
-@@ -1234,6 +1234,9 @@ struct mvpp2_port {
- bool rx_hwtstamp;
- enum hwtstamp_tx_types tx_hwtstamp_type;
- struct mvpp2_hwtstamp_queue tx_hwtstamp_queue[2];
+@@ -770,6 +770,18 @@
+ #define MVPP2_TX_FIFO_THRESHOLD(kb) \
+ ((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
+
++/* RX FIFO threshold in 1KB granularity */
++#define MVPP23_PORT0_FIFO_TRSH (9 * 1024)
++#define MVPP23_PORT1_FIFO_TRSH (4 * 1024)
++#define MVPP23_PORT2_FIFO_TRSH (2 * 1024)
+
-+ /* Firmware TX flow control */
-+ bool tx_fc;
- };
++/* RX Flow Control Registers */
++#define MVPP2_RX_FC_REG(port) (0x150 + 4 * (port))
++#define MVPP2_RX_FC_EN BIT(24)
++#define MVPP2_RX_FC_TRSH_OFFS 16
++#define MVPP2_RX_FC_TRSH_MASK (0xFF << MVPP2_RX_FC_TRSH_OFFS)
++#define MVPP2_RX_FC_TRSH_UNIT 256
++
+ /* MSS Flow control */
+ #define MSS_FC_COM_REG 0
+ #define FLOW_CONTROL_ENABLE_BIT BIT(0)
+@@ -1498,6 +1510,8 @@ struct mvpp2_bm_pool {
- /* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
+ void mvpp2_dbgfs_cleanup(struct mvpp2 *priv);
+
++void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en);
++
+ #ifdef CONFIG_MVPP2_PTP
+ int mvpp22_tai_probe(struct device *dev, struct mvpp2 *priv);
+ void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp,
+@@ -1530,4 +1544,5 @@ static inline bool mvpp22_rx_hwtstamping(struct mvpp2_port *port)
+ {
+ return IS_ENABLED(CONFIG_MVPP2_PTP) && port->rx_hwtstamp;
+ }
++
+ #endif
diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-index b7ea94f..3b85aec 100644
+index 3faad04..a472125 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
-@@ -3176,6 +3176,9 @@ static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)
+@@ -6536,6 +6536,8 @@ static void mvpp2_mac_link_up(struct phylink_config *config,
+ mvpp2_bm_pool_update_fc(port, port->pool_long, tx_pause);
+ mvpp2_bm_pool_update_fc(port, port->pool_short, tx_pause);
+ }
++ if (port->priv->hw_version == MVPP23)
++ mvpp23_rx_fifo_fc_en(port->priv, port->id, tx_pause);
+ }
- for (queue = 0; queue < port->nrxqs; queue++)
- mvpp2_rxq_deinit(port, port->rxqs[queue]);
-+
-+ if (port->tx_fc)
-+ mvpp2_rxq_disable_fc(port);
+ mvpp2_port_enable(port);
+@@ -7004,6 +7006,55 @@ static void mvpp22_rx_fifo_init(struct mvpp2 *priv)
+ mvpp2_write(priv, MVPP2_RX_FIFO_INIT_REG, 0x1);
}
- /* Init all Rx queues for port */
-@@ -3188,6 +3191,10 @@ static int mvpp2_setup_rxqs(struct mvpp2_port *port)
- if (err)
- goto err_cleanup;
++/* Configure Rx FIFO Flow control thresholds */
++static void mvpp23_rx_fifo_fc_set_tresh(struct mvpp2 *priv)
++{
++ int port, val;
++
++ /* Port 0: maximum speed -10Gb/s port
++ * required by spec RX FIFO threshold 9KB
++ * Port 1: maximum speed -5Gb/s port
++ * required by spec RX FIFO threshold 4KB
++ * Port 2: maximum speed -1Gb/s port
++ * required by spec RX FIFO threshold 2KB
++ */
++
++ /* Without loopback port */
++ for (port = 0; port < (MVPP2_MAX_PORTS - 1); port++) {
++ if (port == 0) {
++ val = (MVPP23_PORT0_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
++ << MVPP2_RX_FC_TRSH_OFFS;
++ val &= MVPP2_RX_FC_TRSH_MASK;
++ mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
++ } else if (port == 1) {
++ val = (MVPP23_PORT1_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
++ << MVPP2_RX_FC_TRSH_OFFS;
++ val &= MVPP2_RX_FC_TRSH_MASK;
++ mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
++ } else {
++ val = (MVPP23_PORT2_FIFO_TRSH / MVPP2_RX_FC_TRSH_UNIT)
++ << MVPP2_RX_FC_TRSH_OFFS;
++ val &= MVPP2_RX_FC_TRSH_MASK;
++ mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
++ }
++ }
++}
++
++/* Configure Rx FIFO Flow control thresholds */
++void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en)
++{
++ int val;
++
++ val = mvpp2_read(priv, MVPP2_RX_FC_REG(port));
++
++ if (en)
++ val |= MVPP2_RX_FC_EN;
++ else
++ val &= ~MVPP2_RX_FC_EN;
++
++ mvpp2_write(priv, MVPP2_RX_FC_REG(port), val);
++}
++
+ static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size)
+ {
+ int threshold = MVPP2_TX_FIFO_THRESHOLD(size);
+@@ -7155,6 +7206,8 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
+ } else {
+ mvpp22_rx_fifo_init(priv);
+ mvpp22_tx_fifo_init(priv);
++ if (priv->hw_version == MVPP23)
++ mvpp23_rx_fifo_fc_set_tresh(priv);
}
-+
-+ if (port->tx_fc)
-+ mvpp2_rxq_enable_fc(port);
-+
- return 0;
- err_cleanup:
+ if (priv->hw_version == MVPP21)
--
1.9.1