--- v5
+++ v11
@@ -1,21 +1,21 @@
-It will make sense to store the pcie_devcap2 value in the pci_dev
-structure instead of reading Device Capabilities 2 Register multiple
-times. Get the pcie_devcap2 value set_pcie_port_type(), then use
-cached pcie_devcap2 in the needed place.
+Add a new member called devcap2 in struct pci_dev for caching the PCIe
+Device Capabilities 2 register to avoid reading PCI_EXP_DEVCAP2 multiple
+times.
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
+Reviewed-by: Christoph Hellwig <hch@lst.de>
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 4 +---
- drivers/pci/pci.c | 9 ++++-----
+ drivers/pci/pci.c | 8 +++-----
drivers/pci/probe.c | 10 ++++------
- include/linux/pci.h | 2 ++
- 4 files changed, 11 insertions(+), 14 deletions(-)
+ include/linux/pci.h | 1 +
+ 4 files changed, 9 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
-index 1f601de..06d24c6 100644
+index 0d9cda4ab303..ae0b6def994b 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
-@@ -6303,7 +6303,6 @@ static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
+@@ -6304,7 +6304,6 @@ static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
struct pci_dev *pbridge;
struct port_info *pi;
char name[IFNAMSIZ];
@@ -23,7 +23,7 @@
u16 flags;
/* If we want to instantiate Virtual Functions, then our
-@@ -6313,10 +6312,9 @@ static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
+@@ -6314,10 +6313,9 @@ static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
*/
pbridge = pdev->bus->self;
pcie_capability_read_word(pbridge, PCI_EXP_FLAGS, &flags);
@@ -31,15 +31,15 @@
if ((flags & PCI_EXP_FLAGS_VERS) < 2 ||
- !(devcap2 & PCI_EXP_DEVCAP2_ARI)) {
-+ !(pbridge->pcie_devcap2 & PCI_EXP_DEVCAP2_ARI)) {
++ !(pbridge->devcap2 & PCI_EXP_DEVCAP2_ARI)) {
/* Our parent bridge does not support ARI so issue a
* warning and skip instantiating the VFs. They
* won't be reachable.
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
-index 68ccd77..e3cd2f4 100644
+index ce2ab62b64cf..64138a83b0f7 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
-@@ -3690,7 +3690,7 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
+@@ -3717,7 +3717,7 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
{
struct pci_bus *bus = dev->bus;
struct pci_dev *bridge;
@@ -48,7 +48,7 @@
if (!pci_is_pcie(dev))
return -EINVAL;
-@@ -3714,19 +3714,18 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
+@@ -3741,19 +3741,17 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
while (bus->parent) {
bridge = bus->self;
@@ -59,31 +59,30 @@
case PCI_EXP_TYPE_UPSTREAM:
case PCI_EXP_TYPE_DOWNSTREAM:
- if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
-+ if (!(bridge->pcie_devcap2 &
-+ PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
++ if (!(bridge->devcap2 & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
return -EINVAL;
break;
/* Ensure root port supports all the sizes we care about */
case PCI_EXP_TYPE_ROOT_PORT:
- if ((cap & cap_mask) != cap_mask)
-+ if ((bridge->pcie_devcap2 & cap_mask) != cap_mask)
++ if ((bridge->devcap2 & cap_mask) != cap_mask)
return -EINVAL;
break;
}
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
-index 76ddc89..0208865 100644
+index 96ecdf34f931..7259ad774ac8 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
-@@ -1500,6 +1500,7 @@ void set_pcie_port_type(struct pci_dev *pdev)
+@@ -1509,6 +1509,7 @@ void set_pcie_port_type(struct pci_dev *pdev)
pdev->pcie_flags_reg = reg16;
- pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->pcie_devcap);
- pdev->pcie_mpss = pdev->pcie_devcap & PCI_EXP_DEVCAP_PAYLOAD;
-+ pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP2, &pdev->pcie_devcap2);
+ pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap);
+ pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap);
++ pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP2, &pdev->devcap2);
parent = pci_upstream_bridge(pdev);
if (!parent)
-@@ -2094,7 +2095,7 @@ static void pci_configure_ltr(struct pci_dev *dev)
+@@ -2129,7 +2130,7 @@ static void pci_configure_ltr(struct pci_dev *dev)
#ifdef CONFIG_PCIEASPM
struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
struct pci_dev *bridge;
@@ -92,17 +91,17 @@
if (!pci_is_pcie(dev))
return;
-@@ -2102,8 +2103,7 @@ static void pci_configure_ltr(struct pci_dev *dev)
+@@ -2137,8 +2138,7 @@ static void pci_configure_ltr(struct pci_dev *dev)
/* Read L1 PM substate capabilities */
dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
- pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
- if (!(cap & PCI_EXP_DEVCAP2_LTR))
-+ if (!(dev->pcie_devcap2 & PCI_EXP_DEVCAP2_LTR))
++ if (!(dev->devcap2 & PCI_EXP_DEVCAP2_LTR))
return;
pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
-@@ -2143,13 +2143,11 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev)
+@@ -2178,13 +2178,11 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev)
#ifdef CONFIG_PCI_PASID
struct pci_dev *bridge;
int pcie_type;
@@ -113,23 +112,22 @@
- pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
- if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
-+ if (!(dev->pcie_devcap2 & PCI_EXP_DEVCAP2_EE_PREFIX))
++ if (!(dev->devcap2 & PCI_EXP_DEVCAP2_EE_PREFIX))
return;
pcie_type = pci_pcie_type(dev);
diff --git a/include/linux/pci.h b/include/linux/pci.h
-index 0674161..de1fc24 100644
+index cd8aa6fce204..286d89e22738 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
-@@ -341,6 +341,8 @@ struct pci_dev {
- u8 pin; /* Interrupt pin this device uses */
- u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
- u32 pcie_devcap; /* Cached Device Capabilities Register */
-+ u32 pcie_devcap2; /* Cached Device Capabilities 2
-+ Register */
- unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
-
- struct pci_driver *driver; /* Driver bound to this device */
+@@ -333,6 +333,7 @@ struct pci_dev {
+ struct pci_dev *rcec; /* Associated RCEC device */
+ #endif
+ u32 devcap; /* PCIe Device Capabilities */
++ u32 devcap2; /* PCIe Device Capabilities 2 */
+ u8 pcie_cap; /* PCIe capability offset */
+ u8 msi_cap; /* MSI capability offset */
+ u8 msix_cap; /* MSI-X capability offset */
--
-2.7.4
+2.22.0