[PATCH iwl-next] ice: describe generic DPLL pins from firmware pin classification

@@ -4284,10 +4284,60 @@ static void ice_dpll_phase_range_set(struct dpll_pin_phase_adjust_range *range,
 	range->max = phase_adj;
 }
 
+/**
+ * ice_dpll_init_info_pin_generic_input - describe a generic input pin
+ * @pf: board private structure
+ * @pin: pin to describe
+ *
+ * Derive the pin type, board label and supported frequencies from the pin
+ * classification reported by firmware.
+ *
+ * Return:
+ * * 0 - success
+ * * negative - AQ failure
+ */
+static int
+ice_dpll_init_info_pin_generic_input(struct ice_pf *pf, struct ice_dpll_pin *pin)
+{
+	u8 type, caps, num;
+	const char *kind;
+	int ret;
+
+	ret = ice_aq_get_input_pin_cfg(&pf->hw, pin->idx, NULL, &type, &caps,
+				       NULL, NULL, NULL);
+	if (ret)
+		return ret;
+
+	if (type & ICE_AQC_GET_CGU_IN_CFG_TYPE_GPS) {
+		pin->prop.type = DPLL_PIN_TYPE_GNSS;
+		kind = "GNSS";
+	} else if (type & ICE_AQC_GET_CGU_IN_CFG_TYPE_PHY) {
+		pin->prop.type = DPLL_PIN_TYPE_MUX;
+		kind = "RCLK";
+	} else if (type & ICE_AQC_GET_CGU_IN_CFG_TYPE_EXTERNAL) {
+		pin->prop.type = DPLL_PIN_TYPE_EXT;
+		kind = "EXT";
+		if (caps & ICE_AQC_GET_CGU_IN_CFG_FLG1_ANYFREQ)
+			caps |= ICE_AQC_GET_CGU_IN_CFG_FLG1_1PPS_SUPP |
+				ICE_AQC_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP;
+	} else {
+		pin->prop.type = pin->freq == ICE_DPLL_PIN_GEN_RCLK_FREQ ?
+				 DPLL_PIN_TYPE_MUX : DPLL_PIN_TYPE_EXT;
+		kind = "IN";
+	}
+	snprintf(pin->label, sizeof(pin->label), "%s-%u", kind, pin->idx);
+	pin->prop.board_label = pin->label;
+	pin->prop.freq_supported =
+		ice_cgu_get_pin_freq_supp_by_caps(caps, &num);
+	pin->prop.freq_supported_num = num;
+
+	return 0;
+}
+
 /**
  * ice_dpll_init_info_pins_generic - initializes generic pins info
  * @pf: board private structure
- * @input: if input pins initialized
+ * @input: if we are initializing input pins
  *
  * Init information for generic pins, cache them in PF's pins structures.
  *

@@ -4298,13 +4348,10 @@ static void ice_dpll_phase_range_set(struct dpll_pin_phase_adjust_range *range,
 static int ice_dpll_init_info_pins_generic(struct ice_pf *pf, bool input)
 {
 	struct ice_dpll *de = &pf->dplls.eec, *dp = &pf->dplls.pps;
-	static const char labels[][sizeof("99")] = {
-		"0", "1", "2", "3", "4", "5", "6", "7", "8",
-		"9", "10", "11", "12", "13", "14", "15" };
 	u32 cap = DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE;
 	enum ice_dpll_pin_type pin_type;
-	int i, pin_num, ret = -EINVAL;
 	struct ice_dpll_pin *pins;
+	int i, pin_num, ret = 0;
 	u32 phase_adj_max;
 
 	if (input) {

@@ -4319,12 +4366,9 @@ static int ice_dpll_init_info_pins_generic(struct ice_pf *pf, bool input)
 		phase_adj_max = pf->dplls.output_phase_adj_max;
 		pin_type = ICE_DPLL_PIN_TYPE_OUTPUT;
 	}
-	if (pin_num > ARRAY_SIZE(labels))
-		return ret;
 
 	for (i = 0; i < pin_num; i++) {
 		pins[i].idx = i;
-		pins[i].prop.board_label = labels[i];
 		ice_dpll_phase_range_set(&pins[i].prop.phase_range,
 					 phase_adj_max);
 		pins[i].prop.capabilities = cap;

@@ -4332,12 +4376,16 @@ static int ice_dpll_init_info_pins_generic(struct ice_pf *pf, bool input)
 		ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL);
 		if (ret)
 			break;
-		if (input && pins[i].freq == ICE_DPLL_PIN_GEN_RCLK_FREQ)
-			pins[i].prop.type = DPLL_PIN_TYPE_MUX;
-		else
+		if (!input) {
+			snprintf(pins[i].label, sizeof(pins[i].label),
+				 "OUT-%u", pins[i].idx);
+			pins[i].prop.board_label = pins[i].label;
 			pins[i].prop.type = DPLL_PIN_TYPE_EXT;
-		if (!input)
 			continue;
+		}
+		ret = ice_dpll_init_info_pin_generic_input(pf, &pins[i]);
+		if (ret)
+			break;
 		ret = ice_aq_get_cgu_ref_prio(&pf->hw, de->dpll_idx, i,
 					      &de->input_prio[i]);
 		if (ret)

@@ -6,6 +6,7 @@
 
 #include "ice.h"
 
+#define ICE_DPLL_PIN_LABEL_LEN		16
 #define ICE_DPLL_RCLK_NUM_MAX	4
 #define ICE_DPLL_TXCLK_NUM_MAX	2
 #define E825_EXT_EREF_PIN_IDX	0

@@ -83,6 +84,7 @@ struct ice_dpll_pin {
 	bool active;
 	bool hidden;
 	enum ice_e825c_ref_clk tx_ref_src;
+	char label[ICE_DPLL_PIN_LABEL_LEN];
 };
 
 /** ice_dpll - store info required for DPLL control

@@ -6059,6 +6059,37 @@ ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num)
 	return t[pin].freq_supp;
 }
 
+/**
+ * ice_cgu_get_pin_freq_supp_by_caps - get supported frequencies from pin caps
+ * @caps: input pin capability flags from Get CGU Input Config
+ * @num: number of returned frequencies
+ *
+ * Return: array of supported frequencies, NULL if no fixed frequency is
+ * advertised.
+ */
+struct dpll_pin_frequency *
+ice_cgu_get_pin_freq_supp_by_caps(u8 caps, u8 *num)
+{
+	bool pps = caps & ICE_AQC_GET_CGU_IN_CFG_FLG1_1PPS_SUPP;
+	bool mhz = caps & ICE_AQC_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP;
+
+	if (pps && mhz) {
+		*num = ARRAY_SIZE(ice_cgu_pin_freq_common);
+		return ice_cgu_pin_freq_common;
+	}
+	if (pps) {
+		*num = ARRAY_SIZE(ice_cgu_pin_freq_1_hz);
+		return ice_cgu_pin_freq_1_hz;
+	}
+	if (mhz) {
+		*num = ARRAY_SIZE(ice_cgu_pin_freq_10_mhz);
+		return ice_cgu_pin_freq_10_mhz;
+	}
+	*num = 0;
+
+	return NULL;
+}
+
 /**
  * ice_cgu_get_pin_name - get pin's name
  * @hw: pointer to the hw struct

@@ -367,6 +367,8 @@ int ice_cgu_get_num_pins(struct ice_hw *hw, bool input);
 enum dpll_pin_type ice_cgu_get_pin_type(struct ice_hw *hw, u8 pin, bool input);
 struct dpll_pin_frequency *
 ice_cgu_get_pin_freq_supp(struct ice_hw *hw, u8 pin, bool input, u8 *num);
+struct dpll_pin_frequency *
+ice_cgu_get_pin_freq_supp_by_caps(u8 caps, u8 *num);
 const char *ice_cgu_get_pin_name(struct ice_hw *hw, u8 pin, bool input);
 int ice_get_cgu_state(struct ice_hw *hw, u8 dpll_idx,
 		      enum dpll_lock_status last_dpll_state, u8 *pin,