[PATCH v2 net-next] octeontx2-af: add new mbox to support sync cycle on rx path
From: Ratheesh Kannoth <rkannoth@marvell.com>
Date: 2026-07-15 04:13:07
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Subsystem:
marvell octeontx2 rvu admin function driver, networking drivers, the rest · Maintainers:
Sunil Goutham, Ratheesh Kannoth, Geetha sowjanya, Subbaraya Sundeep, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
From: Satha Rao <redacted> sync ensures that all packets that were in flight are flushed out to memory. This can be used to assist in the tearing down of an active RQ. To complete disabling RQs or disabling SMQ and its SQs, LF software send mbox to AF to complete RX_SW_SYNC. Signed-off-by: Satha Rao <redacted> Signed-off-by: Ratheesh Kannoth <rkannoth@marvell.com> --- .../net/ethernet/marvell/octeontx2/af/mbox.h | 1 + .../ethernet/marvell/octeontx2/af/rvu_nix.c | 20 +++++++++++++++++++ 2 files changed, 21 insertions(+)
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index f87cdf1b971d..92175de036d5 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h@@ -362,6 +362,7 @@ M(NIX_CPT_BP_ENABLE, 0x8020, nix_cpt_bp_enable, nix_bp_cfg_req, \ nix_bp_cfg_rsp) \ M(NIX_CPT_BP_DISABLE, 0x8021, nix_cpt_bp_disable, nix_bp_cfg_req, \ msg_rsp) \ +M(NIX_RX_SW_SYNC, 0x8022, nix_rx_sw_sync, msg_req, msg_rsp) \ M(NIX_READ_INLINE_IPSEC_CFG, 0x8023, nix_read_inline_ipsec_cfg, \ msg_req, nix_inline_ipsec_cfg) \ M(NIX_MCAST_GRP_CREATE, 0x802b, nix_mcast_grp_create, nix_mcast_grp_create_req, \
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 78667a0977c0..47e1a4e3392b 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c@@ -273,6 +273,8 @@ static void nix_rx_sync(struct rvu *rvu, int blkaddr) { int err; + mutex_lock(&rvu->rsrc_lock); + /* Sync all in flight RX packets to LLC/DRAM */ rvu_write64(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0)); err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true);
@@ -289,6 +291,8 @@ static void nix_rx_sync(struct rvu *rvu, int blkaddr) err = rvu_poll_reg(rvu, blkaddr, NIX_AF_RX_SW_SYNC, BIT_ULL(0), true); if (err) dev_err(rvu->dev, "SYNC2: NIX RX software sync failed\n"); + + mutex_unlock(&rvu->rsrc_lock); } static bool is_valid_txschq(struct rvu *rvu, int blkaddr,
@@ -6324,6 +6328,22 @@ int rvu_mbox_handler_nix_bandprof_get_hwinfo(struct rvu *rvu, struct msg_req *re return 0; } +int rvu_mbox_handler_nix_rx_sw_sync(struct rvu *rvu, struct msg_req *req, + struct msg_rsp *rsp) +{ + int blkaddr; + + /* NIX_AF_RX_SW_SYNC is global per NIX block; nix_rx_sync() serializes + * access under rvu->rsrc_lock across mbox and teardown paths. + */ + blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, req->hdr.pcifunc); + if (blkaddr < 0) + return NIX_AF_ERR_AF_LF_INVALID; + + nix_rx_sync(rvu, blkaddr); + return 0; +} + static struct nix_mcast_grp_elem *rvu_nix_mcast_find_grp_elem(struct nix_mcast_grp *mcast_grp, u32 mcast_grp_idx) {
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2.43.0