Changes in v3:
v3:
1) List the names of SoCs mt8188 and mt8195 in correct order as
AngeloGioacchino Del Regno's comment.
2) Add patch version info as Krzysztof Kozlowski'comment.
v2:
1) Delete patch 'stmmac: dwmac-mediatek: add support for mt8188' as
Krzysztof Kozlowski's comment.
2) Update patch 'dt-bindings: net: mediatek-dwmac: add support for
mt8188' as Krzysztof Kozlowski's comment.
3) Add clk_csr property to fix warning ('clk_csr' was unexpected) when
runnig 'make dtbs_check'.
v1:
1) Add ethernet driver entry for mt8188.
2) Add binding document for ethernet on mt8188.
Jianguo Zhang (2):
dt-bindings: net: mediatek-dwmac: add support for mt8188
dt-bindings: net: snps,dwmac: add clk_csr property
.../devicetree/bindings/net/mediatek-dwmac.yaml | 10 ++++++++--
Documentation/devicetree/bindings/net/snps,dwmac.yaml | 5 +++++
2 files changed, 13 insertions(+), 2 deletions(-)
--
2.25.1
@@ -288,6 +288,11 @@ properties:is supported. For example, this is used in case of SGMII andMAC2MAC connection.+clk_csr:+$ref:/schemas/types.yaml#/definitions/uint32+description:+Frequency division factor for MDC clock.+mdio:$ref:mdio.yaml#unevaluatedProperties:false
@@ -74,7 +80,7 @@ properties:or will round down. Range 0~31*170.For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,or will round down. Range 0~31*550.-For MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,+For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,or will round down. Range 0~31*290.mediatek,rx-delay-ps:
@@ -84,7 +90,7 @@ properties:or will round down. Range 0~31*170.For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,or will round down. Range 0~31*550.-For MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple+For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multipleof 290, or will round down. Range 0~31*290.mediatek,rmii-rxc:
@@ -288,6 +288,11 @@ properties:is supported. For example, this is used in case of SGMII andMAC2MAC connection.+clk_csr:
No underscores in node names. Missing vendor prefix.
We will remane the property name 'clk_csr' as 'snps,clk-csr' and
another driver patch is needed to align the name used in driver with
the new name.
quoted
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Frequency division factor for MDC clock.
Can't common clock framework do the job? What is the MDC clock?
MDC clock is used for ethernet MAC accessing PHY register by MDIO bus.
There is frequency divider designed in ethernet internal HW to ensure
that ethernet can get correct frequency of MDC colck and the vlaue of
frequency divider can be got from DTS.
@@ -288,6 +288,11 @@ properties:is supported. For example, this is used in case of SGMII andMAC2MAC connection.+clk_csr:
No underscores in node names. Missing vendor prefix.
We will remane the property name 'clk_csr' as 'snps,clk-csr' and
another driver patch is needed to align the name used in driver with
the new name.
You did not say anything that you document existing property. Commit msg
*must* explain why you are doing stuff in commit body.
We should not be asking for this and for reason of clk_csr.
Best regards,
Krzysztof
@@ -288,6 +288,11 @@ properties:is supported. For example, this is used in case of SGMII
and
MAC2MAC connection.
+ clk_csr:
No underscores in node names. Missing vendor prefix.
We will remane the property name 'clk_csr' as 'snps,clk-csr' and
another driver patch is needed to align the name used in driver
with
the new name.
You did not say anything that you document existing property. Commit
msg
*must* explain why you are doing stuff in commit body.
We should not be asking for this and for reason of clk_csr.
We will explain the background that why we document 'clk_csr' property
in binding file in commit message in next version patches.