From: Biju Das <biju.das.jz@bp.renesas.com> Date: 2021-10-09 19:08:10
The DMAC and EMAC blocks of Gigabit Ethernet IP found on RZ/G2L SoC are
similar to the R-Car Ethernet AVB IP.
The Gigabit Ethernet IP consists of Ethernet controller (E-MAC), Internal
TCP/IP Offload Engine (TOE) and Dedicated Direct memory access controller
(DMAC).
With a few changes in the driver we can support both IPs.
This patch series is aims to add functional support for Gigabit Ethernet driver
by filling all the stubs except set_features.
set_feature patch will send as separate RFC patch along with rx_checksum
patch, as it needs detailed discussion related to HW checksum.
Ref:-
https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=557655
RFC->V1:
* Removed patch#3 will send it as RFC
* Removed rx_csum functionality from patch#7, will send it as RFC
* Renamed "nc_queue" -> "nc_queues"
* Separated the comment patch into 2 separate patches.
* Documented PFRI register bit
* Added Sergy's Rb tag
RFC changes:
* used ALIGN macro for calculating the value for max_rx_len.
* used rx_max_buf_size instead of rx_2k_buffers feature bit.
* moved struct ravb_rx_desc *gbeth_rx_ring near to ravb_private::rx_ring
and allocating it for 1 RX queue.
* Started using gbeth_rx_ring instead of gbeth_rx_ring[q].
* renamed ravb_alloc_rx_desc to ravb_alloc_rx_desc_rcar
* renamed ravb_rx_ring_free to ravb_rx_ring_free_rcar
* renamed ravb_rx_ring_format to ravb_rx_ring_format_rcar
* renamed ravb_rcar_rx to ravb_rx_rcar
* renamed "tsrq" variable
* Updated the comments
Biju Das (14):
ravb: Use ALIGN macro for max_rx_len
ravb: Add rx_max_buf_size to struct ravb_hw_info
ravb: Fillup ravb_alloc_rx_desc_gbeth() stub
ravb: Fillup ravb_rx_ring_free_gbeth() stub
ravb: Fillup ravb_rx_ring_format_gbeth() stub
ravb: Fillup ravb_rx_gbeth() stub
ravb: Add carrier_counters to struct ravb_hw_info
ravb: Add support to retrieve stats for GbEthernet
ravb: Rename "tsrq" variable
ravb: Optimize ravb_emac_init_gbeth function
ravb: Rename "nc_queue" feature bit
ravb: Document PFRI register bit
ravb: Update EMAC configuration mode comment
ravb: Fix typo AVB->DMAC
drivers/net/ethernet/renesas/ravb.h | 17 +-
drivers/net/ethernet/renesas/ravb_main.c | 325 +++++++++++++++++++----
2 files changed, 291 insertions(+), 51 deletions(-)
--
2.17.1
From: Biju Das <biju.das.jz@bp.renesas.com> Date: 2021-10-09 19:08:17
R-Car AVB-DMAC has maximum 2K size on RX buffer, whereas on RZ/G2L
it is 8K. We need to allow for changing the MTU within the limit
of the maximum size of a descriptor.
Add a rx_max_buf_size variable to struct ravb_hw_info to handle
this difference.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Sergey Shtylyov <redacted>
---
RFC->V1:
* No Change. Added Sergey's Rb tag
---
drivers/net/ethernet/renesas/ravb.h | 1 +
drivers/net/ethernet/renesas/ravb_main.c | 5 ++++-
2 files changed, 5 insertions(+), 1 deletion(-)
From: Biju Das <biju.das.jz@bp.renesas.com> Date: 2021-10-09 19:08:21
Fillup ravb_alloc_rx_desc_gbeth() function to support RZ/G2L.
This patch also renames ravb_alloc_rx_desc to ravb_alloc_rx_desc_rcar
to be consistent with the naming convention used in sh_eth driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Sergey Shtylyov <redacted>
---
RFC->V1:
* No Change. Added Sergey's Rb tag
RFC:
* started allocating 1 rx queue for "gbeth_rx_ring"
* Moved gbeth_rx_ring near to rx_ring in priv structure
* renamed ravb_alloc_rx_desc to ravb_alloc_rx_desc_rcar
---
drivers/net/ethernet/renesas/ravb.h | 1 +
drivers/net/ethernet/renesas/ravb_main.c | 30 ++++++++++++++++++------
2 files changed, 24 insertions(+), 7 deletions(-)
From: Biju Das <biju.das.jz@bp.renesas.com> Date: 2021-10-09 19:08:23
Fillup ravb_rx_ring_free_gbeth() function to support RZ/G2L.
This patch also renames ravb_rx_ring_free to ravb_rx_ring_free_rcar
to be consistent with the naming convention used in sh_eth driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Sergey Shtylyov <redacted>
---
RFC->V1:
* No change. Added Sergey's Rb tag.
RFC Changes:
* moved "gbeth_rx_ring" to previous patch
* started using "gbeth_rx_ring" instead of gbeth_rx_ring[q].
* renamed ravb_rx_ring_free to ravb_rx_ring_free_rcar
---
drivers/net/ethernet/renesas/ravb_main.c | 28 ++++++++++++++++++++----
1 file changed, 24 insertions(+), 4 deletions(-)
@@ -236,10 +236,30 @@ static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)staticvoidravb_rx_ring_free_gbeth(structnet_device*ndev,intq){-/* Place holder */+structravb_private*priv=netdev_priv(ndev);+unsignedintring_size;+unsignedinti;++if(!priv->gbeth_rx_ring)+return;++for(i=0;i<priv->num_rx_ring[q];i++){+structravb_rx_desc*desc=&priv->gbeth_rx_ring[i];++if(!dma_mapping_error(ndev->dev.parent,+le32_to_cpu(desc->dptr)))+dma_unmap_single(ndev->dev.parent,+le32_to_cpu(desc->dptr),+GBETH_RX_BUFF_MAX,+DMA_FROM_DEVICE);+}+ring_size=sizeof(structravb_rx_desc)*(priv->num_rx_ring[q]+1);+dma_free_coherent(ndev->dev.parent,ring_size,priv->gbeth_rx_ring,+priv->rx_desc_dma[q]);+priv->gbeth_rx_ring=NULL;}-staticvoidravb_rx_ring_free(structnet_device*ndev,intq)+staticvoidravb_rx_ring_free_rcar(structnet_device*ndev,intq){structravb_private*priv=netdev_priv(ndev);unsignedintring_size;
@@ -2189,7 +2209,7 @@ static int ravb_mdio_release(struct ravb_private *priv)}staticconststructravb_hw_inforavb_gen3_hw_info={-.rx_ring_free=ravb_rx_ring_free,+.rx_ring_free=ravb_rx_ring_free_rcar,.rx_ring_format=ravb_rx_ring_format,.alloc_rx_desc=ravb_alloc_rx_desc_rcar,.receive=ravb_rcar_rx,
From: Biju Das <biju.das.jz@bp.renesas.com> Date: 2021-10-09 19:08:28
Fillup ravb_rx_ring_format_gbeth() function to support RZ/G2L.
This patch also renames ravb_rx_ring_format to ravb_rx_ring_format_rcar
to be consistent with the naming convention used in sh_eth driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Sergey Shtylyov <redacted>
---
RFC->V1:
* No change. Added Sergey's Rb tag.
RFC changes:
* Started using gbeth_rx_ring instead of gbeth_rx_ring[q].
* renamed ravb_rx_ring_format to ravb_rx_ring_format_rcar
---
drivers/net/ethernet/renesas/ravb.h | 1 +
drivers/net/ethernet/renesas/ravb_main.c | 34 +++++++++++++++++++++---
2 files changed, 31 insertions(+), 4 deletions(-)
@@ -327,10 +327,36 @@ static void ravb_ring_free(struct net_device *ndev, int q)staticvoidravb_rx_ring_format_gbeth(structnet_device*ndev,intq){-/* Place holder */+structravb_private*priv=netdev_priv(ndev);+structravb_rx_desc*rx_desc;+unsignedintrx_ring_size;+dma_addr_tdma_addr;+unsignedinti;++rx_ring_size=sizeof(*rx_desc)*priv->num_rx_ring[q];+memset(priv->gbeth_rx_ring,0,rx_ring_size);+/* Build RX ring buffer */+for(i=0;i<priv->num_rx_ring[q];i++){+/* RX descriptor */+rx_desc=&priv->gbeth_rx_ring[i];+rx_desc->ds_cc=cpu_to_le16(GBETH_RX_DESC_DATA_SIZE);+dma_addr=dma_map_single(ndev->dev.parent,priv->rx_skb[q][i]->data,+GBETH_RX_BUFF_MAX,+DMA_FROM_DEVICE);+/* We just set the data size to 0 for a failed mapping which+*shouldpreventDMAfromhappening...+*/+if(dma_mapping_error(ndev->dev.parent,dma_addr))+rx_desc->ds_cc=cpu_to_le16(0);+rx_desc->dptr=cpu_to_le32(dma_addr);+rx_desc->die_dt=DT_FEMPTY;+}+rx_desc=&priv->gbeth_rx_ring[i];+rx_desc->dptr=cpu_to_le32((u32)priv->rx_desc_dma[q]);+rx_desc->die_dt=DT_LINKFIX;/* type */}-staticvoidravb_rx_ring_format(structnet_device*ndev,intq)+staticvoidravb_rx_ring_format_rcar(structnet_device*ndev,intq){structravb_private*priv=netdev_priv(ndev);structravb_ex_rx_desc*rx_desc;
@@ -2210,7 +2236,7 @@ static int ravb_mdio_release(struct ravb_private *priv)staticconststructravb_hw_inforavb_gen3_hw_info={.rx_ring_free=ravb_rx_ring_free_rcar,-.rx_ring_format=ravb_rx_ring_format,+.rx_ring_format=ravb_rx_ring_format_rcar,.alloc_rx_desc=ravb_alloc_rx_desc_rcar,.receive=ravb_rcar_rx,.set_rate=ravb_set_rate_rcar,
From: Biju Das <biju.das.jz@bp.renesas.com> Date: 2021-10-09 19:08:34
Fillup ravb_rx_gbeth() function to support RZ/G2L.
This patch also renames ravb_rcar_rx to ravb_rx_rcar to be
consistent with the naming convention used in sh_eth driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
RFC->v1:
* Removed ravb_rx_csum_gbeth() and will post this as seperate RFC
patch.
---
drivers/net/ethernet/renesas/ravb.h | 5 +
drivers/net/ethernet/renesas/ravb_main.c | 146 ++++++++++++++++++++++-
2 files changed, 146 insertions(+), 5 deletions(-)
@@ -734,15 +734,151 @@ static void ravb_rx_csum(struct sk_buff *skb)skb_trim(skb,skb->len-sizeof(__sum16));}+staticstructsk_buff*ravb_get_skb_gbeth(structnet_device*ndev,intentry,+structravb_rx_desc*desc)+{+structravb_private*priv=netdev_priv(ndev);+structsk_buff*skb;++skb=priv->rx_skb[RAVB_BE][entry];+priv->rx_skb[RAVB_BE][entry]=NULL;+dma_unmap_single(ndev->dev.parent,le32_to_cpu(desc->dptr),+ALIGN(GBETH_RX_BUFF_MAX,16),DMA_FROM_DEVICE);++returnskb;+}+/* Packet receive function for Gigabit Ethernet */staticboolravb_rx_gbeth(structnet_device*ndev,int*quota,intq){-/* Place holder */-returntrue;+structravb_private*priv=netdev_priv(ndev);+conststructravb_hw_info*info=priv->info;+structnet_device_stats*stats;+structravb_rx_desc*desc;+structsk_buff*skb;+dma_addr_tdma_addr;+u8desc_status;+intboguscnt;+u16pkt_len;+u8die_dt;+intentry;+intlimit;++entry=priv->cur_rx[q]%priv->num_rx_ring[q];+boguscnt=priv->dirty_rx[q]+priv->num_rx_ring[q]-priv->cur_rx[q];+stats=&priv->stats[q];++boguscnt=min(boguscnt,*quota);+limit=boguscnt;+desc=&priv->gbeth_rx_ring[entry];+while(desc->die_dt!=DT_FEMPTY){+/* Descriptor type must be checked before all other reads */+dma_rmb();+desc_status=desc->msc;+pkt_len=le16_to_cpu(desc->ds_cc)&RX_DS;++if(--boguscnt<0)+break;++/* We use 0-byte descriptors to mark the DMA mapping errors */+if(!pkt_len)+continue;++if(desc_status&MSC_MC)+stats->multicast++;++if(desc_status&(MSC_CRC|MSC_RFE|MSC_RTSF|MSC_RTLF|MSC_CEEF)){+stats->rx_errors++;+if(desc_status&MSC_CRC)+stats->rx_crc_errors++;+if(desc_status&MSC_RFE)+stats->rx_frame_errors++;+if(desc_status&(MSC_RTLF|MSC_RTSF))+stats->rx_length_errors++;+if(desc_status&MSC_CEEF)+stats->rx_missed_errors++;+}else{+die_dt=desc->die_dt&0xF0;+switch(die_dt){+caseDT_FSINGLE:+skb=ravb_get_skb_gbeth(ndev,entry,desc);+skb_put(skb,pkt_len);+skb->protocol=eth_type_trans(skb,ndev);+napi_gro_receive(&priv->napi[q],skb);+stats->rx_packets++;+stats->rx_bytes+=pkt_len;+break;+caseDT_FSTART:+priv->rx_1st_skb=ravb_get_skb_gbeth(ndev,entry,desc);+skb_put(priv->rx_1st_skb,pkt_len);+break;+caseDT_FMID:+skb=ravb_get_skb_gbeth(ndev,entry,desc);+skb_copy_to_linear_data_offset(priv->rx_1st_skb,+priv->rx_1st_skb->len,+skb->data,+pkt_len);+skb_put(priv->rx_1st_skb,pkt_len);+dev_kfree_skb(skb);+break;+caseDT_FEND:+skb=ravb_get_skb_gbeth(ndev,entry,desc);+skb_copy_to_linear_data_offset(priv->rx_1st_skb,+priv->rx_1st_skb->len,+skb->data,+pkt_len);+skb_put(priv->rx_1st_skb,pkt_len);+dev_kfree_skb(skb);+priv->rx_1st_skb->protocol=+eth_type_trans(priv->rx_1st_skb,ndev);+napi_gro_receive(&priv->napi[q],+priv->rx_1st_skb);+stats->rx_packets++;+stats->rx_bytes+=priv->rx_1st_skb->len;+break;+}+}++entry=(++priv->cur_rx[q])%priv->num_rx_ring[q];+desc=&priv->gbeth_rx_ring[entry];+}++/* Refill the RX ring buffers. */+for(;priv->cur_rx[q]-priv->dirty_rx[q]>0;priv->dirty_rx[q]++){+entry=priv->dirty_rx[q]%priv->num_rx_ring[q];+desc=&priv->gbeth_rx_ring[entry];+desc->ds_cc=cpu_to_le16(GBETH_RX_DESC_DATA_SIZE);++if(!priv->rx_skb[q][entry]){+skb=netdev_alloc_skb(ndev,info->max_rx_len);+if(!skb)+break;+ravb_set_buffer_align(skb);+dma_addr=dma_map_single(ndev->dev.parent,+skb->data,+GBETH_RX_BUFF_MAX,+DMA_FROM_DEVICE);+skb_checksum_none_assert(skb);+/* We just set the data size to 0 for a failed mapping+*whichshouldpreventDMAfromhappening...+*/+if(dma_mapping_error(ndev->dev.parent,dma_addr))+desc->ds_cc=cpu_to_le16(0);+desc->dptr=cpu_to_le32(dma_addr);+priv->rx_skb[q][entry]=skb;+}+/* Descriptor type must be set after all the above writes */+dma_wmb();+desc->die_dt=DT_FEMPTY;+}++*quota-=limit-(++boguscnt);++returnboguscnt<=0;}/* Packet receive function for Ethernet AVB */-staticboolravb_rcar_rx(structnet_device*ndev,int*quota,intq)+staticboolravb_rx_rcar(structnet_device*ndev,int*quota,intq){structravb_private*priv=netdev_priv(ndev);conststructravb_hw_info*info=priv->info;
From: Biju Das <biju.das.jz@bp.renesas.com> Date: 2021-10-09 19:08:36
RZ/G2L E-MAC supports carrier counters.
Add a carrier_counter hw feature bit to struct ravb_hw_info
to add this feature only for RZ/G2L.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Sergey Shtylyov <redacted>
---
RFC->V1:
* Moved carrier_counters near to tx_counters.
* removed CXR55 and CXR56 registers as it is rx related registers.
* Retained Sergey's Rb tag as it is trivial change.
RFC changes:
* Added Sergey's Rb tag.
---
drivers/net/ethernet/renesas/ravb.h | 3 +++
drivers/net/ethernet/renesas/ravb_main.c | 8 ++++++++
2 files changed, 11 insertions(+)
@@ -200,6 +200,8 @@ enum ravb_reg {MAHR=0x05c0,MALR=0x05c8,TROCR=0x0700,/* R-Car Gen3 and RZ/G2L only */+CXR41=0x0708,/* RZ/G2L only */+CXR42=0x0710,/* RZ/G2L only */CEFCR=0x0740,FRECR=0x0748,TSFRCR=0x0750,
@@ -1021,6 +1023,7 @@ struct ravb_hw_info {/* hardware features */unsignedinternal_delay:1;/* AVB-DMAC has internal delays */unsignedtx_counters:1;/* E-MAC has TX counters */+unsignedcarrier_counters:1;/* E-MAC has carrier counters */unsignedmulti_irqs:1;/* AVB-DMAC and E-MAC has multiple irqs */unsignedgptp:1;/* AVB-DMAC has gPTP support */unsignedccc_gac:1;/* AVB-DMAC has gPTP support active in config mode */
From: Biju Das <biju.das.jz@bp.renesas.com> Date: 2021-10-09 19:08:42
Rename the variable "tsrq" with "tccr_mask" as we are passing
TCCR mask to the ravb_wait() function.
There is no functional change.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Suggested-by: Sergey Shtylyov <redacted>
Reviewed-by: Sergey Shtylyov <redacted>
---
RFC->v1:
* No Change. Added Sergey's Rb tag.
RFC changes:
* New patch.
---
drivers/net/ethernet/renesas/ravb.h | 2 +-
drivers/net/ethernet/renesas/ravb_main.c | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
@@ -1021,7 +1021,7 @@ static int ravb_stop_dma(struct net_device *ndev)interror;/* Wait for stopping the hardware TX process */-error=ravb_wait(ndev,TCCR,info->tsrq,0);+error=ravb_wait(ndev,TCCR,info->tccr_mask,0);if(error)returnerror;
From: Biju Das <biju.das.jz@bp.renesas.com> Date: 2021-10-09 19:08:57
Rename the feature bit "nc_queue" with "nc_queues" as AVB DMAC has
RX and TX NC queues.
There is no functional change.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Suggested-by: Sergey Shtylyov <redacted>
---
V1:
* New patch.
---
drivers/net/ethernet/renesas/ravb.h | 2 +-
drivers/net/ethernet/renesas/ravb_main.c | 36 ++++++++++++------------
2 files changed, 19 insertions(+), 19 deletions(-)
@@ -1027,7 +1027,7 @@ struct ravb_hw_info {unsignedmulti_irqs:1;/* AVB-DMAC and E-MAC has multiple irqs */unsignedgptp:1;/* AVB-DMAC has gPTP support */unsignedccc_gac:1;/* AVB-DMAC has gPTP support active in config mode */-unsignednc_queue:1;/* AVB-DMAC has NC queue */+unsignednc_queues:1;/* AVB-DMAC has RX and TX NC queues */unsignedmagic_pkt:1;/* E-MAC supports magic packet detection */unsignedhalf_duplex:1;/* E-MAC supports half duplex mode */};
@@ -1643,7 +1643,7 @@ static int ravb_set_ringparam(struct net_device *ndev,/* Free all the skb's in the RX queue and the DMA buffers. */ravb_ring_free(ndev,RAVB_BE);-if(info->nc_queue)+if(info->nc_queues)ravb_ring_free(ndev,RAVB_NC);}
@@ -1763,7 +1763,7 @@ static int ravb_open(struct net_device *ndev)interror;napi_enable(&priv->napi[RAVB_BE]);-if(info->nc_queue)+if(info->nc_queues)napi_enable(&priv->napi[RAVB_NC]);if(!info->multi_irqs){
@@ -1838,7 +1838,7 @@ static int ravb_open(struct net_device *ndev)out_free_irq:free_irq(ndev->irq,ndev);out_napi_off:-if(info->nc_queue)+if(info->nc_queues)napi_disable(&priv->napi[RAVB_NC]);napi_disable(&priv->napi[RAVB_BE]);returnerror;
@@ -2169,13 +2169,13 @@ static int ravb_close(struct net_device *ndev)}free_irq(ndev->irq,ndev);-if(info->nc_queue)+if(info->nc_queues)napi_disable(&priv->napi[RAVB_NC]);napi_disable(&priv->napi[RAVB_BE]);/* Free all the skb's in the RX queue and the DMA buffers. */ravb_ring_free(ndev,RAVB_BE);-if(info->nc_queue)+if(info->nc_queues)ravb_ring_free(ndev,RAVB_NC);return0;
From: Biju Das <biju.das.jz@bp.renesas.com> Date: 2021-10-09 19:09:00
Fix the typo AVB->DMAC in comment, as the code following the comment
is for DMAC on Gigabit Ethernet IP.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Suggested-by: Sergey Shtylyov <redacted>
---
V1:
* New patch.
---
drivers/net/ethernet/renesas/ravb_main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
@@ -587,7 +587,7 @@ static int ravb_dmac_init_gbeth(struct net_device *ndev)/* Descriptor format */ravb_ring_format(ndev,RAVB_BE);-/* Set AVB RX */+/* Set DMAC RX */ravb_write(ndev,0x60000000,RCR);/* Set Max Frame Length (RTC) */
The DMAC and EMAC blocks of Gigabit Ethernet IP found on RZ/G2L SoC are
similar to the R-Car Ethernet AVB IP.
The Gigabit Ethernet IP consists of Ethernet controller (E-MAC), Internal
TCP/IP Offload Engine (TOE) and Dedicated Direct memory access controller
(DMAC).
With a few changes in the driver we can support both IPs.
This patch series is aims to add functional support for Gigabit Ethernet driver
by filling all the stubs except set_features.
set_feature patch will send as separate RFC patch along with rx_checksum
patch, as it needs detailed discussion related to HW checksum.
Ref:-
https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=557655
RFC->V1:
* Removed patch#3 will send it as RFC
* Removed rx_csum functionality from patch#7, will send it as RFC
* Renamed "nc_queue" -> "nc_queues"
* Separated the comment patch into 2 separate patches.
* Documented PFRI register bit
* Added Sergy's Rb tag
It's Sergey. :-)
RFC changes:
* used ALIGN macro for calculating the value for max_rx_len.
* used rx_max_buf_size instead of rx_2k_buffers feature bit.
* moved struct ravb_rx_desc *gbeth_rx_ring near to ravb_private::rx_ring
and allocating it for 1 RX queue.
* Started using gbeth_rx_ring instead of gbeth_rx_ring[q].
* renamed ravb_alloc_rx_desc to ravb_alloc_rx_desc_rcar
* renamed ravb_rx_ring_free to ravb_rx_ring_free_rcar
* renamed ravb_rx_ring_format to ravb_rx_ring_format_rcar
* renamed ravb_rcar_rx to ravb_rx_rcar
* renamed "tsrq" variable
* Updated the comments
Biju Das (14):
ravb: Use ALIGN macro for max_rx_len
ravb: Add rx_max_buf_size to struct ravb_hw_info
ravb: Fillup ravb_alloc_rx_desc_gbeth() stub
ravb: Fillup ravb_rx_ring_free_gbeth() stub
ravb: Fillup ravb_rx_ring_format_gbeth() stub
ravb: Fillup ravb_rx_gbeth() stub
ravb: Add carrier_counters to struct ravb_hw_info
ravb: Add support to retrieve stats for GbEthernet
ravb: Rename "tsrq" variable
ravb: Optimize ravb_emac_init_gbeth function
ravb: Rename "nc_queue" feature bit
ravb: Document PFRI register bit
ravb: Update EMAC configuration mode comment
ravb: Fix typo AVB->DMAC
drivers/net/ethernet/renesas/ravb.h | 17 +-
drivers/net/ethernet/renesas/ravb_main.c | 325 +++++++++++++++++++----
2 files changed, 291 insertions(+), 51 deletions(-)
DaveM, I'm going to review this patch series (starting on Monday). Is that acceptable forewarning? :-)
MBR, Sergey
From: Biju Das <biju.das.jz@bp.renesas.com> Date: 2021-10-10 07:27:19
Hi Sergey,
Subject: Re: [PATCH 00/14] Add functional support for Gigabit Ethernet
driver
On 10/9/21 10:07 PM, Biju Das wrote:
quoted
The DMAC and EMAC blocks of Gigabit Ethernet IP found on RZ/G2L SoC
are similar to the R-Car Ethernet AVB IP.
The Gigabit Ethernet IP consists of Ethernet controller (E-MAC),
Internal TCP/IP Offload Engine (TOE) and Dedicated Direct memory
access controller (DMAC).
With a few changes in the driver we can support both IPs.
This patch series is aims to add functional support for Gigabit
Ethernet driver by filling all the stubs except set_features.
set_feature patch will send as separate RFC patch along with
rx_checksum patch, as it needs detailed discussion related to HW
checksum.
quoted
Ref:-
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
hwork.kernel.org%2Fproject%2Flinux-renesas-soc%2Flist%2F%3Fseries%3D55
7655&data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7C25bc7b9155d8402
a191808d98b5ae62f%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C6376940
44814904836%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMz
IiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Vktj5v0GvrNf%2BDNIFs
e6xjCUm6OjtzwHvK3q8aG1E5Y%3D&reserved=0
RFC->V1:
* Removed patch#3 will send it as RFC
* Removed rx_csum functionality from patch#7, will send it as RFC
* Renamed "nc_queue" -> "nc_queues"
* Separated the comment patch into 2 separate patches.
* Documented PFRI register bit
* Added Sergy's Rb tag
It's Sergey. :-)
My Bad. Sorry will taken care this in future. I need to send V2, as accidentally I have added 2 macros in patch #6
As part of RFC discussion into v1. I will send V2 to remove this.
Regards,
Biju
quoted
RFC changes:
* used ALIGN macro for calculating the value for max_rx_len.
* used rx_max_buf_size instead of rx_2k_buffers feature bit.
* moved struct ravb_rx_desc *gbeth_rx_ring near to
ravb_private::rx_ring
quoted
and allocating it for 1 RX queue.
* Started using gbeth_rx_ring instead of gbeth_rx_ring[q].
* renamed ravb_alloc_rx_desc to ravb_alloc_rx_desc_rcar
* renamed ravb_rx_ring_free to ravb_rx_ring_free_rcar
* renamed ravb_rx_ring_format to ravb_rx_ring_format_rcar
* renamed ravb_rcar_rx to ravb_rx_rcar
* renamed "tsrq" variable
* Updated the comments
Biju Das (14):
ravb: Use ALIGN macro for max_rx_len
ravb: Add rx_max_buf_size to struct ravb_hw_info
ravb: Fillup ravb_alloc_rx_desc_gbeth() stub
ravb: Fillup ravb_rx_ring_free_gbeth() stub
ravb: Fillup ravb_rx_ring_format_gbeth() stub
ravb: Fillup ravb_rx_gbeth() stub
ravb: Add carrier_counters to struct ravb_hw_info
ravb: Add support to retrieve stats for GbEthernet
ravb: Rename "tsrq" variable
ravb: Optimize ravb_emac_init_gbeth function
ravb: Rename "nc_queue" feature bit
ravb: Document PFRI register bit
ravb: Update EMAC configuration mode comment
ravb: Fix typo AVB->DMAC
drivers/net/ethernet/renesas/ravb.h | 17 +-
drivers/net/ethernet/renesas/ravb_main.c | 325
+++++++++++++++++++----
2 files changed, 291 insertions(+), 51 deletions(-)
DaveM, I'm going to review this patch series (starting on Monday). Is
that acceptable forewarning? :-)
MBR, Sergey
The DMAC and EMAC blocks of Gigabit Ethernet IP found on RZ/G2L SoC
are similar to the R-Car Ethernet AVB IP.
The Gigabit Ethernet IP consists of Ethernet controller (E-MAC),
Internal TCP/IP Offload Engine (TOE) and Dedicated Direct memory
access controller (DMAC).
With a few changes in the driver we can support both IPs.
This patch series is aims to add functional support for Gigabit
Ethernet driver by filling all the stubs except set_features.
set_feature patch will send as separate RFC patch along with
rx_checksum patch, as it needs detailed discussion related to HW
checksum.
quoted
Ref:-
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
hwork.kernel.org%2Fproject%2Flinux-renesas-soc%2Flist%2F%3Fseries%3D55
7655&data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7C25bc7b9155d8402
a191808d98b5ae62f%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C6376940
44814904836%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMz
IiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Vktj5v0GvrNf%2BDNIFs
e6xjCUm6OjtzwHvK3q8aG1E5Y%3D&reserved=0
RFC->V1:
* Removed patch#3 will send it as RFC
* Removed rx_csum functionality from patch#7, will send it as RFC
* Renamed "nc_queue" -> "nc_queues"
* Separated the comment patch into 2 separate patches.
* Documented PFRI register bit
* Added Sergy's Rb tag
It's Sergey. :-)
My Bad. Sorry will taken care this in future. I need to send V2, as accidentally I have added 2 macros in patch #6
As part of RFC discussion into v1. I will send V2 to remove this.
I'm not seeing patches #2, #4, and #9 in my inboxes... :-/
The DMAC and EMAC blocks of Gigabit Ethernet IP found on RZ/G2L SoC
are similar to the R-Car Ethernet AVB IP.
The Gigabit Ethernet IP consists of Ethernet controller (E-MAC),
Internal TCP/IP Offload Engine (TOE) and Dedicated Direct memory
access controller (DMAC).
With a few changes in the driver we can support both IPs.
This patch series is aims to add functional support for Gigabit
Ethernet driver by filling all the stubs except set_features.
set_feature patch will send as separate RFC patch along with
rx_checksum patch, as it needs detailed discussion related to HW
checksum.
quoted
Ref:-
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
hwork.kernel.org%2Fproject%2Flinux-renesas-soc%2Flist%2F%3Fseries%3D55
7655&data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7C25bc7b9155d8402
a191808d98b5ae62f%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C6376940
44814904836%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMz
IiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Vktj5v0GvrNf%2BDNIFs
e6xjCUm6OjtzwHvK3q8aG1E5Y%3D&reserved=0
RFC->V1:
* Removed patch#3 will send it as RFC
* Removed rx_csum functionality from patch#7, will send it as RFC
* Renamed "nc_queue" -> "nc_queues"
* Separated the comment patch into 2 separate patches.
* Documented PFRI register bit
* Added Sergy's Rb tag
It's Sergey. :-)
My Bad. Sorry will taken care this in future. I need to send V2, as
accidentally I have added 2 macros in patch #6
As part of RFC discussion into v1. I will send V2 to remove this.
I'm not seeing patches #2, #4, and #9 in my inboxes... :-/
Seeing them now in the linux-renesas-soc folder in the GMail account. But
they should have landed on the OMP account too. :-/
From: Biju Das <biju.das.jz@bp.renesas.com> Date: 2021-10-10 09:25:18
Hi Sergey,
Subject: Re: [PATCH 00/14] Add functional support for Gigabit Ethernet
driver
On 10.10.2021 12:13, Sergey Shtylyov wrote:
[...]
quoted
quoted
quoted
quoted
The DMAC and EMAC blocks of Gigabit Ethernet IP found on RZ/G2L SoC
are similar to the R-Car Ethernet AVB IP.
The Gigabit Ethernet IP consists of Ethernet controller (E-MAC),
Internal TCP/IP Offload Engine (TOE) and Dedicated Direct memory
access controller (DMAC).
With a few changes in the driver we can support both IPs.
This patch series is aims to add functional support for Gigabit
Ethernet driver by filling all the stubs except set_features.
set_feature patch will send as separate RFC patch along with
rx_checksum patch, as it needs detailed discussion related to HW
checksum.
quoted
Ref:-
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fp
atc
hwork.kernel.org%2Fproject%2Flinux-renesas-soc%2Flist%2F%3Fseries%3
D55
7655&data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7C25bc7b9155d8
402
a191808d98b5ae62f%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C6376
940
44814904836%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2l
uMz
IiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Vktj5v0GvrNf%2BDN
IFs
e6xjCUm6OjtzwHvK3q8aG1E5Y%3D&reserved=0
RFC->V1:
* Removed patch#3 will send it as RFC
* Removed rx_csum functionality from patch#7, will send it as RFC
* Renamed "nc_queue" -> "nc_queues"
* Separated the comment patch into 2 separate patches.
* Documented PFRI register bit
* Added Sergy's Rb tag
It's Sergey. :-)
My Bad. Sorry will taken care this in future. I need to send V2, as
accidentally I have added 2 macros in patch #6 As part of RFC
discussion into v1. I will send V2 to remove this.
I'm not seeing patches #2, #4, and #9 in my inboxes... :-/
Seeing them now in the linux-renesas-soc folder in the GMail account.
But they should have landed on the OMP account too. :-/
The DMAC and EMAC blocks of Gigabit Ethernet IP found on RZ/G2L SoC
are similar to the R-Car Ethernet AVB IP.
The Gigabit Ethernet IP consists of Ethernet controller (E-MAC),
Internal TCP/IP Offload Engine (TOE) and Dedicated Direct memory
access controller (DMAC).
With a few changes in the driver we can support both IPs.
This patch series is aims to add functional support for Gigabit
Ethernet driver by filling all the stubs except set_features.
set_feature patch will send as separate RFC patch along with
rx_checksum patch, as it needs detailed discussion related to HW
checksum.
quoted
Ref:-
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fp
atc
hwork.kernel.org%2Fproject%2Flinux-renesas-soc%2Flist%2F%3Fseries%3
D55
7655&data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7C25bc7b9155d8
402
a191808d98b5ae62f%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C6376
940
44814904836%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2l
uMz
IiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Vktj5v0GvrNf%2BDN
IFs
e6xjCUm6OjtzwHvK3q8aG1E5Y%3D&reserved=0
RFC->V1:
* Removed patch#3 will send it as RFC
* Removed rx_csum functionality from patch#7, will send it as RFC
* Renamed "nc_queue" -> "nc_queues"
* Separated the comment patch into 2 separate patches.
* Documented PFRI register bit
* Added Sergy's Rb tag
It's Sergey. :-)
My Bad. Sorry will taken care this in future. I need to send V2, as
accidentally I have added 2 macros in patch #6 As part of RFC
discussion into v1. I will send V2 to remove this.
I'm not seeing patches #2, #4, and #9 in my inboxes... :-/
Seeing them now in the linux-renesas-soc folder in the GMail account.
But they should have landed on the OMP account too. :-/
From: Biju Das <biju.das.jz@bp.renesas.com> Date: 2021-10-10 10:31:08
Hi Sergei,
Subject: Re: [PATCH 00/14] Add functional support for Gigabit Ethernet
driver
On 10.10.2021 12:25, Biju Das wrote:
[...]
quoted
quoted
quoted
quoted
quoted
quoted
The DMAC and EMAC blocks of Gigabit Ethernet IP found on RZ/G2L
SoC are similar to the R-Car Ethernet AVB IP.
The Gigabit Ethernet IP consists of Ethernet controller (E-MAC),
Internal TCP/IP Offload Engine (TOE) and Dedicated Direct memory
access controller (DMAC).
With a few changes in the driver we can support both IPs.
This patch series is aims to add functional support for Gigabit
Ethernet driver by filling all the stubs except set_features.
set_feature patch will send as separate RFC patch along with
rx_checksum patch, as it needs detailed discussion related to HW
checksum.
quoted
Ref:-
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2
Fp
atc
hwork.kernel.org%2Fproject%2Flinux-renesas-soc%2Flist%2F%3Fseries
%3
D55
7655&data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7C25bc7b9155
d8
402
a191808d98b5ae62f%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C63
76
940
44814904836%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV
2l
uMz
IiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Vktj5v0GvrNf%2B
DN
IFs
e6xjCUm6OjtzwHvK3q8aG1E5Y%3D&reserved=0
RFC->V1:
* Removed patch#3 will send it as RFC
* Removed rx_csum functionality from patch#7, will send it as
RFC
* Renamed "nc_queue" -> "nc_queues"
* Separated the comment patch into 2 separate patches.
* Documented PFRI register bit
* Added Sergy's Rb tag
It's Sergey. :-)
My Bad. Sorry will taken care this in future. I need to send V2, as
accidentally I have added 2 macros in patch #6 As part of RFC
discussion into v1. I will send V2 to remove this.
I'm not seeing patches #2, #4, and #9 in my inboxes... :-/
Seeing them now in the linux-renesas-soc folder in the GMail
account.
quoted
quoted
But they should have landed on the OMP account too. :-/
Can you please confirm latest series[1] lands on your OMP account?
[1]
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
hwork.kernel.org%2Fproject%2Fnetdevbpf%2Flist%2F%3Fseries%3D560617&
;data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7C4ba52eb2327b42fb997c08d
98bd48373%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637694567141278
405%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTi
I6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=LyurKu2sR%2BujQkts4LRyLMfPxw
7xmjON91zgS7f5Ktg%3D&reserved=0
No, as I've told you already. Was unclear again. :-)
Which patch doesn't have OMP account? I am sure, I have added your OMP account
As first cc list in the latest series.
Regards,
Biju
The DMAC and EMAC blocks of Gigabit Ethernet IP found on RZ/G2L
SoC are similar to the R-Car Ethernet AVB IP.
The Gigabit Ethernet IP consists of Ethernet controller (E-MAC),
Internal TCP/IP Offload Engine (TOE) and Dedicated Direct memory
access controller (DMAC).
With a few changes in the driver we can support both IPs.
This patch series is aims to add functional support for Gigabit
Ethernet driver by filling all the stubs except set_features.
set_feature patch will send as separate RFC patch along with
rx_checksum patch, as it needs detailed discussion related to HW
checksum.
quoted
Ref:-
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2
Fp
atc
hwork.kernel.org%2Fproject%2Flinux-renesas-soc%2Flist%2F%3Fseries
%3
D55
7655&data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7C25bc7b9155
d8
402
a191808d98b5ae62f%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C63
76
940
44814904836%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV
2l
uMz
IiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=Vktj5v0GvrNf%2B
DN
IFs
e6xjCUm6OjtzwHvK3q8aG1E5Y%3D&reserved=0
RFC->V1:
* Removed patch#3 will send it as RFC
* Removed rx_csum functionality from patch#7, will send it as
RFC
* Renamed "nc_queue" -> "nc_queues"
* Separated the comment patch into 2 separate patches.
* Documented PFRI register bit
* Added Sergy's Rb tag
It's Sergey. :-)
My Bad. Sorry will taken care this in future. I need to send V2, as
accidentally I have added 2 macros in patch #6 As part of RFC
discussion into v1. I will send V2 to remove this.
I'm not seeing patches #2, #4, and #9 in my inboxes... :-/
Seeing them now in the linux-renesas-soc folder in the GMail
account.
quoted
quoted
But they should have landed on the OMP account too. :-/
Can you please confirm latest series[1] lands on your OMP account?
[1]
https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatc
hwork.kernel.org%2Fproject%2Fnetdevbpf%2Flist%2F%3Fseries%3D560617&
;data=04%7C01%7Cbiju.das.jz%40bp.renesas.com%7C4ba52eb2327b42fb997c08d
98bd48373%7C53d82571da1947e49cb4625a166a4a2a%7C0%7C0%7C637694567141278
405%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTi
I6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdata=LyurKu2sR%2BujQkts4LRyLMfPxw
7xmjON91zgS7f5Ktg%3D&reserved=0
No, as I've told you already. Was unclear again. :-)
Which patch doesn't have OMP account?
As I said, #2, #4, and #9.
I am sure, I have added your OMP account
As first cc list in the latest series.