[PATCH 0/2] net: Add LiteETH network driver

This adds a driver for the LiteX network device, LiteETH.

It is a simple driver for the FPGA based Ethernet device used in various
RISC-V, PowerPC's microwatt, OpenRISC's mor1k and other FPGA based
systems on chip.

Joel Stanley (2):
  dt-bindings: net: Add bindings for LiteETH
  net: Add driver for LiteX's LiteETH network interface

 .../bindings/net/litex,liteeth.yaml           |  62 ++++
 drivers/net/ethernet/Kconfig                  |   1 +
 drivers/net/ethernet/Makefile                 |   1 +
 drivers/net/ethernet/litex/Kconfig            |  24 ++
 drivers/net/ethernet/litex/Makefile           |   5 +
 drivers/net/ethernet/litex/litex_liteeth.c    | 340 ++++++++++++++++++
 6 files changed, 433 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/litex,liteeth.yaml
 create mode 100644 drivers/net/ethernet/litex/Kconfig
 create mode 100644 drivers/net/ethernet/litex/Makefile
 create mode 100644 drivers/net/ethernet/litex/litex_liteeth.c

-- 
2.32.0

LiteETH is a small footprint and configurable Ethernet core for FPGA
based system on chips.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 .../bindings/net/litex,liteeth.yaml           | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/litex,liteeth.yaml

diff --git a/Documentation/devicetree/bindings/net/litex,liteeth.yaml b/Documentation/devicetree/bindings/net/litex,liteeth.yaml
new file mode 100644
index 000000000000..e2a837dbfdaa
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/litex,liteeth.yaml

@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/litex,liteeth.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LiteX LiteETH ethernet device
+
+maintainers:
+  - Joel Stanley <joel@jms.id.au>
+
+description: |
+  LiteETH is a small footprint and configurable Ethernet core for FPGA based
+  system on chips.
+
+  The hardware source is Open Source and can be found on at
+  https://github.com/enjoy-digital/liteeth/.
+
+properties:
+  compatible:
+    const: litex,liteeth
+
+  reg:
+    minItems: 3
+    items:
+      - description: MAC registers
+      - description: MDIO registers
+      - description: Packet buffer
+
+  interrupts:
+    maxItems: 1
+
+  rx-fifo-depth:
+    description: Receive FIFO size, in units of 2048 bytes
+
+  tx-fifo-depth:
+    description: Transmit FIFO size, in units of 2048 bytes
+
+  mac-address:
+    description: MAC address to use
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    mac: ethernet@8020000 {
+        compatible = "litex,liteeth";
+        reg = <0x8021000 0x100
+               0x8020800 0x100
+               0x8030000 0x2000>;
+        rx-fifo-depth = <2>;
+        tx-fifo-depth = <2>;
+        interrupts = <0x11 0x1>;
+    };
+...
+
+#  vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml :

-- 
2.32.0

LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic
network device that is commonly used in LiteX designs.

The driver was first written in 2017 and has been maintained by the
LiteX community in various trees. Thank you to all who have contributed.

Co-developed-by: Gabriel Somlo <gsomlo@gmail.com>
Co-developed-by: David Shah <redacted>
Co-developed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 drivers/net/ethernet/Kconfig               |   1 +
 drivers/net/ethernet/Makefile              |   1 +
 drivers/net/ethernet/litex/Kconfig         |  24 ++
 drivers/net/ethernet/litex/Makefile        |   5 +
 drivers/net/ethernet/litex/litex_liteeth.c | 340 +++++++++++++++++++++
 5 files changed, 371 insertions(+)
 create mode 100644 drivers/net/ethernet/litex/Kconfig
 create mode 100644 drivers/net/ethernet/litex/Makefile
 create mode 100644 drivers/net/ethernet/litex/litex_liteeth.c

diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index 1cdff1dca790..d796684ec9ca 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig

@@ -118,6 +118,7 @@ config LANTIQ_XRX200
 	  Support for the PMAC of the Gigabit switch (GSWIP) inside the
 	  Lantiq / Intel VRX200 VDSL SoC
 
+source "drivers/net/ethernet/litex/Kconfig"
 source "drivers/net/ethernet/marvell/Kconfig"
 source "drivers/net/ethernet/mediatek/Kconfig"
 source "drivers/net/ethernet/mellanox/Kconfig"

diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index cb3f9084a21b..aaa5078cd7d1 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile

@@ -51,6 +51,7 @@ obj-$(CONFIG_JME) += jme.o
 obj-$(CONFIG_KORINA) += korina.o
 obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
 obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o
+obj-$(CONFIG_NET_VENDOR_LITEX) += litex/
 obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/
 obj-$(CONFIG_NET_VENDOR_MEDIATEK) += mediatek/
 obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/

diff --git a/drivers/net/ethernet/litex/Kconfig b/drivers/net/ethernet/litex/Kconfig
new file mode 100644
index 000000000000..0a863e3ff7bf
--- /dev/null
+++ b/drivers/net/ethernet/litex/Kconfig

@@ -0,0 +1,24 @@
+#
+# LiteX device configuration
+#
+
+config NET_VENDOR_LITEX
+	bool "LiteX devices"
+	default y
+	help
+	  If you have a network (Ethernet) card belonging to this class, say Y.
+
+	  Note that the answer to this question doesn't directly affect the
+	  kernel: saying N will just cause the configurator to skip all
+	  the questions about LiteX devices. If you say Y, you will be asked
+	  for your specific card in the following questions.
+
+if NET_VENDOR_LITEX
+
+config LITEX_LITEETH
+	tristate "LiteX Ethernet support"
+	help
+	  If you wish to compile a kernel for hardware with a LiteX LiteEth
+	  device then you should answer Y to this.
+
+endif # NET_VENDOR_LITEX

diff --git a/drivers/net/ethernet/litex/Makefile b/drivers/net/ethernet/litex/Makefile
new file mode 100644
index 000000000000..9343b73b8e49
--- /dev/null
+++ b/drivers/net/ethernet/litex/Makefile

@@ -0,0 +1,5 @@
+#
+# Makefile for the LiteX network device drivers.
+#
+
+obj-$(CONFIG_LITEX_LITEETH) += litex_liteeth.o

diff --git a/drivers/net/ethernet/litex/litex_liteeth.c b/drivers/net/ethernet/litex/litex_liteeth.c
new file mode 100644
index 000000000000..48b551e6d97b
--- /dev/null
+++ b/drivers/net/ethernet/litex/litex_liteeth.c

@@ -0,0 +1,340 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * LiteX Liteeth Ethernet
+ *
+ * Copyright 2017 Joel Stanley <joel@jms.id.au>
+ *
+ */
+
+#include <linux/etherdevice.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_net.h>
+#include <linux/of_address.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/iopoll.h>
+
+#define LITEETH_WRITER_SLOT       0x00
+#define LITEETH_WRITER_LENGTH     0x04
+#define LITEETH_WRITER_ERRORS     0x08
+#define LITEETH_WRITER_EV_STATUS  0x0C
+#define LITEETH_WRITER_EV_PENDING 0x10
+#define LITEETH_WRITER_EV_ENABLE  0x14
+#define LITEETH_READER_START      0x18
+#define LITEETH_READER_READY      0x1C
+#define LITEETH_READER_LEVEL      0x20
+#define LITEETH_READER_SLOT       0x24
+#define LITEETH_READER_LENGTH     0x28
+#define LITEETH_READER_EV_STATUS  0x2C
+#define LITEETH_READER_EV_PENDING 0x30
+#define LITEETH_READER_EV_ENABLE  0x34
+#define LITEETH_PREAMBLE_CRC      0x38
+#define LITEETH_PREAMBLE_ERRORS   0x3C
+#define LITEETH_CRC_ERRORS        0x40
+
+#define LITEETH_PHY_CRG_RESET     0x00
+#define LITEETH_MDIO_W            0x04
+#define LITEETH_MDIO_R            0x0C
+
+#define DRV_NAME	"liteeth"
+
+#define LITEETH_BUFFER_SIZE		0x800
+#define MAX_PKT_SIZE			LITEETH_BUFFER_SIZE
+
+struct liteeth {
+	void __iomem *base;
+	void __iomem *mdio_base;
+	struct net_device *netdev;
+	struct device *dev;
+	struct mii_bus *mii_bus;
+
+	/* Link management */
+	int cur_duplex;
+	int cur_speed;
+
+	/* Tx */
+	int tx_slot;
+	int num_tx_slots;
+	void __iomem *tx_base;
+
+	/* Rx */
+	int rx_slot;
+	int num_rx_slots;
+	void __iomem *rx_base;
+};
+
+
+static int liteeth_rx(struct net_device *netdev)
+{
+	struct liteeth *priv = netdev_priv(netdev);
+	struct sk_buff *skb;
+	unsigned char *data;
+	u8 rx_slot;
+	int len;
+
+	rx_slot = readb(priv->base + LITEETH_WRITER_SLOT);
+	len = readl(priv->base + LITEETH_WRITER_LENGTH);
+
+	skb = netdev_alloc_skb(netdev, len + NET_IP_ALIGN);
+	if (!skb) {
+		netdev_err(netdev, "couldn't get memory");
+		netdev->stats.rx_dropped++;
+		return NET_RX_DROP;
+	}
+
+	/* Ensure alignemnt of the ip header within the skb */
+	skb_reserve(skb, NET_IP_ALIGN);
+	if (len == 0 || len > 2048)
+		return NET_RX_DROP;
+	data = skb_put(skb, len);
+	memcpy_fromio(data, priv->rx_base + rx_slot * LITEETH_BUFFER_SIZE, len);
+	skb->protocol = eth_type_trans(skb, netdev);
+
+	netdev->stats.rx_packets++;
+	netdev->stats.rx_bytes += len;
+
+	return netif_rx(skb);
+}
+
+static irqreturn_t liteeth_interrupt(int irq, void *dev_id)
+{
+	struct net_device *netdev = dev_id;
+	struct liteeth *priv = netdev_priv(netdev);
+	u8 reg;
+
+	reg = readb(priv->base + LITEETH_READER_EV_PENDING);
+	if (reg) {
+		netdev->stats.tx_packets++;
+		writeb(reg, priv->base + LITEETH_READER_EV_PENDING);
+	}
+
+	reg = readb(priv->base + LITEETH_WRITER_EV_PENDING);
+	if (reg) {
+		liteeth_rx(netdev);
+		writeb(reg, priv->base + LITEETH_WRITER_EV_PENDING);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int liteeth_open(struct net_device *netdev)
+{
+	struct liteeth *priv = netdev_priv(netdev);
+	int err;
+
+	/* Clear pending events */
+	writeb(1, priv->base + LITEETH_WRITER_EV_PENDING);
+	writeb(1, priv->base + LITEETH_READER_EV_PENDING);
+
+	err = request_irq(netdev->irq, liteeth_interrupt, 0, netdev->name, netdev);
+	if (err) {
+		netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
+		return err;
+	}
+
+	/* Enable IRQs */
+	writeb(1, priv->base + LITEETH_WRITER_EV_ENABLE);
+	writeb(1, priv->base + LITEETH_READER_EV_ENABLE);
+
+	/* TODO: Remove these once we have working mdio support */
+	priv->cur_duplex = DUPLEX_FULL;
+	priv->cur_speed = SPEED_100;
+	netif_carrier_on(netdev);
+
+	netif_start_queue(netdev);
+
+	return 0;
+}
+
+static int liteeth_stop(struct net_device *netdev)
+{
+	struct liteeth *priv = netdev_priv(netdev);
+
+	netif_stop_queue(netdev);
+
+	writeb(0, priv->base + LITEETH_WRITER_EV_ENABLE);
+	writeb(0, priv->base + LITEETH_READER_EV_ENABLE);
+
+	free_irq(netdev->irq, netdev);
+
+	return 0;
+}
+
+static int liteeth_start_xmit(struct sk_buff *skb, struct net_device *netdev)
+{
+	struct liteeth *priv = netdev_priv(netdev);
+	void __iomem *txbuffer;
+	int ret;
+	u8 val;
+
+	/* Reject oversize packets */
+	if (unlikely(skb->len > MAX_PKT_SIZE)) {
+		if (net_ratelimit())
+			netdev_dbg(netdev, "tx packet too big\n");
+		goto drop;
+	}
+
+	txbuffer = priv->tx_base + priv->tx_slot * LITEETH_BUFFER_SIZE;
+	memcpy_toio(txbuffer, skb->data, skb->len);
+	writeb(priv->tx_slot, priv->base + LITEETH_READER_SLOT);
+	writew(skb->len, priv->base + LITEETH_READER_LENGTH);
+
+	ret = readl_poll_timeout_atomic(priv->base + LITEETH_READER_READY, val, val, 5, 1000);
+	if (ret == -ETIMEDOUT) {
+		netdev_err(netdev, "LITEETH_READER_READY timed out\n");
+		goto drop;
+	}
+
+	writeb(1, priv->base + LITEETH_READER_START);
+
+	netdev->stats.tx_bytes += skb->len;
+
+	priv->tx_slot = (priv->tx_slot + 1) % priv->num_tx_slots;
+	dev_kfree_skb_any(skb);
+	return NETDEV_TX_OK;
+drop:
+	/* Drop the packet */
+	dev_kfree_skb_any(skb);
+	netdev->stats.tx_dropped++;
+
+	return NETDEV_TX_OK;
+}
+
+static const struct net_device_ops liteeth_netdev_ops = {
+	.ndo_open		= liteeth_open,
+	.ndo_stop		= liteeth_stop,
+	.ndo_start_xmit         = liteeth_start_xmit,
+};
+
+static void liteeth_reset_hw(struct liteeth *priv)
+{
+	/* Reset, twice */
+	writeb(0, priv->base + LITEETH_PHY_CRG_RESET);
+	udelay(10);
+	writeb(1, priv->base + LITEETH_PHY_CRG_RESET);
+	udelay(10);
+	writeb(0, priv->base + LITEETH_PHY_CRG_RESET);
+	udelay(10);
+}
+
+static int liteeth_probe(struct platform_device *pdev)
+{
+	struct net_device *netdev;
+	void __iomem *buf_base;
+	struct resource *res;
+	struct liteeth *priv;
+	int irq, err;
+
+	netdev = alloc_etherdev(sizeof(*priv));
+	if (!netdev)
+		return -ENOMEM;
+
+	priv = netdev_priv(netdev);
+	priv->netdev = netdev;
+	priv->dev = &pdev->dev;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "Failed to get IRQ\n");
+		goto err;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(priv->base)) {
+		err = PTR_ERR(priv->base);
+		goto err;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	priv->mdio_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(priv->mdio_base)) {
+		err = PTR_ERR(priv->mdio_base);
+		goto err;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+	buf_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(buf_base)) {
+		err = PTR_ERR(buf_base);
+		goto err;
+	}
+
+	err = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth",
+			&priv->num_rx_slots);
+	if (err) {
+		dev_err(&pdev->dev, "unable to get rx-fifo-depth\n");
+		goto err;
+	}
+
+	err = of_property_read_u32(pdev->dev.of_node, "tx-fifo-depth",
+			&priv->num_tx_slots);
+	if (err) {
+		dev_err(&pdev->dev, "unable to get tx-fifo-depth\n");
+		goto err;
+	}
+
+	/* Rx slots */
+	priv->rx_base = buf_base;
+	priv->rx_slot = 0;
+
+	/* Tx slots come after Rx slots */
+	priv->tx_base = buf_base + priv->num_rx_slots * LITEETH_BUFFER_SIZE;
+	priv->tx_slot = 0;
+
+	err = of_get_mac_address(pdev->dev.of_node, netdev->dev_addr);
+	if (err)
+		eth_hw_addr_random(netdev);
+
+	SET_NETDEV_DEV(netdev, &pdev->dev);
+	platform_set_drvdata(pdev, netdev);
+
+	netdev->netdev_ops = &liteeth_netdev_ops;
+	netdev->irq = irq;
+
+	liteeth_reset_hw(priv);
+
+	err = register_netdev(netdev);
+	if (err) {
+		dev_err(&pdev->dev, "Failed to register netdev\n");
+		goto err;
+	}
+
+	netdev_info(netdev, "irq %d, mapped at %px\n", netdev->irq, priv->base);
+
+	return 0;
+err:
+	free_netdev(netdev);
+	return err;
+}
+
+static int liteeth_remove(struct platform_device *pdev)
+{
+	struct net_device *netdev = platform_get_drvdata(pdev);
+
+	unregister_netdev(netdev);
+	free_netdev(netdev);
+
+	return 0;
+}
+
+static const struct of_device_id liteeth_of_match[] = {
+	{ .compatible = "litex,liteeth" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, liteeth_of_match);
+
+static struct platform_driver liteeth_driver = {
+	.probe = liteeth_probe,
+	.remove = liteeth_remove,
+	.driver = {
+		.name = DRV_NAME,
+		.of_match_table = liteeth_of_match,
+	},
+};
+module_platform_driver(liteeth_driver);
+
+MODULE_AUTHOR("Joel Stanley <joel@jms.id.au>");
+MODULE_LICENSE("GPL");

-- 
2.32.0

Hi Joel,

Thanks for pushing this upstream (and for writing it to begin with)!

Would you mind diff-ing your version of litex_liteeth.c against what
is currently in
https://github.com/litex-hub/linux/blob/litex-rebase/drivers/net/ethernet/litex/litex_liteeth.c ?

Two main differences we should discuss:

	1. there's a polling mode (added by Antony Pavlov), and if we
	   decide *not* to keep it around, I want to ensure we do that
	   deliberately, with an explanation as to why;

	2. LiteX CSRs are accessed using `litex_[read|write][8|16|32]()`
	   as opposed to simply `[read|write][b|w|l]()`. The former set
	   are defined in `include/linux/litex.h` and are needed to
	   ensure correct accesses regardless of endianness, since by
	   default LiteX registers' endianness mirrors that of the
	   configured CPU.

Thanks much,
--Gabriel

On Fri, Aug 06, 2021 at 03:19:04PM +0930, Joel Stanley wrote:

On Fri, 06 Aug 2021 15:19:03 +0930, Joel Stanley wrote:

LiteETH is a small footprint and configurable Ethernet core for FPGA
based system on chips.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 .../bindings/net/litex,liteeth.yaml           | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/litex,liteeth.yaml

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/litex,liteeth.example.dt.yaml: example-0: ethernet@8020000:reg:0: [134352896, 256, 134350848, 256, 134414336, 8192] is too long
	From schema: /usr/local/lib/python3.8/dist-packages/dtschema/schemas/reg.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/litex,liteeth.example.dt.yaml: ethernet@8020000: reg: [[134352896, 256, 134350848, 256, 134414336, 8192]] is too short
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/litex,liteeth.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1514186

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.

On Fri,  6 Aug 2021 15:19:04 +0930 Joel Stanley wrote:

LiteX is a soft system-on-chip that targets FPGAs. LiteETH is a basic
network device that is commonly used in LiteX designs.

The driver was first written in 2017 and has been maintained by the
LiteX community in various trees. Thank you to all who have contributed.

+config NET_VENDOR_LITEX
+	bool "LiteX devices"
+	default y
+	help
+	  If you have a network (Ethernet) card belonging to this class, say Y.
+
+	  Note that the answer to this question doesn't directly affect the
+	  kernel: saying N will just cause the configurator to skip all
+	  the questions about LiteX devices. If you say Y, you will be asked
+	  for your specific card in the following questions.

Maybe mention where the device is usually found (FPGAs) like you did in
the commit message, to help folks make a decision here?

+config LITEX_LITEETH
+	tristate "LiteX Ethernet support"
+	help
+	  If you wish to compile a kernel for hardware with a LiteX LiteEth
+	  device then you should answer Y to this.

+struct liteeth {
+	void __iomem *base;
+	void __iomem *mdio_base;
+	struct net_device *netdev;
+	struct device *dev;
+	struct mii_bus *mii_bus;

unused field

+
+	/* Link management */
+	int cur_duplex;
+	int cur_speed;
+
+	/* Tx */
+	int tx_slot;
+	int num_tx_slots;
+	void __iomem *tx_base;
+
+	/* Rx */
+	int rx_slot;
+	int num_rx_slots;
+	void __iomem *rx_base;
+};
+
+
+static int liteeth_rx(struct net_device *netdev)
+{
+	struct liteeth *priv = netdev_priv(netdev);
+	struct sk_buff *skb;
+	unsigned char *data;
+	u8 rx_slot;
+	int len;
+
+	rx_slot = readb(priv->base + LITEETH_WRITER_SLOT);
+	len = readl(priv->base + LITEETH_WRITER_LENGTH);
+
+	skb = netdev_alloc_skb(netdev, len + NET_IP_ALIGN);

netdev_alloc_skb_ip_align() ...

+	if (!skb) {
+		netdev_err(netdev, "couldn't get memory");

\n at the end? You can skip it but be consistent across messages

+		netdev->stats.rx_dropped++;
+		return NET_RX_DROP;
+	}
+
+	/* Ensure alignemnt of the ip header within the skb */
+	skb_reserve(skb, NET_IP_ALIGN);

... then skip this

+	if (len == 0 || len > 2048)
+		return NET_RX_DROP;

Should this be counted somehow?

+	data = skb_put(skb, len);
+	memcpy_fromio(data, priv->rx_base + rx_slot * LITEETH_BUFFER_SIZE, len);
+	skb->protocol = eth_type_trans(skb, netdev);
+
+	netdev->stats.rx_packets++;
+	netdev->stats.rx_bytes += len;
+
+	return netif_rx(skb);
+}
+
+static irqreturn_t liteeth_interrupt(int irq, void *dev_id)
+{
+	struct net_device *netdev = dev_id;
+	struct liteeth *priv = netdev_priv(netdev);
+	u8 reg;
+
+	reg = readb(priv->base + LITEETH_READER_EV_PENDING);
+	if (reg) {
+		netdev->stats.tx_packets++;
+		writeb(reg, priv->base + LITEETH_READER_EV_PENDING);
+	}
+
+	reg = readb(priv->base + LITEETH_WRITER_EV_PENDING);
+	if (reg) {
+		liteeth_rx(netdev);
+		writeb(reg, priv->base + LITEETH_WRITER_EV_PENDING);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int liteeth_open(struct net_device *netdev)
+{
+	struct liteeth *priv = netdev_priv(netdev);
+	int err;
+
+	/* Clear pending events */
+	writeb(1, priv->base + LITEETH_WRITER_EV_PENDING);
+	writeb(1, priv->base + LITEETH_READER_EV_PENDING);
+
+	err = request_irq(netdev->irq, liteeth_interrupt, 0, netdev->name, netdev);
+	if (err) {
+		netdev_err(netdev, "failed to request irq %d\n", netdev->irq);
+		return err;
+	}
+
+	/* Enable IRQs */
+	writeb(1, priv->base + LITEETH_WRITER_EV_ENABLE);
+	writeb(1, priv->base + LITEETH_READER_EV_ENABLE);
+
+	/* TODO: Remove these once we have working mdio support */
+	priv->cur_duplex = DUPLEX_FULL;
+	priv->cur_speed = SPEED_100;

please remove the fields until they're actually used

+	netif_carrier_on(netdev);
+
+	netif_start_queue(netdev);
+
+	return 0;
+}
+
+static int liteeth_stop(struct net_device *netdev)
+{
+	struct liteeth *priv = netdev_priv(netdev);

carrier_off() for symmetry?

+	netif_stop_queue(netdev);
+
+	writeb(0, priv->base + LITEETH_WRITER_EV_ENABLE);
+	writeb(0, priv->base + LITEETH_READER_EV_ENABLE);
+
+	free_irq(netdev->irq, netdev);
+	return 0;
+}
+
+static int liteeth_start_xmit(struct sk_buff *skb, struct net_device *netdev)
+{
+	struct liteeth *priv = netdev_priv(netdev);
+	void __iomem *txbuffer;
+	int ret;
+	u8 val;
+
+	/* Reject oversize packets */
+	if (unlikely(skb->len > MAX_PKT_SIZE)) {
+		if (net_ratelimit())
+			netdev_dbg(netdev, "tx packet too big\n");
+		goto drop;
+	}
+
+	txbuffer = priv->tx_base + priv->tx_slot * LITEETH_BUFFER_SIZE;
+	memcpy_toio(txbuffer, skb->data, skb->len);
+	writeb(priv->tx_slot, priv->base + LITEETH_READER_SLOT);
+	writew(skb->len, priv->base + LITEETH_READER_LENGTH);
+
+	ret = readl_poll_timeout_atomic(priv->base + LITEETH_READER_READY, val, val, 5, 1000);

Why the need for poll if there is an interrupt?
Why not stop the Tx queue once you're out of slots and restart 
it when the completion interrupt comes?

+	if (ret == -ETIMEDOUT) {
+		netdev_err(netdev, "LITEETH_READER_READY timed out\n");

ratelimit this as well, please

+		goto drop;
+	}
+
+	writeb(1, priv->base + LITEETH_READER_START);
+
+	netdev->stats.tx_bytes += skb->len;

Please count bytes and packets in the same place

+	priv->tx_slot = (priv->tx_slot + 1) % priv->num_tx_slots;
+	dev_kfree_skb_any(skb);
+	return NETDEV_TX_OK;
+drop:
+	/* Drop the packet */
+	dev_kfree_skb_any(skb);
+	netdev->stats.tx_dropped++;
+
+	return NETDEV_TX_OK;
+}

+static int liteeth_probe(struct platform_device *pdev)
+{
+	struct net_device *netdev;
+	void __iomem *buf_base;
+	struct resource *res;
+	struct liteeth *priv;
+	int irq, err;
+
+	netdev = alloc_etherdev(sizeof(*priv));
+	if (!netdev)
+		return -ENOMEM;
+
+	priv = netdev_priv(netdev);
+	priv->netdev = netdev;
+	priv->dev = &pdev->dev;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "Failed to get IRQ\n");
+		goto err;

`err` variable is not set here, you'd return 0

+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(priv->base)) {
+		err = PTR_ERR(priv->base);
+		goto err;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	priv->mdio_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(priv->mdio_base)) {
+		err = PTR_ERR(priv->mdio_base);
+		goto err;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+	buf_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(buf_base)) {
+		err = PTR_ERR(buf_base);
+		goto err;
+	}
+
+	err = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth",
+			&priv->num_rx_slots);

Please run checkpatch --strict and fix what it points out

+	if (err) {
+		dev_err(&pdev->dev, "unable to get rx-fifo-depth\n");
+		goto err;
+	}

+	return 0;
+err:
+	free_netdev(netdev);
+	return err;
+}

On Fri, Aug 06, 2021 at 03:19:03PM +0930, Joel Stanley wrote:

Hi Joel

How configurable is the synthesis? Can the MDIO bus be left out? You
can have only the MDIO bus and no MAC?

I've not looked at the driver yet, but if the MDIO bus has its own
address space, you could consider making it a standalone
device. Somebody including two or more LiteETH blocks could then have
one shared MDIO bus. That is a supported Linux architecture.

+
+  interrupts:
+    maxItems: 1
+
+  rx-fifo-depth:
+    description: Receive FIFO size, in units of 2048 bytes
+
+  tx-fifo-depth:
+    description: Transmit FIFO size, in units of 2048 bytes
+
+  mac-address:
+    description: MAC address to use
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    mac: ethernet@8020000 {
+        compatible = "litex,liteeth";
+        reg = <0x8021000 0x100
+               0x8020800 0x100
+               0x8030000 0x2000>;
+        rx-fifo-depth = <2>;
+        tx-fifo-depth = <2>;
+        interrupts = <0x11 0x1>;
+    };

You would normally expect to see some MDIO properties here, a link to
the standard MDIO yaml, etc.

    Andrew

+static void liteeth_reset_hw(struct liteeth *priv)
+{
+	/* Reset, twice */
+	writeb(0, priv->base + LITEETH_PHY_CRG_RESET);
+	udelay(10);
+	writeb(1, priv->base + LITEETH_PHY_CRG_RESET);
+	udelay(10);
+	writeb(0, priv->base + LITEETH_PHY_CRG_RESET);
+	udelay(10);

What is this actually resetting?

+static int liteeth_probe(struct platform_device *pdev)
+{
+	struct net_device *netdev;
+	void __iomem *buf_base;
+	struct resource *res;
+	struct liteeth *priv;
+	int irq, err;
+
+	netdev = alloc_etherdev(sizeof(*priv));
+	if (!netdev)
+		return -ENOMEM;
+
+	priv = netdev_priv(netdev);
+	priv->netdev = netdev;
+	priv->dev = &pdev->dev;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "Failed to get IRQ\n");
+		goto err;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(priv->base)) {
+		err = PTR_ERR(priv->base);
+		goto err;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	priv->mdio_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(priv->mdio_base)) {
+		err = PTR_ERR(priv->mdio_base);
+		goto err;
+	}

So you don't have any PHY handling, or any MDIO bus master code. So i
would drop this, until the MDIO architecture question is answered. I
also wonder how much use the MAC driver is without any PHY code?
Unless you have a good reason, i don't think we should merge this
until it makes the needed calls into phylib. It is not much code to
add.

	Andrew

On Sat, 7 Aug 2021 at 19:19, Andrew Lunn [off-list ref] wrote:

quoted

+static void liteeth_reset_hw(struct liteeth *priv)
+{
+     /* Reset, twice */
+     writeb(0, priv->base + LITEETH_PHY_CRG_RESET);
+     udelay(10);
+     writeb(1, priv->base + LITEETH_PHY_CRG_RESET);
+     udelay(10);
+     writeb(0, priv->base + LITEETH_PHY_CRG_RESET);
+     udelay(10);

What is this actually resetting?

This comes from the reference firmware that many (but not all) litex
systems run before loading their operating system.

I'm not completely sure how necessary it still is; I will drop it for now.

quoted

+static int liteeth_probe(struct platform_device *pdev)
+{
+     struct net_device *netdev;
+     void __iomem *buf_base;
+     struct resource *res;
+     struct liteeth *priv;
+     int irq, err;
+
+     netdev = alloc_etherdev(sizeof(*priv));
+     if (!netdev)
+             return -ENOMEM;
+
+     priv = netdev_priv(netdev);
+     priv->netdev = netdev;
+     priv->dev = &pdev->dev;
+
+     irq = platform_get_irq(pdev, 0);
+     if (irq < 0) {
+             dev_err(&pdev->dev, "Failed to get IRQ\n");
+             goto err;
+     }
+
+     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+     priv->base = devm_ioremap_resource(&pdev->dev, res);
+     if (IS_ERR(priv->base)) {
+             err = PTR_ERR(priv->base);
+             goto err;
+     }
+
+     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+     priv->mdio_base = devm_ioremap_resource(&pdev->dev, res);
+     if (IS_ERR(priv->mdio_base)) {
+             err = PTR_ERR(priv->mdio_base);
+             goto err;
+     }

So you don't have any PHY handling, or any MDIO bus master code. So i
would drop this, until the MDIO architecture question is answered. I
also wonder how much use the MAC driver is without any PHY code?
Unless you have a good reason, i don't think we should merge this
until it makes the needed calls into phylib. It is not much code to
add.

You mean I should skip out the parsing of the mdio base until I'm
using it? That's reasonable.

On Sat, 7 Aug 2021 at 19:05, Andrew Lunn [off-list ref] wrote:

On Fri, Aug 06, 2021 at 03:19:03PM +0930, Joel Stanley wrote:

quoted

LiteETH is a small footprint and configurable Ethernet core for FPGA
based system on chips.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 .../bindings/net/litex,liteeth.yaml           | 62 +++++++++++++++++++
 1 file changed, 62 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/litex,liteeth.yaml

diff --git a/Documentation/devicetree/bindings/net/litex,liteeth.yaml b/Documentation/devicetree/bindings/net/litex,liteeth.yaml
new file mode 100644
index 000000000000..e2a837dbfdaa
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/litex,liteeth.yaml

@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/litex,liteeth.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: LiteX LiteETH ethernet device
+
+maintainers:
+  - Joel Stanley <joel@jms.id.au>
+
+description: |
+  LiteETH is a small footprint and configurable Ethernet core for FPGA based
+  system on chips.
+
+  The hardware source is Open Source and can be found on at
+  https://github.com/enjoy-digital/liteeth/.
+
+properties:
+  compatible:
+    const: litex,liteeth
+
+  reg:
+    minItems: 3
+    items:
+      - description: MAC registers
+      - description: MDIO registers
+      - description: Packet buffer

Hi Joel

How configurable is the synthesis? Can the MDIO bus be left out? You
can have only the MDIO bus and no MAC?

I've not looked at the driver yet, but if the MDIO bus has its own
address space, you could consider making it a standalone
device. Somebody including two or more LiteETH blocks could then have
one shared MDIO bus. That is a supported Linux architecture.

It's currently integrated as one device. If you instatined two blocks,
you would end up with two mdio controllers, each inside those two
liteeth blocks.

Obviously being software someone could change that. We've had a few
discussions about the infinite possibilities of a soft SoC and what
that means for adding driver support to mainline. I think having some
basic driver support is useful, particularly as we then get close
review as Jakub provided.

The liteeth block has seen a lot of use under Linux by risc-v
(vexriscv), powerpc (microwatt), and openrisc (mor1k) designs. The
microwatt and or1k designs have mainline support, making them easy to
test. This driver will support the normal configurations of those
platforms.

As the soft core project evolves, we can revisit what goes in
mainline, how flexible that driver support needs to be, and how best
to manage that.

quoted

+
+  interrupts:
+    maxItems: 1
+
+  rx-fifo-depth:
+    description: Receive FIFO size, in units of 2048 bytes
+
+  tx-fifo-depth:
+    description: Transmit FIFO size, in units of 2048 bytes
+
+  mac-address:
+    description: MAC address to use
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    mac: ethernet@8020000 {
+        compatible = "litex,liteeth";
+        reg = <0x8021000 0x100
+               0x8020800 0x100
+               0x8030000 0x2000>;
+        rx-fifo-depth = <2>;
+        tx-fifo-depth = <2>;
+        interrupts = <0x11 0x1>;
+    };

You would normally expect to see some MDIO properties here, a link to
the standard MDIO yaml, etc.

Do you have a favourite example that I could follow?

Thanks for the review Jakub.

On Fri, 6 Aug 2021 at 23:10, Jakub Kicinski [off-list ref] wrote:

quoted

+static int liteeth_start_xmit(struct sk_buff *skb, struct net_device *netdev)
+{
+     struct liteeth *priv = netdev_priv(netdev);
+     void __iomem *txbuffer;
+     int ret;
+     u8 val;
+
+     /* Reject oversize packets */
+     if (unlikely(skb->len > MAX_PKT_SIZE)) {
+             if (net_ratelimit())
+                     netdev_dbg(netdev, "tx packet too big\n");
+             goto drop;
+     }
+
+     txbuffer = priv->tx_base + priv->tx_slot * LITEETH_BUFFER_SIZE;
+     memcpy_toio(txbuffer, skb->data, skb->len);
+     writeb(priv->tx_slot, priv->base + LITEETH_READER_SLOT);
+     writew(skb->len, priv->base + LITEETH_READER_LENGTH);
+
+     ret = readl_poll_timeout_atomic(priv->base + LITEETH_READER_READY, val, val, 5, 1000);

Why the need for poll if there is an interrupt?
Why not stop the Tx queue once you're out of slots and restart
it when the completion interrupt comes?

That makes sense.

In testing I have not been able to hit the LITEETH_READER_READY
not-ready state. I assume it's there to say that the slots are full.

quoted

+     if (ret == -ETIMEDOUT) {
+             netdev_err(netdev, "LITEETH_READER_READY timed out\n");

ratelimit this as well, please

quoted

+             goto drop;
+     }
+
+     writeb(1, priv->base + LITEETH_READER_START);
+
+     netdev->stats.tx_bytes += skb->len;

Please count bytes and packets in the same place

AFAIK we don't know the length when the interrupt comes in, so we need
to count both here in xmit?

quoted

+     priv->tx_slot = (priv->tx_slot + 1) % priv->num_tx_slots;
+     dev_kfree_skb_any(skb);
+     return NETDEV_TX_OK;
+drop:
+     /* Drop the packet */
+     dev_kfree_skb_any(skb);
+     netdev->stats.tx_dropped++;
+
+     return NETDEV_TX_OK;
+}

On Mon, Aug 09, 2021 at 03:20:57AM +0000, Joel Stanley wrote:

On Sat, 7 Aug 2021 at 19:19, Andrew Lunn [off-list ref] wrote:

quoted

quoted

+static void liteeth_reset_hw(struct liteeth *priv)
+{
+     /* Reset, twice */
+     writeb(0, priv->base + LITEETH_PHY_CRG_RESET);
+     udelay(10);
+     writeb(1, priv->base + LITEETH_PHY_CRG_RESET);
+     udelay(10);
+     writeb(0, priv->base + LITEETH_PHY_CRG_RESET);
+     udelay(10);

What is this actually resetting?

This comes from the reference firmware that many (but not all) litex
systems run before loading their operating system.

I'm not completely sure how necessary it still is; I will drop it for now.

Which did not answer my question. Once we know what is being reset, we
can maybe suggest when/how it should be reset.

quoted

quoted

+static int liteeth_probe(struct platform_device *pdev)
+{
+     struct net_device *netdev;
+     void __iomem *buf_base;
+     struct resource *res;
+     struct liteeth *priv;
+     int irq, err;
+
+     netdev = alloc_etherdev(sizeof(*priv));
+     if (!netdev)
+             return -ENOMEM;
+
+     priv = netdev_priv(netdev);
+     priv->netdev = netdev;
+     priv->dev = &pdev->dev;
+
+     irq = platform_get_irq(pdev, 0);
+     if (irq < 0) {
+             dev_err(&pdev->dev, "Failed to get IRQ\n");
+             goto err;
+     }
+
+     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+     priv->base = devm_ioremap_resource(&pdev->dev, res);
+     if (IS_ERR(priv->base)) {
+             err = PTR_ERR(priv->base);
+             goto err;
+     }
+
+     res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+     priv->mdio_base = devm_ioremap_resource(&pdev->dev, res);
+     if (IS_ERR(priv->mdio_base)) {
+             err = PTR_ERR(priv->mdio_base);
+             goto err;
+     }

So you don't have any PHY handling, or any MDIO bus master code. So i
would drop this, until the MDIO architecture question is answered. I
also wonder how much use the MAC driver is without any PHY code?
Unless you have a good reason, i don't think we should merge this
until it makes the needed calls into phylib. It is not much code to
add.

You mean I should skip out the parsing of the mdio base until I'm
using it? That's reasonable.

It could be we insist you add MDIO and PHY handling. But first we need
to understand the architecture.

   Andrew

quoted

Hi Joel

How configurable is the synthesis? Can the MDIO bus be left out? You
can have only the MDIO bus and no MAC?

I've not looked at the driver yet, but if the MDIO bus has its own
address space, you could consider making it a standalone
device. Somebody including two or more LiteETH blocks could then have
one shared MDIO bus. That is a supported Linux architecture.

It's currently integrated as one device. If you instatined two blocks,
you would end up with two mdio controllers, each inside those two
liteeth blocks.

O.K. So at the moment, that is the default architecture, and the
driver should then support it. But since there appears to be a clean
address space split, the Linux MDIO driver could still be
separate. But it might depend on the reset, since the register is in
the MDIO address space. So again, we need to understand what that
reset is about.

Obviously being software someone could change that. We've had a few
discussions about the infinite possibilities of a soft SoC and what
that means for adding driver support to mainline.

Has any thought been given to making the hardware somehow
enumerable/self describing? A register containing features which have
been synthesised? There could be a bit indicating is the MDIO bus
master is present, etc.

As the soft core project evolves, we can revisit what goes in
mainline, how flexible that driver support needs to be, and how best
to manage that.

We can do that, but we have to keep backwards compatibility in
mind. We cannot break older synthesised IP blobs because a new feature
has come along and the driver has changed. It is best to put some
thought into that now, how forward/backward compatibility will work.
A revision register, a self description register, something which
helps the software driver identify what the 'hardware' is.

      Andrew

quoted

quoted

+
+  interrupts:
+    maxItems: 1
+
+  rx-fifo-depth:
+    description: Receive FIFO size, in units of 2048 bytes
+
+  tx-fifo-depth:
+    description: Transmit FIFO size, in units of 2048 bytes
+
+  mac-address:
+    description: MAC address to use
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+additionalProperties: false
+
+examples:
+  - |
+    mac: ethernet@8020000 {
+        compatible = "litex,liteeth";
+        reg = <0x8021000 0x100
+               0x8020800 0x100
+               0x8030000 0x2000>;
+        rx-fifo-depth = <2>;
+        tx-fifo-depth = <2>;
+        interrupts = <0x11 0x1>;
+    };

You would normally expect to see some MDIO properties here, a link to
the standard MDIO yaml, etc.

Do you have a favourite example that I could follow?

Documentation/devicetree/bindings/net/mdio.yaml describes all the
standard properties. Picking a file at random:

Documentation/devicetree/bindings/net/socionext,uniphier-ave4.yaml

On Mon, 9 Aug 2021 12:03:36 +0000 Joel Stanley wrote:

On Fri, 6 Aug 2021 at 23:10, Jakub Kicinski [off-list ref] wrote:

quoted

quoted

+static int liteeth_start_xmit(struct sk_buff *skb, struct net_device *netdev)
+{
+     struct liteeth *priv = netdev_priv(netdev);
+     void __iomem *txbuffer;
+     int ret;
+     u8 val;
+
+     /* Reject oversize packets */
+     if (unlikely(skb->len > MAX_PKT_SIZE)) {
+             if (net_ratelimit())
+                     netdev_dbg(netdev, "tx packet too big\n");
+             goto drop;
+     }
+
+     txbuffer = priv->tx_base + priv->tx_slot * LITEETH_BUFFER_SIZE;
+     memcpy_toio(txbuffer, skb->data, skb->len);
+     writeb(priv->tx_slot, priv->base + LITEETH_READER_SLOT);
+     writew(skb->len, priv->base + LITEETH_READER_LENGTH);
+
+     ret = readl_poll_timeout_atomic(priv->base + LITEETH_READER_READY, val, val, 5, 1000);  

Why the need for poll if there is an interrupt?
Why not stop the Tx queue once you're out of slots and restart
it when the completion interrupt comes?  

That makes sense.

In testing I have not been able to hit the LITEETH_READER_READY
not-ready state. I assume it's there to say that the slots are full.

In that case it's probably best to stop the Tx queue in the xmit routine
once all the lots are used, and restart it from the interrupt. I was
guessing maybe the IRQ is not always there, but that doesn't seem to be
the case.
 

quoted

quoted

+     if (ret == -ETIMEDOUT) {
+             netdev_err(netdev, "LITEETH_READER_READY timed out\n");  

ratelimit this as well, please
 

quoted

+             goto drop;
+     }
+
+     writeb(1, priv->base + LITEETH_READER_START);
+
+     netdev->stats.tx_bytes += skb->len;  

Please count bytes and packets in the same place  

AFAIK we don't know the length when the interrupt comes in, so we need
to count both here in xmit?

Either that or allocate a small array (num_tx_slots) to save the
lengths for IRQ routine to use.

quoted

quoted

+     priv->tx_slot = (priv->tx_slot + 1) % priv->num_tx_slots;
+     dev_kfree_skb_any(skb);
+     return NETDEV_TX_OK;
+drop:
+     /* Drop the packet */
+     dev_kfree_skb_any(skb);
+     netdev->stats.tx_dropped++;
+
+     return NETDEV_TX_OK;
+}