# Re: \[PATCH v2 4/5\] clk: renesas: r9a07g044-cpg: Add entry for fixed clock P0\_DIV2

- From: Geert Uytterhoeven \<geert@linux-m68k.org\>
- Date: 2021-07-20 10:41:25 
- List: netdev
- Page: https://ratatoskr.run/netdev/2021/07/1452256
- Thread: https://ratatoskr.run/linux-can/2021/07/1449209/t.md

```text
On Mon, Jul 19, 2021 at 4:40 PM Lad Prabhakar
[ref] wrote:
> Add entry for fixed core clock P0_DIV2 and assign LAST_DT_CORE_CLK
> to R9A07G044_CLK_P0_DIV2.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.15.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
```