From: Vladimir Oltean <olteanv@gmail.com> Date: 2021-03-31 20:09:51
From: Vladimir Oltean <vladimir.oltean@nxp.com>
This series adds support to the enetc driver for the basic XDP primitives.
The ENETC is a network controller found inside the NXP LS1028A SoC,
which is a dual-core Cortex A72 device for industrial networking,
with the CPUs clocked at up to 1.3 GHz. On this platform, there are 4
ENETC ports and a 6-port embedded DSA switch, in a topology that looks
like this:
+-------------------------------------------------------------------------+
| +--------+ 1 Gbps (typically disabled) |
| ENETC PCI | ENETC |--------------------------+ |
| Root Complex | port 3 |-----------------------+ | |
| Integrated +--------+ | | |
| Endpoint | | |
| +--------+ 2.5 Gbps | | |
| | ENETC |--------------+ | | |
| | port 2 |-----------+ | | | |
| +--------+ | | | | |
| | | | | |
| +------------------------------------------------+
| | | Felix | | Felix | |
| | Switch | port 4 | | port 5 | |
| | +--------+ +--------+ |
| | |
| +--------+ +--------+ | +--------+ +--------+ +--------+ +--------+ |
| | ENETC | | ENETC | | | Felix | | Felix | | Felix | | Felix | |
| | port 0 | | port 1 | | | port 0 | | port 1 | | port 2 | | port 3 | |
+-------------------------------------------------------------------------+
| | | | | |
v v v v v v
Up to Up to Up to 4x 2.5Gbps
2.5Gbps 1Gbps
The ENETC ports 2 and 3 can act as DSA masters for the embedded switch.
Because 4 out of the 6 externally-facing ports of the SoC are switch
ports, the most interesting use case for XDP on this device is in fact
XDP_TX on the 2.5Gbps DSA master.
Nonetheless, the results presented below are for IPv4 forwarding between
ENETC port 0 (eno0) and port 1 (eno1) both configured for 1Gbps.
There are two streams of IPv4/UDP datagrams with a frame length of 64
octets delivered at 100% port load to eno0 and to eno1. eno0 has a flow
steering rule to process the traffic on RX ring 0 (CPU 0), and eno1 has
a flow steering rule towards RX ring 1 (CPU 1).
For the IPFWD test, standard IP routing was enabled in the netns.
For the XDP_DROP test, the samples/bpf/xdp1 program was attached to both
eno0 and to eno1.
For the XDP_TX test, the samples/bpf/xdp2 program was attached to both
eno0 and to eno1.
For the XDP_REDIRECT test, the samples/bpf/xdp_redirect program was
attached once to the input of eno0/output of eno1, and twice to the
input of eno1/output of eno0.
Finally, the preliminary results are as follows:
| IPFWD | XDP_TX | XDP_REDIRECT | XDP_DROP
--------+-------+--------+-------------------------
fps | 761 | 2535 | 1735 | 2783
Gbps | 0.51 | 1.71 | 1.17 | n/a
There is a strange phenomenon in my testing sistem where it appears that
one CPU is processing more than the other. I have not investigated this
too much. Also, the code might not be very well optimized (for example
dma_sync_for_device is called with the full ENETC_RXB_DMA_SIZE_XDP).
Design wise, the ENETC is a PCI device with BD rings, so it uses the
MEM_TYPE_PAGE_SHARED memory model, as can typically be seen in Intel
devices. The strategy was to build upon the existing model that the
driver uses, and not change it too much. So you will see things like a
separate NAPI poll function for XDP.
I have only tested with PAGE_SIZE=4096, and since we split pages in
half, it means that MTU-sized frames are scatter/gather (the XDP
headroom + skb_shared_info only leaves us 1476 bytes of data per
buffer). This is sub-optimal, but I would rather keep it this way and
help speed up Lorenzo's series for S/G support through testing, rather
than change the enetc driver to use some other memory model like page_pool.
My code is already structured for S/G, and that works fine for XDP_DROP
and XDP_TX, just not for XDP_REDIRECT, even between two enetc ports.
So the S/G XDP_REDIRECT is stubbed out (the frames are dropped), but
obviously I would like to remove that limitation soon.
Please note that I am rather new to this kind of stuff, I am more of a
control path person, so I would appreciate feedback.
Enough talking, on to the patches.
Vladimir Oltean (9):
net: enetc: consume the error RX buffer descriptors in a dedicated
function
net: enetc: move skb creation into enetc_build_skb
net: enetc: add a dedicated is_eof bit in the TX software BD
net: enetc: clean the TX software BD on the TX confirmation path
net: enetc: move up enetc_reuse_page and enetc_page_reusable
net: enetc: add support for XDP_DROP and XDP_PASS
net: enetc: add support for XDP_TX
net: enetc: increase RX ring default size
net: enetc: add support for XDP_REDIRECT
drivers/net/ethernet/freescale/enetc/enetc.c | 826 +++++++++++++++---
drivers/net/ethernet/freescale/enetc/enetc.h | 53 +-
.../ethernet/freescale/enetc/enetc_ethtool.c | 19 +-
.../net/ethernet/freescale/enetc/enetc_pf.c | 2 +
4 files changed, 796 insertions(+), 104 deletions(-)
--
2.25.1
From: Vladimir Oltean <olteanv@gmail.com> Date: 2021-03-31 20:09:51
From: Vladimir Oltean <vladimir.oltean@nxp.com>
We can and should check the RX BD errors before starting to build the
skb. The only apparent reason why things are done in this backwards
order is to spare one call to enetc_rxbd_next.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/net/ethernet/freescale/enetc/enetc.c | 43 ++++++++++++--------
1 file changed, 27 insertions(+), 16 deletions(-)
@@ -605,6 +605,28 @@ static void enetc_add_rx_buff_to_skb(struct enetc_bdr *rx_ring, int i,enetc_put_rx_buff(rx_ring,rx_swbd);}+staticboolenetc_check_bd_errors_and_consume(structenetc_bdr*rx_ring,+u32bd_status,+unionenetc_rx_bd**rxbd,int*i)+{+if(likely(!(bd_status&ENETC_RXBD_LSTATUS(ENETC_RXBD_ERR_MASK))))+returnfalse;++enetc_rxbd_next(rx_ring,rxbd,i);++while(!(bd_status&ENETC_RXBD_LSTATUS_F)){+dma_rmb();+bd_status=le32_to_cpu((*rxbd)->r.lstatus);++enetc_rxbd_next(rx_ring,rxbd,i);+}++rx_ring->ndev->stats.rx_dropped++;+rx_ring->ndev->stats.rx_errors++;++returntrue;+}+#define ENETC_RXBD_BUNDLE 16 /* # of BDs to update at once */staticintenetc_clean_rx_ring(structenetc_bdr*rx_ring,
@@ -634,6 +656,11 @@ static int enetc_clean_rx_ring(struct enetc_bdr *rx_ring,enetc_wr_reg_hot(rx_ring->idr,BIT(rx_ring->index));dma_rmb();/* for reading other rxbd fields */++if(enetc_check_bd_errors_and_consume(rx_ring,bd_status,+&rxbd,&i))+break;+size=le16_to_cpu(rxbd->r.buf_len);skb=enetc_map_rx_buff_to_skb(rx_ring,i,size);if(!skb)
@@ -645,22 +672,6 @@ static int enetc_clean_rx_ring(struct enetc_bdr *rx_ring,enetc_rxbd_next(rx_ring,&rxbd,&i);-if(unlikely(bd_status&-ENETC_RXBD_LSTATUS(ENETC_RXBD_ERR_MASK))){-dev_kfree_skb(skb);-while(!(bd_status&ENETC_RXBD_LSTATUS_F)){-dma_rmb();-bd_status=le32_to_cpu(rxbd->r.lstatus);--enetc_rxbd_next(rx_ring,&rxbd,&i);-}--rx_ring->ndev->stats.rx_dropped++;-rx_ring->ndev->stats.rx_errors++;--break;-}-/* not last BD in frame? */while(!(bd_status&ENETC_RXBD_LSTATUS_F)){bd_status=le32_to_cpu(rxbd->r.lstatus);
From: Vladimir Oltean <olteanv@gmail.com> Date: 2021-03-31 20:09:51
From: Vladimir Oltean <vladimir.oltean@nxp.com>
We need to build an skb from two code paths now: from the plain RX data
path and from the XDP data path when the verdict is XDP_PASS.
Create a new enetc_build_skb function which contains the essential steps
for building an skb based on the first and last positions of buffer
descriptors within the RX ring.
We also squash the enetc_process_skb function into enetc_build_skb,
because what that function did wasn't very meaningful on its own.
The "rx_frm_cnt++" instruction has been moved around napi_gro_receive
for cosmetic reasons, to be in the same spot as rx_byte_cnt++, which
itself must be before napi_gro_receive, because that's when we lose
ownership of the skb.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/net/ethernet/freescale/enetc/enetc.c | 81 +++++++++++---------
1 file changed, 44 insertions(+), 37 deletions(-)
@@ -627,6 +620,47 @@ static bool enetc_check_bd_errors_and_consume(struct enetc_bdr *rx_ring,returntrue;}+staticstructsk_buff*enetc_build_skb(structenetc_bdr*rx_ring,+u32bd_status,unionenetc_rx_bd**rxbd,+int*i,int*cleaned_cnt)+{+structsk_buff*skb;+u16size;++size=le16_to_cpu((*rxbd)->r.buf_len);+skb=enetc_map_rx_buff_to_skb(rx_ring,*i,size);+if(!skb)+returnNULL;++enetc_get_offloads(rx_ring,*rxbd,skb);++(*cleaned_cnt)++;++enetc_rxbd_next(rx_ring,rxbd,i);++/* not last BD in frame? */+while(!(bd_status&ENETC_RXBD_LSTATUS_F)){+bd_status=le32_to_cpu((*rxbd)->r.lstatus);+size=ENETC_RXB_DMA_SIZE;++if(bd_status&ENETC_RXBD_LSTATUS_F){+dma_rmb();+size=le16_to_cpu((*rxbd)->r.buf_len);+}++enetc_add_rx_buff_to_skb(rx_ring,*i,size,skb);++(*cleaned_cnt)++;++enetc_rxbd_next(rx_ring,rxbd,i);+}++skb_record_rx_queue(skb,rx_ring->index);+skb->protocol=eth_type_trans(skb,rx_ring->ndev);++returnskb;+}+#define ENETC_RXBD_BUNDLE 16 /* # of BDs to update at once */staticintenetc_clean_rx_ring(structenetc_bdr*rx_ring,
@@ -643,7 +677,6 @@ static int enetc_clean_rx_ring(struct enetc_bdr *rx_ring,unionenetc_rx_bd*rxbd;structsk_buff*skb;u32bd_status;-u16size;if(cleaned_cnt>=ENETC_RXBD_BUNDLE)cleaned_cnt-=enetc_refill_rx_ring(rx_ring,
@@ -661,41 +694,15 @@ static int enetc_clean_rx_ring(struct enetc_bdr *rx_ring,&rxbd,&i))break;-size=le16_to_cpu(rxbd->r.buf_len);-skb=enetc_map_rx_buff_to_skb(rx_ring,i,size);+skb=enetc_build_skb(rx_ring,bd_status,&rxbd,&i,+&cleaned_cnt);if(!skb)break;-enetc_get_offloads(rx_ring,rxbd,skb);--cleaned_cnt++;--enetc_rxbd_next(rx_ring,&rxbd,&i);--/* not last BD in frame? */-while(!(bd_status&ENETC_RXBD_LSTATUS_F)){-bd_status=le32_to_cpu(rxbd->r.lstatus);-size=ENETC_RXB_DMA_SIZE;--if(bd_status&ENETC_RXBD_LSTATUS_F){-dma_rmb();-size=le16_to_cpu(rxbd->r.buf_len);-}--enetc_add_rx_buff_to_skb(rx_ring,i,size,skb);--cleaned_cnt++;--enetc_rxbd_next(rx_ring,&rxbd,&i);-}-rx_byte_cnt+=skb->len;--enetc_process_skb(rx_ring,skb);+rx_frm_cnt++;napi_gro_receive(napi,skb);--rx_frm_cnt++;}rx_ring->next_to_clean=i;
From: Vladimir Oltean <olteanv@gmail.com> Date: 2021-03-31 20:10:22
From: Vladimir Oltean <vladimir.oltean@nxp.com>
In the transmit path, if we have a scatter/gather frame, it is put into
multiple software buffer descriptors, the last of which has the skb
pointer populated (which is necessary for rearming the TX MSI vector and
for collecting the two-step TX timestamp from the TX confirmation path).
At the moment, this is sufficient, but with XDP_TX, we'll need to
service TX software buffer descriptors that don't have an skb pointer,
however they might be final nonetheless. So add a dedicated bit for
final software BDs that we populate and check explicitly. Also, we keep
looking just for an skb when doing TX timestamping, because we don't
want/need that for XDP.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/net/ethernet/freescale/enetc/enetc.c | 7 +++----
drivers/net/ethernet/freescale/enetc/enetc.h | 1 +
2 files changed, 4 insertions(+), 4 deletions(-)
From: Vladimir Oltean <olteanv@gmail.com> Date: 2021-03-31 20:10:23
From: Vladimir Oltean <vladimir.oltean@nxp.com>
With the future introduction of some new fields into enetc_tx_swbd such
as is_xdp_tx, is_xdp_redirect etc, we need not only to set these bits
to true from the XDP_TX/XDP_REDIRECT code path, but also to false from
the old code paths.
This is because TX software buffer descriptors are kept in a ring that
is shadow of the hardware TX ring, so these structures keep getting
reused, and there is always the possibility that when a software BD is
reused (after we ran a full circle through the TX ring), the old user of
the tx_swbd had set is_xdp_tx = true, and now we are sending a regular
skb, which would need to set is_xdp_tx = false.
To be minimally invasive to the old code paths, let's just scrub the
software TX BD in the TX confirmation path (enetc_clean_tx_ring), once
we know that nobody uses this software TX BD (tx_ring->next_to_clean
hasn't yet been updated, and the TX paths check enetc_bd_unused which
tells them if there's any more space in the TX ring for a new enqueue).
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/net/ethernet/freescale/enetc/enetc.c | 4 ++++
1 file changed, 4 insertions(+)
@@ -344,6 +344,10 @@ static bool enetc_clean_tx_ring(struct enetc_bdr *tx_ring, int napi_budget)}tx_byte_cnt+=tx_swbd->len;+/* Scrub the swbd here so we don't have to do that+*whenwereuseitduringxmit+*/+memset(tx_swbd,0,sizeof(*tx_swbd));bds_to_clean--;tx_swbd++;
From: Vladimir Oltean <olteanv@gmail.com> Date: 2021-03-31 20:10:23
From: Vladimir Oltean <vladimir.oltean@nxp.com>
For XDP_TX, we need to call enetc_reuse_page from enetc_clean_tx_ring,
so we need to avoid a forward declaration.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/net/ethernet/freescale/enetc/enetc.c | 38 ++++++++++----------
1 file changed, 19 insertions(+), 19 deletions(-)
@@ -275,6 +275,25 @@ static int enetc_bd_ready_count(struct enetc_bdr *tx_ring, int ci)returnpi>=ci?pi-ci:tx_ring->bd_count-ci+pi;}+staticboolenetc_page_reusable(structpage*page)+{+return(!page_is_pfmemalloc(page)&&page_ref_count(page)==1);+}++staticvoidenetc_reuse_page(structenetc_bdr*rx_ring,+structenetc_rx_swbd*old)+{+structenetc_rx_swbd*new;++new=&rx_ring->rx_swbd[rx_ring->next_to_alloc];++/* next buf that may reuse a page */+enetc_bdr_idx_inc(rx_ring,&rx_ring->next_to_alloc);++/* copy page reference */+*new=*old;+}+staticvoidenetc_get_tx_tstamp(structenetc_hw*hw,unionenetc_tx_bd*txbd,u64*tstamp){
@@ -516,25 +535,6 @@ static void enetc_get_offloads(struct enetc_bdr *rx_ring,#endif}-staticboolenetc_page_reusable(structpage*page)-{-return(!page_is_pfmemalloc(page)&&page_ref_count(page)==1);-}--staticvoidenetc_reuse_page(structenetc_bdr*rx_ring,-structenetc_rx_swbd*old)-{-structenetc_rx_swbd*new;--new=&rx_ring->rx_swbd[rx_ring->next_to_alloc];--/* next buf that may reuse a page */-enetc_bdr_idx_inc(rx_ring,&rx_ring->next_to_alloc);--/* copy page reference */-*new=*old;-}-staticstructenetc_rx_swbd*enetc_get_rx_buff(structenetc_bdr*rx_ring,inti,u16size){
From: Vladimir Oltean <olteanv@gmail.com> Date: 2021-03-31 20:10:23
From: Vladimir Oltean <vladimir.oltean@nxp.com>
For the RX ring, enetc uses an allocation scheme based on pages split
into two buffers, which is already very efficient in terms of preventing
reallocations / maximizing reuse, so I see no reason why I would change
that.
+--------+--------+--------+--------+--------+--------+--------+
| | | | | | | |
| half B | half B | half B | half B | half B | half B | half B |
| | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+
| | | | | | | |
| half A | half A | half A | half A | half A | half A | half A | RX ring
| | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+
^ ^
| |
next_to_clean next_to_alloc
next_to_use
+--------+--------+--------+--------+--------+
| | | | | |
| half B | half B | half B | half B | half B |
| | | | | |
+--------+--------+--------+--------+--------+--------+--------+
| | | | | | | |
| half B | half B | half A | half A | half A | half A | half A | RX ring
| | | | | | | |
+--------+--------+--------+--------+--------+--------+--------+
| | | ^ ^
| half A | half A | | |
| | | next_to_clean next_to_use
+--------+--------+
^
|
next_to_alloc
then when enetc_refill_rx_ring is called, whose purpose is to advance
next_to_use, it sees that it can take buffers up to next_to_alloc, and
it says "oh, hey, rx_swbd->page isn't NULL, I don't need to allocate
one!".
The only problem is that for default PAGE_SIZE values of 4096, buffer
sizes are 2048 bytes. While this is enough for normal skb allocations at
an MTU of 1500 bytes, for XDP it isn't, because the XDP headroom is 256
bytes, and including skb_shared_info and alignment, we end up being able
to make use of only 1472 bytes, which is insufficient for the default
MTU.
To solve that problem, we implement scatter/gather processing in the
driver, because we would really like to keep the existing allocation
scheme. A packet of 1500 bytes is received in a buffer of 1472 bytes and
another one of 28 bytes.
Because the headroom required by XDP is different (and much larger) than
the one required by the network stack, whenever a BPF program is added
or deleted on the port, we drain the existing RX buffers and seed new
ones with the required headroom. We also keep the required headroom in
rx_ring->buffer_offset.
The simplest way to implement XDP_PASS, where an skb must be created, is
to create an xdp_buff based on the next_to_clean RX BDs, but not clear
those BDs from the RX ring yet, just keep the original index at which
the BDs for this frame started. Then, if the verdict is XDP_PASS,
instead of converting the xdb_buff to an skb, we replay a call to
enetc_build_skb (just as in the normal enetc_clean_rx_ring case),
starting from the original BD index.
We would also like to be minimally invasive to the regular RX data path,
and not check whether there is a BPF program attached to the ring on
every packet. So we create a separate RX ring processing function for
XDP.
Because we only install/remove the BPF program while the interface is
down, we forgo the rcu_read_lock() in enetc_clean_rx_ring, since there
shouldn't be any circumstance in which we are processing packets and
there is a potentially freed BPF program attached to the RX ring.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/net/ethernet/freescale/enetc/enetc.c | 284 ++++++++++++++++--
drivers/net/ethernet/freescale/enetc/enetc.h | 14 +
.../ethernet/freescale/enetc/enetc_ethtool.c | 2 +
.../net/ethernet/freescale/enetc/enetc_pf.c | 1 +
4 files changed, 281 insertions(+), 20 deletions(-)
@@ -558,8 +561,7 @@ static void enetc_put_rx_buff(struct enetc_bdr *rx_ring,/* sync for use by the device */dma_sync_single_range_for_device(rx_ring->dev,rx_swbd->dma,rx_swbd->page_offset,-ENETC_RXB_DMA_SIZE,-DMA_FROM_DEVICE);+buffer_size,DMA_FROM_DEVICE);}else{dma_unmap_page(rx_ring->dev,rx_swbd->dma,PAGE_SIZE,DMA_FROM_DEVICE);
@@ -644,7 +646,7 @@ static struct sk_buff *enetc_build_skb(struct enetc_bdr *rx_ring,/* not last BD in frame? */while(!(bd_status&ENETC_RXBD_LSTATUS_F)){bd_status=le32_to_cpu((*rxbd)->r.lstatus);-size=ENETC_RXB_DMA_SIZE;+size=buffer_size;if(bd_status&ENETC_RXBD_LSTATUS_F){dma_rmb();
@@ -698,7 +700,7 @@ static int enetc_clean_rx_ring(struct enetc_bdr *rx_ring,break;skb=enetc_build_skb(rx_ring,bd_status,&rxbd,&i,-&cleaned_cnt);+&cleaned_cnt,ENETC_RXB_DMA_SIZE);if(!skb)break;
@@ -716,10 +718,174 @@ static int enetc_clean_rx_ring(struct enetc_bdr *rx_ring,returnrx_frm_cnt;}+staticvoidenetc_map_rx_buff_to_xdp(structenetc_bdr*rx_ring,inti,+structxdp_buff*xdp_buff,u16size)+{+structenetc_rx_swbd*rx_swbd=enetc_get_rx_buff(rx_ring,i,size);+void*hard_start=page_address(rx_swbd->page)+rx_swbd->page_offset;+structskb_shared_info*shinfo;++xdp_prepare_buff(xdp_buff,hard_start-rx_ring->buffer_offset,+rx_ring->buffer_offset,size,false);++shinfo=xdp_get_shared_info_from_buff(xdp_buff);+shinfo->nr_frags=0;+}++staticvoidenetc_add_rx_buff_to_xdp(structenetc_bdr*rx_ring,inti,+u16size,structxdp_buff*xdp_buff)+{+structskb_shared_info*shinfo=xdp_get_shared_info_from_buff(xdp_buff);+structenetc_rx_swbd*rx_swbd=enetc_get_rx_buff(rx_ring,i,size);+skb_frag_t*frag=&shinfo->frags[shinfo->nr_frags];++skb_frag_off_set(frag,rx_swbd->page_offset);+skb_frag_size_set(frag,size);+__skb_frag_set_page(frag,rx_swbd->page);++shinfo->nr_frags++;+}++staticvoidenetc_build_xdp_buff(structenetc_bdr*rx_ring,u32bd_status,+unionenetc_rx_bd**rxbd,int*i,+int*cleaned_cnt,structxdp_buff*xdp_buff)+{+u16size=le16_to_cpu((*rxbd)->r.buf_len);++xdp_init_buff(xdp_buff,ENETC_RXB_TRUESIZE,&rx_ring->xdp.rxq);++enetc_map_rx_buff_to_xdp(rx_ring,*i,xdp_buff,size);+(*cleaned_cnt)++;+enetc_rxbd_next(rx_ring,rxbd,i);++/* not last BD in frame? */+while(!(bd_status&ENETC_RXBD_LSTATUS_F)){+bd_status=le32_to_cpu((*rxbd)->r.lstatus);+size=ENETC_RXB_DMA_SIZE_XDP;++if(bd_status&ENETC_RXBD_LSTATUS_F){+dma_rmb();+size=le16_to_cpu((*rxbd)->r.buf_len);+}++enetc_add_rx_buff_to_xdp(rx_ring,*i,size,xdp_buff);+(*cleaned_cnt)++;+enetc_rxbd_next(rx_ring,rxbd,i);+}+}++/* Reuse the current page without performing half-page buffer flipping */+staticvoidenetc_put_xdp_buff(structenetc_bdr*rx_ring,+structenetc_rx_swbd*rx_swbd)+{+enetc_reuse_page(rx_ring,rx_swbd);++/* sync for use by the device */+dma_sync_single_range_for_device(rx_ring->dev,rx_swbd->dma,+rx_swbd->page_offset,+ENETC_RXB_DMA_SIZE_XDP,+DMA_FROM_DEVICE);++rx_swbd->page=NULL;+}++staticvoidenetc_xdp_drop(structenetc_bdr*rx_ring,intrx_ring_first,+intrx_ring_last)+{+while(rx_ring_first!=rx_ring_last){+enetc_put_xdp_buff(rx_ring,+&rx_ring->rx_swbd[rx_ring_first]);+enetc_bdr_idx_inc(rx_ring,&rx_ring_first);+}+rx_ring->stats.xdp_drops++;+}++staticintenetc_clean_rx_ring_xdp(structenetc_bdr*rx_ring,+structnapi_struct*napi,intwork_limit,+structbpf_prog*prog)+{+intrx_frm_cnt=0,rx_byte_cnt=0;+intcleaned_cnt,i;+u32xdp_act;++cleaned_cnt=enetc_bd_unused(rx_ring);+/* next descriptor to process */+i=rx_ring->next_to_clean;++while(likely(rx_frm_cnt<work_limit)){+unionenetc_rx_bd*rxbd,*orig_rxbd;+intorig_i,orig_cleaned_cnt;+structxdp_buffxdp_buff;+structsk_buff*skb;+u32bd_status;++if(cleaned_cnt>=ENETC_RXBD_BUNDLE)+cleaned_cnt-=enetc_refill_rx_ring(rx_ring,+cleaned_cnt);++rxbd=enetc_rxbd(rx_ring,i);+bd_status=le32_to_cpu(rxbd->r.lstatus);+if(!bd_status)+break;++enetc_wr_reg_hot(rx_ring->idr,BIT(rx_ring->index));+dma_rmb();/* for reading other rxbd fields */++if(enetc_check_bd_errors_and_consume(rx_ring,bd_status,+&rxbd,&i))+break;++orig_rxbd=rxbd;+orig_cleaned_cnt=cleaned_cnt;+orig_i=i;++enetc_build_xdp_buff(rx_ring,bd_status,&rxbd,&i,+&cleaned_cnt,&xdp_buff);++xdp_act=bpf_prog_run_xdp(prog,&xdp_buff);++switch(xdp_act){+caseXDP_ABORTED:+trace_xdp_exception(rx_ring->ndev,prog,xdp_act);+fallthrough;+caseXDP_DROP:+enetc_xdp_drop(rx_ring,orig_i,i);+break;+caseXDP_PASS:+rxbd=orig_rxbd;+cleaned_cnt=orig_cleaned_cnt;+i=orig_i;++skb=enetc_build_skb(rx_ring,bd_status,&rxbd,+&i,&cleaned_cnt,+ENETC_RXB_DMA_SIZE_XDP);+if(unlikely(!skb))+/* Exit the switch/case, not the loop */+break;++napi_gro_receive(napi,skb);+break;+default:+bpf_warn_invalid_xdp_action(xdp_act);+}++rx_frm_cnt++;+}++rx_ring->next_to_clean=i;++rx_ring->stats.packets+=rx_frm_cnt;+rx_ring->stats.bytes+=rx_byte_cnt;++returnrx_frm_cnt;+}+staticintenetc_poll(structnapi_struct*napi,intbudget){structenetc_int_vector*v=container_of(napi,structenetc_int_vector,napi);+structenetc_bdr*rx_ring=&v->rx_ring;+structbpf_prog*prog;boolcomplete=true;intwork_done;inti;
@@ -730,7 +896,11 @@ static int enetc_poll(struct napi_struct *napi, int budget)if(!enetc_clean_tx_ring(&v->tx_ring[i],budget))complete=false;-work_done=enetc_clean_rx_ring(&v->rx_ring,napi,budget);+prog=rx_ring->xdp.prog;+if(prog)+work_done=enetc_clean_rx_ring_xdp(rx_ring,napi,budget,prog);+else+work_done=enetc_clean_rx_ring(rx_ring,napi,budget);if(work_done==budget)complete=false;if(work_done)
@@ -1511,6 +1684,54 @@ int enetc_setup_tc(struct net_device *ndev, enum tc_setup_type type,}}+staticintenetc_setup_xdp_prog(structnet_device*dev,structbpf_prog*prog,+structnetlink_ext_ack*extack)+{+structenetc_ndev_priv*priv=netdev_priv(dev);+structbpf_prog*old_prog;+boolis_up;+inti;++/* The buffer layout is changing, so we need to drain the old+*RXbuffersandseednewones.+*/+is_up=netif_running(dev);+if(is_up)+dev_close(dev);++old_prog=xchg(&priv->xdp_prog,prog);+if(old_prog)+bpf_prog_put(old_prog);++for(i=0;i<priv->num_rx_rings;i++){+structenetc_bdr*rx_ring=priv->rx_ring[i];++rx_ring->xdp.prog=prog;++if(prog)+rx_ring->buffer_offset=XDP_PACKET_HEADROOM;+else+rx_ring->buffer_offset=ENETC_RXB_PAD;+}++if(is_up)+returndev_open(dev,extack);++return0;+}++intenetc_setup_bpf(structnet_device*dev,structnetdev_bpf*xdp)+{+switch(xdp->command){+caseXDP_SETUP_PROG:+returnenetc_setup_xdp_prog(dev,xdp->prog,xdp->extack);+default:+return-EINVAL;+}++return0;+}+structnet_device_stats*enetc_get_stats(structnet_device*ndev){structenetc_ndev_priv*priv=netdev_priv(ndev);
@@ -1727,6 +1948,28 @@ int enetc_alloc_msix(struct enetc_ndev_priv *priv)priv->int_vector[i]=v;+bdr=&v->rx_ring;+bdr->index=i;+bdr->ndev=priv->ndev;+bdr->dev=priv->dev;+bdr->bd_count=priv->rx_bd_count;+bdr->buffer_offset=ENETC_RXB_PAD;+priv->rx_ring[i]=bdr;++err=xdp_rxq_info_reg(&bdr->xdp.rxq,priv->ndev,i,0);+if(err){+kfree(v);+gotofail;+}++err=xdp_rxq_info_reg_mem_model(&bdr->xdp.rxq,+MEM_TYPE_PAGE_SHARED,NULL);+if(err){+xdp_rxq_info_unreg(&bdr->xdp.rxq);+kfree(v);+gotofail;+}+/* init defaults for adaptive IC */if(priv->ic_mode&ENETC_IC_RX_ADAPTIVE){v->rx_ictt=0x1;
@@ -1754,22 +1997,20 @@ int enetc_alloc_msix(struct enetc_ndev_priv *priv)bdr->bd_count=priv->tx_bd_count;priv->tx_ring[idx]=bdr;}--bdr=&v->rx_ring;-bdr->index=i;-bdr->ndev=priv->ndev;-bdr->dev=priv->dev;-bdr->bd_count=priv->rx_bd_count;-priv->rx_ring[i]=bdr;}return0;fail:while(i--){-netif_napi_del(&priv->int_vector[i]->napi);-cancel_work_sync(&priv->int_vector[i]->rx_dim.work);-kfree(priv->int_vector[i]);+structenetc_int_vector*v=priv->int_vector[i];+structenetc_bdr*rx_ring=&v->rx_ring;++xdp_rxq_info_unreg_mem_model(&rx_ring->xdp.rxq);+xdp_rxq_info_unreg(&rx_ring->xdp.rxq);+netif_napi_del(&v->napi);+cancel_work_sync(&v->rx_dim.work);+kfree(v);}pci_free_irq_vectors(pdev);
From: Vladimir Oltean <olteanv@gmail.com> Date: 2021-03-31 20:10:24
From: Vladimir Oltean <vladimir.oltean@nxp.com>
As explained in the XDP_TX patch, when receiving a burst of frames with
the XDP_TX verdict, there is a momentary dip in the number of available
RX buffers. The system will eventually recover as TX completions will
start kicking in and refilling our RX BD ring again. But until that
happens, we need to survive with as few out-of-buffer discards as
possible.
This increases the memory footprint of the driver in order to avoid
discards at 2.5Gbps line rate 64B packet sizes, the maximum speed
available for testing on 1 port on NXP LS1028A.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/net/ethernet/freescale/enetc/enetc.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Vladimir Oltean <olteanv@gmail.com> Date: 2021-03-31 20:10:24
From: Vladimir Oltean <vladimir.oltean@nxp.com>
For reflecting packets back into the interface they came from, we create
an array of TX software BDs derived from the RX software BDs. Therefore,
we need to extend the TX software BD structure to contain most of the
stuff that's already present in the RX software BD structure, for
reasons that will become evident in a moment.
For a frame with the XDP_TX verdict, we don't reuse any buffer right
away as we do for XDP_DROP (the same page half) or XDP_PASS (the other
page half, same as the skb code path).
Because the buffer transfers ownership from the RX ring to the TX ring,
reusing any page half right away is very dangerous. So what we can do is
we can recycle the same page half as soon as TX is complete.
The code path is:
enetc_poll
-> enetc_clean_rx_ring_xdp
-> enetc_xdp_tx
-> enetc_refill_rx_ring
(time passes, another MSI interrupt is raised)
enetc_poll
-> enetc_clean_tx_ring
-> enetc_recycle_xdp_tx_buff
But that creates a problem, because there is a potentially large time
window between enetc_xdp_tx and enetc_recycle_xdp_tx_buff, period in
which we'll have less and less RX buffers.
Basically, when the ship starts sinking, the knee-jerk reaction is to
let enetc_refill_rx_ring do what it does for the standard skb code path
(refill every 16 consumed buffers), but that turns out to be very
inefficient. The problem is that we have no rx_swbd->page at our
disposal from the enetc_reuse_page path, so enetc_refill_rx_ring would
have to call enetc_new_page for every buffer that we refill (if we
choose to refill at this early stage). Very inefficient, it only makes
the problem worse, because page allocation is an expensive process, and
CPU time is exactly what we're lacking.
Additionally, there is an even bigger problem: if we let
enetc_refill_rx_ring top up the ring's buffers again from the RX path,
remember that the buffers sent to transmission haven't disappeared
anywhere. They will be eventually sent, and processed in
enetc_clean_tx_ring, and an attempt will be made to recycle them.
But surprise, the RX ring is already full of new buffers, because we
were premature in deciding that we should refill. So not only we took
the expensive decision of allocating new pages, but now we must throw
away perfectly good and reusable buffers.
So what we do is we implement an elastic refill mechanism, which keeps
track of the number of in-flight XDP_TX buffer descriptors. We top up
the RX ring only up to the total ring capacity minus the number of BDs
that are in flight (because we know that those BDs will return to us
eventually).
The enetc driver manages 1 RX ring per CPU, and the default TX ring
management is the same. So we do XDP_TX towards the TX ring of the same
index, because it is affined to the same CPU. This will probably not
produce great results when we have a tc-taprio/tc-mqprio qdisc on the
interface, because in that case, the number of TX rings might be
greater, but I didn't add any checks for that yet (mostly because I
didn't know what checks to add).
It should also be noted that we need to change the DMA mapping direction
for RX buffers, since they may now be reflected into the TX ring of the
same device. We choose to use DMA_BIDIRECTIONAL instead of unmapping and
remapping as DMA_TO_DEVICE, because performance is better this way.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/net/ethernet/freescale/enetc/enetc.c | 217 ++++++++++++++++--
drivers/net/ethernet/freescale/enetc/enetc.h | 25 ++
.../ethernet/freescale/enetc/enetc_ethtool.c | 11 +-
3 files changed, 228 insertions(+), 25 deletions(-)
@@ -8,21 +8,20 @@#include<linux/vmalloc.h>#include<net/pkt_sched.h>-/* ENETC overhead: optional extension BD + 1 BD gap */-#define ENETC_TXBDS_NEEDED(val) ((val) + 2)-/* max # of chained Tx BDs is 15, including head and extension BD */-#define ENETC_MAX_SKB_FRAGS 13-#define ENETC_TXBDS_MAX_NEEDED ENETC_TXBDS_NEEDED(ENETC_MAX_SKB_FRAGS + 1)-staticvoidenetc_unmap_tx_buff(structenetc_bdr*tx_ring,structenetc_tx_swbd*tx_swbd){+/* For XDP_TX, pages come from RX, whereas for the other contexts where+*wehaveis_dma_page_set,thosecomefromskb_frag_dma_map.Weneed+*tomatchtheDMAmappinglength,soweneedtodifferentiatethose.+*/if(tx_swbd->is_dma_page)dma_unmap_page(tx_ring->dev,tx_swbd->dma,-tx_swbd->len,DMA_TO_DEVICE);+tx_swbd->is_xdp_tx?PAGE_SIZE:tx_swbd->len,+tx_swbd->dir);elsedma_unmap_single(tx_ring->dev,tx_swbd->dma,-tx_swbd->len,DMA_TO_DEVICE);+tx_swbd->len,tx_swbd->dir);tx_swbd->dma=0;}
@@ -38,6 +37,13 @@ static void enetc_free_tx_skb(struct enetc_bdr *tx_ring,}}+/* Let H/W know BD ring has been updated */+staticvoidenetc_update_tx_ring_tail(structenetc_bdr*tx_ring)+{+/* includes wmb() */+enetc_wr_reg_hot(tx_ring->tpir,tx_ring->next_to_use);+}+staticintenetc_map_tx_buffs(structenetc_bdr*tx_ring,structsk_buff*skb,intactive_offloads){
@@ -166,8 +174,7 @@ static int enetc_map_tx_buffs(struct enetc_bdr *tx_ring, struct sk_buff *skb,skb_tx_timestamp(skb);-/* let H/W know BD ring has been updated */-enetc_wr_reg_hot(tx_ring->tpir,i);/* includes wmb() */+enetc_update_tx_ring_tail(tx_ring);returncount;
@@ -320,6 +327,43 @@ static void enetc_tstamp_tx(struct sk_buff *skb, u64 tstamp)}}+staticvoidenetc_recycle_xdp_tx_buff(structenetc_bdr*tx_ring,+structenetc_tx_swbd*tx_swbd)+{+structenetc_ndev_priv*priv=netdev_priv(tx_ring->ndev);+structenetc_bdr*rx_ring=priv->rx_ring[tx_ring->index];+structenetc_rx_swbdrx_swbd={+.dma=tx_swbd->dma,+.page=tx_swbd->page,+.page_offset=tx_swbd->page_offset,+.dir=tx_swbd->dir,+.len=tx_swbd->len,+};++if(likely(enetc_swbd_unused(rx_ring))){+enetc_reuse_page(rx_ring,&rx_swbd);++/* sync for use by the device */+dma_sync_single_range_for_device(rx_ring->dev,rx_swbd.dma,+rx_swbd.page_offset,+ENETC_RXB_DMA_SIZE_XDP,+rx_swbd.dir);++rx_ring->stats.recycles++;+}else{+/* RX ring is already full, we need to unmap and free the+*page,sincethere'snothingusefulwecandowithit.+*/+rx_ring->stats.recycle_failures++;++dma_unmap_page(rx_ring->dev,rx_swbd.dma,PAGE_SIZE,+rx_swbd.dir);+__free_page(rx_swbd.page);+}++rx_ring->xdp.xdp_tx_in_flight--;+}+staticboolenetc_clean_tx_ring(structenetc_bdr*tx_ring,intnapi_budget){structnet_device*ndev=tx_ring->ndev;
@@ -412,7 +459,10 @@ static bool enetc_new_page(struct enetc_bdr *rx_ring,if(unlikely(!page))returnfalse;-addr=dma_map_page(rx_ring->dev,page,0,PAGE_SIZE,DMA_FROM_DEVICE);+/* For XDP_TX, we forgo dma_unmap -> dma_map */+rx_swbd->dir=xdp?DMA_BIDIRECTIONAL:DMA_FROM_DEVICE;++addr=dma_map_page(rx_ring->dev,page,0,PAGE_SIZE,rx_swbd->dir);if(unlikely(dma_mapping_error(rx_ring->dev,addr))){__free_page(page);
@@ -536,6 +586,10 @@ static void enetc_get_offloads(struct enetc_bdr *rx_ring,#endif}+/* This gets called during the non-XDP NAPI poll cycle as well as on XDP_PASS,+*soitneedstoworkwithbothDMA_FROM_DEVICEaswellasDMA_BIDIRECTIONAL+*mappedbuffers.+*/staticstructenetc_rx_swbd*enetc_get_rx_buff(structenetc_bdr*rx_ring,inti,u16size){
@@ -561,10 +615,10 @@ static void enetc_put_rx_buff(struct enetc_bdr *rx_ring,/* sync for use by the device */dma_sync_single_range_for_device(rx_ring->dev,rx_swbd->dma,rx_swbd->page_offset,-buffer_size,DMA_FROM_DEVICE);+buffer_size,rx_swbd->dir);}else{-dma_unmap_page(rx_ring->dev,rx_swbd->dma,-PAGE_SIZE,DMA_FROM_DEVICE);+dma_unmap_page(rx_ring->dev,rx_swbd->dma,PAGE_SIZE,+rx_swbd->dir);}rx_swbd->page=NULL;
@@ -718,6 +772,61 @@ static int enetc_clean_rx_ring(struct enetc_bdr *rx_ring,returnrx_frm_cnt;}+staticvoidenetc_xdp_map_tx_buff(structenetc_bdr*tx_ring,inti,+structenetc_tx_swbd*tx_swbd,+intfrm_len)+{+unionenetc_tx_bd*txbd=ENETC_TXBD(*tx_ring,i);++prefetchw(txbd);++enetc_clear_tx_bd(txbd);+txbd->addr=cpu_to_le64(tx_swbd->dma+tx_swbd->page_offset);+txbd->buf_len=cpu_to_le16(tx_swbd->len);+txbd->frm_len=cpu_to_le16(frm_len);++memcpy(&tx_ring->tx_swbd[i],tx_swbd,sizeof(*tx_swbd));+}++/* Puts in the TX ring one XDP frame, mapped as an array of TX software buffer+*descriptors.+*/+staticboolenetc_xdp_tx(structenetc_bdr*tx_ring,+structenetc_tx_swbd*xdp_tx_arr,intnum_tx_swbd)+{+structenetc_tx_swbd*tmp_tx_swbd=xdp_tx_arr;+inti,k,frm_len=tmp_tx_swbd->len;++if(unlikely(enetc_bd_unused(tx_ring)<ENETC_TXBDS_NEEDED(num_tx_swbd)))+returnfalse;++while(unlikely(!tmp_tx_swbd->is_eof)){+tmp_tx_swbd++;+frm_len+=tmp_tx_swbd->len;+}++i=tx_ring->next_to_use;++for(k=0;k<num_tx_swbd;k++){+structenetc_tx_swbd*xdp_tx_swbd=&xdp_tx_arr[k];++enetc_xdp_map_tx_buff(tx_ring,i,xdp_tx_swbd,frm_len);++/* last BD needs 'F' bit set */+if(xdp_tx_swbd->is_eof){+unionenetc_tx_bd*txbd=ENETC_TXBD(*tx_ring,i);++txbd->flags=ENETC_TXBD_FLAGS_F;+}++enetc_bdr_idx_inc(tx_ring,&i);+}++tx_ring->next_to_use=i;++returntrue;+}+staticvoidenetc_map_rx_buff_to_xdp(structenetc_bdr*rx_ring,inti,structxdp_buff*xdp_buff,u16size){
@@ -725,6 +834,9 @@ static void enetc_map_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i,void*hard_start=page_address(rx_swbd->page)+rx_swbd->page_offset;structskb_shared_info*shinfo;+/* To be used for XDP_TX */+rx_swbd->len=size;+xdp_prepare_buff(xdp_buff,hard_start-rx_ring->buffer_offset,rx_ring->buffer_offset,size,false);
@@ -739,6 +851,9 @@ static void enetc_add_rx_buff_to_xdp(struct enetc_bdr *rx_ring, int i,structenetc_rx_swbd*rx_swbd=enetc_get_rx_buff(rx_ring,i,size);skb_frag_t*frag=&shinfo->frags[shinfo->nr_frags];+/* To be used for XDP_TX */+rx_swbd->len=size;+skb_frag_off_set(frag,rx_swbd->page_offset);skb_frag_size_set(frag,size);__skb_frag_set_page(frag,rx_swbd->page);
@@ -780,15 +895,48 @@ static void enetc_put_xdp_buff(struct enetc_bdr *rx_ring,{enetc_reuse_page(rx_ring,rx_swbd);-/* sync for use by the device */dma_sync_single_range_for_device(rx_ring->dev,rx_swbd->dma,rx_swbd->page_offset,ENETC_RXB_DMA_SIZE_XDP,-DMA_FROM_DEVICE);+rx_swbd->dir);rx_swbd->page=NULL;}+/* Convert RX buffer descriptors to TX buffer descriptors. These will be+*recycledbackintotheRXringinenetc_clean_tx_ring.Weneedtoscrubthe+*RXsoftwareBDsbecausetheownershipofthebuffernolongerbelongstothe+*RXring,soenetc_refill_rx_ringmaynotreuserx_swbd->page.+*/+staticintenetc_rx_swbd_to_xdp_tx_swbd(structenetc_tx_swbd*xdp_tx_arr,+structenetc_bdr*rx_ring,+intrx_ring_first,intrx_ring_last)+{+intn=0;++for(;rx_ring_first!=rx_ring_last;+n++,enetc_bdr_idx_inc(rx_ring,&rx_ring_first)){+structenetc_rx_swbd*rx_swbd=&rx_ring->rx_swbd[rx_ring_first];+structenetc_tx_swbd*tx_swbd=&xdp_tx_arr[n];++/* No need to dma_map, we already have DMA_BIDIRECTIONAL */+tx_swbd->dma=rx_swbd->dma;+tx_swbd->dir=rx_swbd->dir;+tx_swbd->page=rx_swbd->page;+tx_swbd->page_offset=rx_swbd->page_offset;+tx_swbd->len=rx_swbd->len;+tx_swbd->is_dma_page=true;+tx_swbd->is_xdp_tx=true;+tx_swbd->is_eof=false;+memset(rx_swbd,0,sizeof(*rx_swbd));+}++/* We rely on caller providing an rx_ring_last > rx_ring_first */+xdp_tx_arr[n-1].is_eof=true;++returnn;+}+staticvoidenetc_xdp_drop(structenetc_bdr*rx_ring,intrx_ring_first,intrx_ring_last){
@@ -804,6 +952,10 @@ static int enetc_clean_rx_ring_xdp(struct enetc_bdr *rx_ring,structnapi_struct*napi,intwork_limit,structbpf_prog*prog){+structenetc_tx_swbdxdp_tx_arr[ENETC_MAX_SKB_FRAGS]={0};+structenetc_ndev_priv*priv=netdev_priv(rx_ring->ndev);+structenetc_bdr*tx_ring=priv->tx_ring[rx_ring->index];+intxdp_tx_bd_cnt,xdp_tx_frm_cnt=0;intrx_frm_cnt=0,rx_byte_cnt=0;intcleaned_cnt,i;u32xdp_act;
@@ -819,10 +971,6 @@ static int enetc_clean_rx_ring_xdp(struct enetc_bdr *rx_ring,structsk_buff*skb;u32bd_status;-if(cleaned_cnt>=ENETC_RXBD_BUNDLE)-cleaned_cnt-=enetc_refill_rx_ring(rx_ring,-cleaned_cnt);-rxbd=enetc_rxbd(rx_ring,i);bd_status=le32_to_cpu(rxbd->r.lstatus);if(!bd_status)
@@ -865,6 +1013,20 @@ static int enetc_clean_rx_ring_xdp(struct enetc_bdr *rx_ring,napi_gro_receive(napi,skb);break;+caseXDP_TX:+xdp_tx_bd_cnt=enetc_rx_swbd_to_xdp_tx_swbd(xdp_tx_arr,+rx_ring,+orig_i,i);++if(!enetc_xdp_tx(tx_ring,xdp_tx_arr,xdp_tx_bd_cnt)){+enetc_xdp_drop(rx_ring,orig_i,i);+tx_ring->stats.xdp_tx_drops++;+}else{+tx_ring->stats.xdp_tx+=xdp_tx_bd_cnt;+rx_ring->xdp.xdp_tx_in_flight+=xdp_tx_bd_cnt;+xdp_tx_frm_cnt++;+}+break;default:bpf_warn_invalid_xdp_action(xdp_act);}
@@ -877,6 +1039,13 @@ static int enetc_clean_rx_ring_xdp(struct enetc_bdr *rx_ring,rx_ring->stats.packets+=rx_frm_cnt;rx_ring->stats.bytes+=rx_byte_cnt;+if(xdp_tx_frm_cnt)+enetc_update_tx_ring_tail(tx_ring);++if(cleaned_cnt>rx_ring->xdp.xdp_tx_in_flight)+enetc_refill_rx_ring(rx_ring,enetc_bd_unused(rx_ring)-+rx_ring->xdp.xdp_tx_in_flight);+returnrx_frm_cnt;}
@@ -21,11 +21,15 @@structenetc_tx_swbd{structsk_buff*skb;dma_addr_tdma;+structpage*page;/* valid only if is_xdp_tx */+u16page_offset;/* valid only if is_xdp_tx */u16len;+enumdma_data_directiondir;u8is_dma_page:1;u8check_wb:1;u8do_tstamp:1;u8is_eof:1;+u8is_xdp_tx:1;};#define ENETC_RX_MAXFRM_SIZE ENETC_MAC_MAXFRM_SIZE
@@ -40,18 +44,31 @@ struct enetc_rx_swbd {dma_addr_tdma;structpage*page;u16page_offset;+enumdma_data_directiondir;+u16len;};+/* ENETC overhead: optional extension BD + 1 BD gap */+#define ENETC_TXBDS_NEEDED(val) ((val) + 2)+/* max # of chained Tx BDs is 15, including head and extension BD */+#define ENETC_MAX_SKB_FRAGS 13+#define ENETC_TXBDS_MAX_NEEDED ENETC_TXBDS_NEEDED(ENETC_MAX_SKB_FRAGS + 1)+structenetc_ring_stats{unsignedintpackets;unsignedintbytes;unsignedintrx_alloc_errs;unsignedintxdp_drops;+unsignedintxdp_tx;+unsignedintxdp_tx_drops;+unsignedintrecycles;+unsignedintrecycle_failures;};structenetc_xdp_data{structxdp_rxq_inforxq;structbpf_prog*prog;+intxdp_tx_in_flight;};#define ENETC_RX_RING_DEFAULT_SIZE 512
@@ -104,6 +121,14 @@ static inline int enetc_bd_unused(struct enetc_bdr *bdr)returnbdr->bd_count+bdr->next_to_clean-bdr->next_to_use-1;}+staticinlineintenetc_swbd_unused(structenetc_bdr*bdr)+{+if(bdr->next_to_clean>bdr->next_to_alloc)+returnbdr->next_to_clean-bdr->next_to_alloc-1;++returnbdr->bd_count+bdr->next_to_clean-bdr->next_to_alloc-1;+}+/* Control BD ring */#define ENETC_CBDR_DEFAULT_SIZE 64structenetc_cbdr{
@@ -193,10 +193,14 @@ static const char rx_ring_stats[][ETH_GSTRING_LEN] = {"Rx ring %2d frames","Rx ring %2d alloc errors","Rx ring %2d XDP drops",+"Rx ring %2d recycles",+"Rx ring %2d recycle failures",};staticconstchartx_ring_stats[][ETH_GSTRING_LEN]={"Tx ring %2d frames",+"Tx ring %2d XDP frames",+"Tx ring %2d XDP drops",};staticintenetc_get_sset_count(structnet_device*ndev,intsset)
From: Vladimir Oltean <olteanv@gmail.com> Date: 2021-03-31 20:10:24
From: Vladimir Oltean <vladimir.oltean@nxp.com>
The driver implementation of the XDP_REDIRECT action reuses parts from
XDP_TX, most notably the enetc_xdp_tx function which transmits an array
of TX software BDs. Only this time, the buffers don't have DMA mappings,
we need to create them.
When a BPF program reaches the XDP_REDIRECT verdict for a frame, we can
employ the same buffer reuse strategy as for the normal processing path
and for XDP_PASS: we can flip to the other page half and seed that to
the RX ring.
Note that scatter/gather support is there, but disabled due to lack of
multi-buffer support in XDP (which is added by this series):
https://patchwork.kernel.org/project/netdevbpf/cover/cover.1616179034.git.lorenzo@kernel.org/
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/net/ethernet/freescale/enetc/enetc.c | 212 +++++++++++++++++-
drivers/net/ethernet/freescale/enetc/enetc.h | 11 +-
.../ethernet/freescale/enetc/enetc_ethtool.c | 6 +
.../net/ethernet/freescale/enetc/enetc_pf.c | 1 +
4 files changed, 218 insertions(+), 12 deletions(-)
@@ -969,6 +1118,7 @@ static int enetc_clean_rx_ring_xdp(struct enetc_bdr *rx_ring,intorig_i,orig_cleaned_cnt;structxdp_buffxdp_buff;structsk_buff*skb;+inttmp_orig_i,err;u32bd_status;rxbd=enetc_rxbd(rx_ring,i);
@@ -1026,6 +1176,43 @@ static int enetc_clean_rx_ring_xdp(struct enetc_bdr *rx_ring,rx_ring->xdp.xdp_tx_in_flight+=xdp_tx_bd_cnt;xdp_tx_frm_cnt++;}+break;+caseXDP_REDIRECT:+/* xdp_return_frame does not support S/G in the sense+*thatitleaksthefragments(__xdp_returnshouldnot+*callpage_frag_freeonlyfortheinitialbuffer).+*UntilXDP_REDIRECTgainssupportforS/Glet'skeep+*thecodestructureinplace,butdead.Wedropthe+*S/Gframesourselvestoavoidmemoryleakswhich+*wouldotherwiseleavethekernelOOM.+*/+if(unlikely(cleaned_cnt-orig_cleaned_cnt!=1)){+enetc_xdp_drop(rx_ring,orig_i,i);+rx_ring->stats.xdp_redirect_sg++;+break;+}++tmp_orig_i=orig_i;++while(orig_i!=i){+enetc_put_rx_buff(rx_ring,+&rx_ring->rx_swbd[orig_i]);+enetc_bdr_idx_inc(rx_ring,&orig_i);+}++err=xdp_do_redirect(rx_ring->ndev,&xdp_buff,prog);+if(unlikely(err)){+enetc_xdp_free(rx_ring,tmp_orig_i,i);+}else{+xdp_redirect_frm_cnt++;+rx_ring->stats.xdp_redirect++;+}++if(unlikely(xdp_redirect_frm_cnt>ENETC_DEFAULT_TX_WORK)){+xdp_do_flush_map();+xdp_redirect_frm_cnt=0;+}+break;default:bpf_warn_invalid_xdp_action(xdp_act);
@@ -1039,6 +1226,9 @@ static int enetc_clean_rx_ring_xdp(struct enetc_bdr *rx_ring,rx_ring->stats.packets+=rx_frm_cnt;rx_ring->stats.bytes+=rx_byte_cnt;+if(xdp_redirect_frm_cnt)+xdp_do_flush_map();+if(xdp_tx_frm_cnt)enetc_update_tx_ring_tail(tx_ring);
@@ -19,7 +19,10 @@(ETH_FCS_LEN+ETH_HLEN+VLAN_HLEN))structenetc_tx_swbd{-structsk_buff*skb;+union{+structsk_buff*skb;+structxdp_frame*xdp_frame;+};dma_addr_tdma;structpage*page;/* valid only if is_xdp_tx */u16page_offset;/* valid only if is_xdp_tx */
Hello:
This series was applied to netdev/net-next.git (refs/heads/master):
On Wed, 31 Mar 2021 23:08:48 +0300 you wrote:
From: Vladimir Oltean <vladimir.oltean@nxp.com>
This series adds support to the enetc driver for the basic XDP primitives.
The ENETC is a network controller found inside the NXP LS1028A SoC,
which is a dual-core Cortex A72 device for industrial networking,
with the CPUs clocked at up to 1.3 GHz. On this platform, there are 4
ENETC ports and a 6-port embedded DSA switch, in a topology that looks
like this:
[...]
From: Vladimir Oltean <olteanv@gmail.com> Date: 2021-03-31 22:56:48
On Wed, Mar 31, 2021 at 10:20:18PM +0000, patchwork-bot+netdevbpf@kernel.org wrote:
Hello:
This series was applied to netdev/net-next.git (refs/heads/master):
On Wed, 31 Mar 2021 23:08:48 +0300 you wrote:
quoted
From: Vladimir Oltean <vladimir.oltean@nxp.com>
This series adds support to the enetc driver for the basic XDP primitives.
The ENETC is a network controller found inside the NXP LS1028A SoC,
which is a dual-core Cortex A72 device for industrial networking,
with the CPUs clocked at up to 1.3 GHz. On this platform, there are 4
ENETC ports and a 6-port embedded DSA switch, in a topology that looks
like this:
[...]
Let's play a drinking game, the winner is who doesn't get drunk every
time Dave merges a 9-patch series with no review in less than two hours
after it was posted :D
Now in all seriousness, I'm very much open to receiving feedback still.
In a way, I appreciate seeing the patches merged as is, since further
fixups made based on review will add more nuance and color to the git
log, and it will be easier to understand why things were done or
modified in a certain way, etc, as opposed to the alternative which is
to keep amending the same blank 'add support for XDP_TX / XDP_REDIRECT /
whatever', with never enough attention given to the finer points.
What mechanism guarantees that this won't overflow the array? :)
Which array, the array of TX rings?
You mean that it's possible to receive a TC_SETUP_QDISC_MQPRIO or
TC_SETUP_QDISC_TAPRIO with num_tc == 1, and we have 2 CPUs?
Well, yeah, I don't know what's the proper way to deal with that. Ideas?
From: Vladimir Oltean <vladimir.oltean@nxp.com>
The driver implementation of the XDP_REDIRECT action reuses parts from
XDP_TX, most notably the enetc_xdp_tx function which transmits an array
of TX software BDs. Only this time, the buffers don't have DMA mappings,
we need to create them.
When a BPF program reaches the XDP_REDIRECT verdict for a frame, we can
employ the same buffer reuse strategy as for the normal processing path
and for XDP_PASS: we can flip to the other page half and seed that to
the RX ring.
Note that scatter/gather support is there, but disabled due to lack of
multi-buffer support in XDP (which is added by this series):
https://patchwork.kernel.org/project/netdevbpf/cover/cover.1616179034.git.lorenzo@kernel.org/
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
drivers/net/ethernet/freescale/enetc/enetc.c | 212 +++++++++++++++++-
drivers/net/ethernet/freescale/enetc/enetc.h | 11 +-
.../ethernet/freescale/enetc/enetc_ethtool.c | 6 +
.../net/ethernet/freescale/enetc/enetc_pf.c | 1 +
4 files changed, 218 insertions(+), 12 deletions(-)
On Wed, Mar 31, 2021 at 10:20:18PM +0000, patchwork-bot+netdevbpf@kernel.org wrote:
quoted
Hello:
This series was applied to netdev/net-next.git (refs/heads/master):
On Wed, 31 Mar 2021 23:08:48 +0300 you wrote:
quoted
From: Vladimir Oltean <vladimir.oltean@nxp.com>
This series adds support to the enetc driver for the basic XDP primitives.
The ENETC is a network controller found inside the NXP LS1028A SoC,
which is a dual-core Cortex A72 device for industrial networking,
with the CPUs clocked at up to 1.3 GHz. On this platform, there are 4
ENETC ports and a 6-port embedded DSA switch, in a topology that looks
like this:
[...]
Let's play a drinking game, the winner is who doesn't get drunk every
time Dave merges a 9-patch series with no review in less than two hours
after it was posted :D
No thanks! I value my liver too much for that ;)
(I was wondering about whether there was some black magic going on here
that I had missed; glad to see it's not just me)
Now in all seriousness, I'm very much open to receiving feedback
still.
Good - sent you one comment on the REDIRECT support to start with :)
-Toke
What mechanism guarantees that this won't overflow the array? :)
Which array, the array of TX rings?
Yes.
The problem isn't even accessing an out-of-bounds element in the TX ring array.
As it turns out, I had a relatively superficial understanding of how
things are organized, but let me try to explain.
The number of TX rings is a configurable resource (between PFs and VFs)
and we read the capability at probe time:
enetc_get_si_caps:
val = enetc_rd(hw, ENETC_SICAPR0);
si->num_rx_rings = (val >> 16) & 0xff;
si->num_tx_rings = val & 0xff;
enetc_init_si_rings_params:
priv->num_tx_rings = si->num_tx_rings;
In any case, the TX array is declared as:
struct enetc_ndev_priv {
struct enetc_bdr *tx_ring[16];
struct enetc_bdr *rx_ring[16];
};
because that's the maximum hardware capability.
The priv->tx_ring array is populated in:
enetc_alloc_msix:
/* # of tx rings per int vector */
v_tx_rings = priv->num_tx_rings / priv->bdr_int_num;
for (i = 0; i < priv->bdr_int_num; i++) {
for (j = 0; j < v_tx_rings; j++) {
if (priv->bdr_int_num == ENETC_MAX_BDR_INT)
idx = 2 * j + i; /* 2 CPUs */
else
idx = j + i * v_tx_rings; /* default */
priv->tx_ring[idx] = bdr;
}
}
priv->bdr_int_num is set to "num_online_cpus()".
On LS1028A, it can be either 1 or 2 (and the ENETC_MAX_BDR_INT macro is
equal to 2).
Otherwise said, the convoluted logic above does the following:
- It affines an MSI interrupt vector per CPU
- It affines an RX ring per MSI vector, hence per CPU
- It balances the fixed number of TX rings (say 8) among the available
MSI vectors, hence CPUs (say 2). It does this by iterating with i
through the RX MSI interrupt vectors, and with j through the number of
TX rings per MSI vector.
This logic maps:
- the even TX rings to CPU 0 and the odd TX rings to CPU 1, if 2 CPUs
are used
- all TX rings to CPU 0, if 1 CPU is used
This is done because we have this logic in enetc_poll:
for (i = 0; i < v->count_tx_rings; i++)
if (!enetc_clean_tx_ring(&v->tx_ring[i], budget))
complete = false;
for processing the TX completions of a given group of TX rings in the RX
MSI interrupt handler of a certain CPU.
Otherwise said, priv->tx_ring[i] is always BD ring i, and that mapping
never changes. All 8 TX rings are enabled and available for use.
What I knew about tc-taprio and tc-mqprio is that they only enqueue to
TX queues [0, num_tc-1] because of this, as it turns out:
enetc_xmit:
tx_ring = priv->tx_ring[skb->queue_mapping];
where skb->queue_mapping is given by:
err = netif_set_real_num_tx_queues(ndev, priv->num_tx_rings);
and by this, respectively, from the mqprio code path:
netif_set_real_num_tx_queues(ndev, num_tc);
As for why XDP works, and priv->tx_ring[smp_processor_id()] is:
- TX ring 0 for CPU 0 and TX ring 1 for CPU 1, if 2 CPUs are used
- TX ring 0, if 1 CPU is used
The TX completions in the first case are handled by:
- CPU 0 for TX ring 0 (because it is even) and CPU 1 for TX ring 1
(because it is odd), if 2 CPUs are used, due to the mapping I talked
about earlier
- CPU 0 if only 1 CPU is used
Right - thank you for the details! So what are the constraints on the
configuration. Specifically, given two netdevs on the same device, is it
possible that the system can ever end up in a situation where one device
has two *RXQs* configured, and the other only one *TXQ*. Because then
you could get a redirect from RXQ 1 on one device, which would also end
up trying to transmit on TXQ 1 on the other device; and that would break
if that other device only has TXQ 0 configured... Same thing if a single
device has 2 RXQs but only one TXQ (it can redirect to itself).
quoted
quoted
You mean that it's possible to receive a TC_SETUP_QDISC_MQPRIO or
TC_SETUP_QDISC_TAPRIO with num_tc == 1, and we have 2 CPUs?
Not just that, this ndo can be called on arbitrary CPUs after a
redirect. The code just calls through from the XDP receive path so which
CPU it ends up on depends on the RSS+IRQ config of the other device,
which may not even be the same driver; i.e., you have no control over
that... :)
What do you mean by "arbitrary" CPU? You can't plug CPUs in, it's a dual
core system... Why does the source ifindex matter at all? I'm using the
TX ring affined to the CPU that ndo_xdp_xmit is currently running on.
See, this is why I asked 'what mechanism ensures'. Because if that
mechanism is 'this driver is only ever used on a system with fewer CPUs
than TXQs', then that's of course fine :)
But there are drivers that do basically the same thing as what you've
done here, *without* having such an assurance, and just looking at that
function it's not obvious that there's an out-of-band reason why it's
safe. And I literally just came from looking at such a case when I
replied to your initial patch...
quoted
quoted
Well, yeah, I don't know what's the proper way to deal with that. Ideas?
Well the obvious one is just:
tx_ring = priv->tx_ring[smp_processor_id() % num_ring_ids];
and then some kind of locking to deal with multiple CPUs accessing the
same TX ring...
By multiple CPUs accessing the same TX ring, you mean locking between
ndo_xdp_xmit and ndo_start_xmit? Can that even happen if the hardware
architecture is to have at least as many TX rings as CPUs?
Because otherwise, I see that ndo_xdp_xmit is only called from
xdp_do_flush, which is in softirq context, which to my very rudimentary
knowledge run with bottom halves, thus preemption, disabled? So I don't
think it's possible for ndo_xdp_xmit and ndo_xmit, or even two
ndo_xdp_xmit instances, to access the same TX ring?
Yup, I think you're right about that. The "we always have more TXQs than
CPUs" condition was the bit I was missing (and of course you're *sure*
that this would never change sometime in the future, right? ;)).
Sorry, I'm sure these are trivial questions, but I would like to really
understand what I need to change and why :D
Given the above I think the only potentially breaking thing is the
#RXQ > #TXQ case I outlined. And maybe a comment documenting why indexing
the tx_ring array by smp_processor_id() is safe would be nice? :)
-Toke
What mechanism guarantees that this won't overflow the array? :)
Which array, the array of TX rings?
Yes.
You mean that it's possible to receive a TC_SETUP_QDISC_MQPRIO or
TC_SETUP_QDISC_TAPRIO with num_tc == 1, and we have 2 CPUs?
Not just that, this ndo can be called on arbitrary CPUs after a
redirect. The code just calls through from the XDP receive path so which
CPU it ends up on depends on the RSS+IRQ config of the other device,
which may not even be the same driver; i.e., you have no control over
that... :)
Well, yeah, I don't know what's the proper way to deal with that. Ideas?
Well the obvious one is just:
tx_ring = priv->tx_ring[smp_processor_id() % num_ring_ids];
and then some kind of locking to deal with multiple CPUs accessing the
same TX ring...
-Toke
What mechanism guarantees that this won't overflow the array? :)
Which array, the array of TX rings?
Yes.
The problem isn't even accessing an out-of-bounds element in the TX ring array.
As it turns out, I had a relatively superficial understanding of how
things are organized, but let me try to explain.
The number of TX rings is a configurable resource (between PFs and VFs)
and we read the capability at probe time:
enetc_get_si_caps:
val = enetc_rd(hw, ENETC_SICAPR0);
si->num_rx_rings = (val >> 16) & 0xff;
si->num_tx_rings = val & 0xff;
enetc_init_si_rings_params:
priv->num_tx_rings = si->num_tx_rings;
In any case, the TX array is declared as:
struct enetc_ndev_priv {
struct enetc_bdr *tx_ring[16];
struct enetc_bdr *rx_ring[16];
};
because that's the maximum hardware capability.
The priv->tx_ring array is populated in:
enetc_alloc_msix:
/* # of tx rings per int vector */
v_tx_rings = priv->num_tx_rings / priv->bdr_int_num;
for (i = 0; i < priv->bdr_int_num; i++) {
for (j = 0; j < v_tx_rings; j++) {
if (priv->bdr_int_num == ENETC_MAX_BDR_INT)
idx = 2 * j + i; /* 2 CPUs */
else
idx = j + i * v_tx_rings; /* default */
priv->tx_ring[idx] = bdr;
}
}
priv->bdr_int_num is set to "num_online_cpus()".
On LS1028A, it can be either 1 or 2 (and the ENETC_MAX_BDR_INT macro is
equal to 2).
Otherwise said, the convoluted logic above does the following:
- It affines an MSI interrupt vector per CPU
- It affines an RX ring per MSI vector, hence per CPU
- It balances the fixed number of TX rings (say 8) among the available
MSI vectors, hence CPUs (say 2). It does this by iterating with i
through the RX MSI interrupt vectors, and with j through the number of
TX rings per MSI vector.
This logic maps:
- the even TX rings to CPU 0 and the odd TX rings to CPU 1, if 2 CPUs
are used
- all TX rings to CPU 0, if 1 CPU is used
This is done because we have this logic in enetc_poll:
for (i = 0; i < v->count_tx_rings; i++)
if (!enetc_clean_tx_ring(&v->tx_ring[i], budget))
complete = false;
for processing the TX completions of a given group of TX rings in the RX
MSI interrupt handler of a certain CPU.
Otherwise said, priv->tx_ring[i] is always BD ring i, and that mapping
never changes. All 8 TX rings are enabled and available for use.
What I knew about tc-taprio and tc-mqprio is that they only enqueue to
TX queues [0, num_tc-1] because of this, as it turns out:
enetc_xmit:
tx_ring = priv->tx_ring[skb->queue_mapping];
where skb->queue_mapping is given by:
err = netif_set_real_num_tx_queues(ndev, priv->num_tx_rings);
and by this, respectively, from the mqprio code path:
netif_set_real_num_tx_queues(ndev, num_tc);
As for why XDP works, and priv->tx_ring[smp_processor_id()] is:
- TX ring 0 for CPU 0 and TX ring 1 for CPU 1, if 2 CPUs are used
- TX ring 0, if 1 CPU is used
The TX completions in the first case are handled by:
- CPU 0 for TX ring 0 (because it is even) and CPU 1 for TX ring 1
(because it is odd), if 2 CPUs are used, due to the mapping I talked
about earlier
- CPU 0 if only 1 CPU is used
quoted
You mean that it's possible to receive a TC_SETUP_QDISC_MQPRIO or
TC_SETUP_QDISC_TAPRIO with num_tc == 1, and we have 2 CPUs?
Not just that, this ndo can be called on arbitrary CPUs after a
redirect. The code just calls through from the XDP receive path so which
CPU it ends up on depends on the RSS+IRQ config of the other device,
which may not even be the same driver; i.e., you have no control over
that... :)
What do you mean by "arbitrary" CPU? You can't plug CPUs in, it's a dual
core system... Why does the source ifindex matter at all? I'm using the
TX ring affined to the CPU that ndo_xdp_xmit is currently running on.
quoted
Well, yeah, I don't know what's the proper way to deal with that. Ideas?
Well the obvious one is just:
tx_ring = priv->tx_ring[smp_processor_id() % num_ring_ids];
and then some kind of locking to deal with multiple CPUs accessing the
same TX ring...
By multiple CPUs accessing the same TX ring, you mean locking between
ndo_xdp_xmit and ndo_start_xmit? Can that even happen if the hardware
architecture is to have at least as many TX rings as CPUs?
Because otherwise, I see that ndo_xdp_xmit is only called from
xdp_do_flush, which is in softirq context, which to my very rudimentary
knowledge run with bottom halves, thus preemption, disabled? So I don't
think it's possible for ndo_xdp_xmit and ndo_xmit, or even two
ndo_xdp_xmit instances, to access the same TX ring?
Sorry, I'm sure these are trivial questions, but I would like to really
understand what I need to change and why :D
What mechanism guarantees that this won't overflow the array? :)
Which array, the array of TX rings?
Yes.
The problem isn't even accessing an out-of-bounds element in the TX ring array.
As it turns out, I had a relatively superficial understanding of how
things are organized, but let me try to explain.
The number of TX rings is a configurable resource (between PFs and VFs)
and we read the capability at probe time:
enetc_get_si_caps:
val = enetc_rd(hw, ENETC_SICAPR0);
si->num_rx_rings = (val >> 16) & 0xff;
si->num_tx_rings = val & 0xff;
enetc_init_si_rings_params:
priv->num_tx_rings = si->num_tx_rings;
In any case, the TX array is declared as:
struct enetc_ndev_priv {
struct enetc_bdr *tx_ring[16];
struct enetc_bdr *rx_ring[16];
};
because that's the maximum hardware capability.
The priv->tx_ring array is populated in:
enetc_alloc_msix:
/* # of tx rings per int vector */
v_tx_rings = priv->num_tx_rings / priv->bdr_int_num;
for (i = 0; i < priv->bdr_int_num; i++) {
for (j = 0; j < v_tx_rings; j++) {
if (priv->bdr_int_num == ENETC_MAX_BDR_INT)
idx = 2 * j + i; /* 2 CPUs */
else
idx = j + i * v_tx_rings; /* default */
priv->tx_ring[idx] = bdr;
}
}
priv->bdr_int_num is set to "num_online_cpus()".
On LS1028A, it can be either 1 or 2 (and the ENETC_MAX_BDR_INT macro is
equal to 2).
Otherwise said, the convoluted logic above does the following:
- It affines an MSI interrupt vector per CPU
- It affines an RX ring per MSI vector, hence per CPU
- It balances the fixed number of TX rings (say 8) among the available
MSI vectors, hence CPUs (say 2). It does this by iterating with i
through the RX MSI interrupt vectors, and with j through the number of
TX rings per MSI vector.
This logic maps:
- the even TX rings to CPU 0 and the odd TX rings to CPU 1, if 2 CPUs
are used
- all TX rings to CPU 0, if 1 CPU is used
This is done because we have this logic in enetc_poll:
for (i = 0; i < v->count_tx_rings; i++)
if (!enetc_clean_tx_ring(&v->tx_ring[i], budget))
complete = false;
for processing the TX completions of a given group of TX rings in the RX
MSI interrupt handler of a certain CPU.
Otherwise said, priv->tx_ring[i] is always BD ring i, and that mapping
never changes. All 8 TX rings are enabled and available for use.
What I knew about tc-taprio and tc-mqprio is that they only enqueue to
TX queues [0, num_tc-1] because of this, as it turns out:
enetc_xmit:
tx_ring = priv->tx_ring[skb->queue_mapping];
where skb->queue_mapping is given by:
err = netif_set_real_num_tx_queues(ndev, priv->num_tx_rings);
and by this, respectively, from the mqprio code path:
netif_set_real_num_tx_queues(ndev, num_tc);
As for why XDP works, and priv->tx_ring[smp_processor_id()] is:
- TX ring 0 for CPU 0 and TX ring 1 for CPU 1, if 2 CPUs are used
- TX ring 0, if 1 CPU is used
The TX completions in the first case are handled by:
- CPU 0 for TX ring 0 (because it is even) and CPU 1 for TX ring 1
(because it is odd), if 2 CPUs are used, due to the mapping I talked
about earlier
- CPU 0 if only 1 CPU is used
Right - thank you for the details! So what are the constraints on the
configuration. Specifically, given two netdevs on the same device, is it
possible that the system can ever end up in a situation where one device
has two *RXQs* configured, and the other only one *TXQ*. Because then
you could get a redirect from RXQ 1 on one device, which would also end
up trying to transmit on TXQ 1 on the other device; and that would break
if that other device only has TXQ 0 configured... Same thing if a single
device has 2 RXQs but only one TXQ (it can redirect to itself).
I discover more and more of the driver as I talk to you, I like it :D
So I said that there is a maximum number of RX and TX rings splittable
between the PF and its VFs, but I wasn't exactly sure where that
configuration is done. I found it now.
enetc_port_si_configure: (SI == station interface)
- read Port capability register 0 (PCAPR0) to determine how many
RX rings and TX rings the hardware has for this port (PFs + VFs)
in total.
- assign num_rings = min(TX rings, RX rings)
- try to assign 8 TX rings and 8 RX rings to the PF
- if this fails, just assign ${num_rings} TX rings and
${num_rings} RX rings to the PF
- split the remaining RX and TX rings to the number of
configured VFs (example: if there are 16 RX rings and 16 TX
rings for a port with 2 VFs, the driver assigns 8RX/8TX rings
for the PF, and 4RX/4TX rings for each VF).
- if we couldn't assign 8RX/8TX rings for the PF in the
previous step, we don't assign any ring to the VF
So yeah, we have an equal number of RX and TX rings. The driver,
however, only uses 2 RX rings _actively_: one per CPU. The other 6, I
don't know, I guess I can use them for AF_XDP (I haven't looked very
closely at that yet), at the moment they're pretty much unused, even if
reserved and not given to VFs.
quoted
quoted
quoted
You mean that it's possible to receive a TC_SETUP_QDISC_MQPRIO or
TC_SETUP_QDISC_TAPRIO with num_tc == 1, and we have 2 CPUs?
Not just that, this ndo can be called on arbitrary CPUs after a
redirect. The code just calls through from the XDP receive path so which
CPU it ends up on depends on the RSS+IRQ config of the other device,
which may not even be the same driver; i.e., you have no control over
that... :)
What do you mean by "arbitrary" CPU? You can't plug CPUs in, it's a dual
core system... Why does the source ifindex matter at all? I'm using the
TX ring affined to the CPU that ndo_xdp_xmit is currently running on.
See, this is why I asked 'what mechanism ensures'. Because if that
mechanism is 'this driver is only ever used on a system with fewer CPUs
than TXQs', then that's of course fine :)
But there are drivers that do basically the same thing as what you've
done here, *without* having such an assurance, and just looking at that
function it's not obvious that there's an out-of-band reason why it's
safe. And I literally just came from looking at such a case when I
replied to your initial patch...
Maybe you were confused seeing that this is a PCI device, thinking it's
a plug-in card or something, therefore we don't get to choose the number
of CPUs that the host has. In hindsight, I don't know why you didn't ask
about this, it is pretty strange when you think about it.
It is actually more like a platform device with a PCI front-end - we
found this loophole in the PCI standard where you can create a "root
complex/integrated endpoint" which is basically an ECAM where the config
space contains PFs corresponding to some platform devices in the SoC (in
our case, all 4 Ethernet ports have their own PF, the switch has its own
PF, same thing for the MDIO controller and the 1588 timer). Their
register map is exposed as a number of BARs which use Enhanced
Allocation, so the generic PCI ECAM driver doesn't need to create any
translation windows for these addresses, it just uses what's in there,
which, surprise, is the actual base address of the peripheral in the
SoC's memory space.
We do that because we gain a lot of cool stuff by appearing as PCI
devices to system software, like for example multiple interfaces on top
of a 'shared MAC' are simply mapped over SR-IOV.
So it just 'smells' like PCI, but they're regular memory-mapped devices,
there is no PCI transaction layer or physical layer. At the moment the
LS1028A is the only SoC running Linux that integrates the ENETC block,
so we fully control the environment.
quoted
quoted
quoted
Well, yeah, I don't know what's the proper way to deal with that. Ideas?
Well the obvious one is just:
tx_ring = priv->tx_ring[smp_processor_id() % num_ring_ids];
and then some kind of locking to deal with multiple CPUs accessing the
same TX ring...
By multiple CPUs accessing the same TX ring, you mean locking between
ndo_xdp_xmit and ndo_start_xmit? Can that even happen if the hardware
architecture is to have at least as many TX rings as CPUs?
Because otherwise, I see that ndo_xdp_xmit is only called from
xdp_do_flush, which is in softirq context, which to my very rudimentary
knowledge run with bottom halves, thus preemption, disabled? So I don't
think it's possible for ndo_xdp_xmit and ndo_xmit, or even two
ndo_xdp_xmit instances, to access the same TX ring?
Yup, I think you're right about that. The "we always have more TXQs than
CPUs" condition was the bit I was missing (and of course you're *sure*
that this would never change sometime in the future, right? ;)).
I'm pretty sure, yeah, we build the SoCs and one of the requirements we
have is that every ENETC PF has enough TX rings in order for every CPU
to have its own one. That helps a lot with avoiding contention and
simplifying the driver. Maybe I'll use this opportunity to talk again to
the hardware design guys and make sure that the next SoCs with Linux
follow the same pattern as LS1028A, although I see no reason why not.
quoted
Sorry, I'm sure these are trivial questions, but I would like to really
understand what I need to change and why :D
Given the above I think the only potentially breaking thing is the
#RXQ > #TXQ case I outlined. And maybe a comment documenting why indexing
the tx_ring array by smp_processor_id() is safe would be nice? :)
Sure, which part exactly do you think would explain it best? Should I
add a reference to enetc_port_si_configure?
What mechanism guarantees that this won't overflow the array? :)
Which array, the array of TX rings?
Yes.
The problem isn't even accessing an out-of-bounds element in the TX ring array.
As it turns out, I had a relatively superficial understanding of how
things are organized, but let me try to explain.
The number of TX rings is a configurable resource (between PFs and VFs)
and we read the capability at probe time:
enetc_get_si_caps:
val = enetc_rd(hw, ENETC_SICAPR0);
si->num_rx_rings = (val >> 16) & 0xff;
si->num_tx_rings = val & 0xff;
enetc_init_si_rings_params:
priv->num_tx_rings = si->num_tx_rings;
In any case, the TX array is declared as:
struct enetc_ndev_priv {
struct enetc_bdr *tx_ring[16];
struct enetc_bdr *rx_ring[16];
};
because that's the maximum hardware capability.
The priv->tx_ring array is populated in:
enetc_alloc_msix:
/* # of tx rings per int vector */
v_tx_rings = priv->num_tx_rings / priv->bdr_int_num;
for (i = 0; i < priv->bdr_int_num; i++) {
for (j = 0; j < v_tx_rings; j++) {
if (priv->bdr_int_num == ENETC_MAX_BDR_INT)
idx = 2 * j + i; /* 2 CPUs */
else
idx = j + i * v_tx_rings; /* default */
priv->tx_ring[idx] = bdr;
}
}
priv->bdr_int_num is set to "num_online_cpus()".
On LS1028A, it can be either 1 or 2 (and the ENETC_MAX_BDR_INT macro is
equal to 2).
Otherwise said, the convoluted logic above does the following:
- It affines an MSI interrupt vector per CPU
- It affines an RX ring per MSI vector, hence per CPU
- It balances the fixed number of TX rings (say 8) among the available
MSI vectors, hence CPUs (say 2). It does this by iterating with i
through the RX MSI interrupt vectors, and with j through the number of
TX rings per MSI vector.
This logic maps:
- the even TX rings to CPU 0 and the odd TX rings to CPU 1, if 2 CPUs
are used
- all TX rings to CPU 0, if 1 CPU is used
This is done because we have this logic in enetc_poll:
for (i = 0; i < v->count_tx_rings; i++)
if (!enetc_clean_tx_ring(&v->tx_ring[i], budget))
complete = false;
for processing the TX completions of a given group of TX rings in the RX
MSI interrupt handler of a certain CPU.
Otherwise said, priv->tx_ring[i] is always BD ring i, and that mapping
never changes. All 8 TX rings are enabled and available for use.
What I knew about tc-taprio and tc-mqprio is that they only enqueue to
TX queues [0, num_tc-1] because of this, as it turns out:
enetc_xmit:
tx_ring = priv->tx_ring[skb->queue_mapping];
where skb->queue_mapping is given by:
err = netif_set_real_num_tx_queues(ndev, priv->num_tx_rings);
and by this, respectively, from the mqprio code path:
netif_set_real_num_tx_queues(ndev, num_tc);
As for why XDP works, and priv->tx_ring[smp_processor_id()] is:
- TX ring 0 for CPU 0 and TX ring 1 for CPU 1, if 2 CPUs are used
- TX ring 0, if 1 CPU is used
The TX completions in the first case are handled by:
- CPU 0 for TX ring 0 (because it is even) and CPU 1 for TX ring 1
(because it is odd), if 2 CPUs are used, due to the mapping I talked
about earlier
- CPU 0 if only 1 CPU is used
Right - thank you for the details! So what are the constraints on the
configuration. Specifically, given two netdevs on the same device, is it
possible that the system can ever end up in a situation where one device
has two *RXQs* configured, and the other only one *TXQ*. Because then
you could get a redirect from RXQ 1 on one device, which would also end
up trying to transmit on TXQ 1 on the other device; and that would break
if that other device only has TXQ 0 configured... Same thing if a single
device has 2 RXQs but only one TXQ (it can redirect to itself).
I discover more and more of the driver as I talk to you, I like it :D
So I said that there is a maximum number of RX and TX rings splittable
between the PF and its VFs, but I wasn't exactly sure where that
configuration is done. I found it now.
enetc_port_si_configure: (SI == station interface)
- read Port capability register 0 (PCAPR0) to determine how many
RX rings and TX rings the hardware has for this port (PFs + VFs)
in total.
- assign num_rings = min(TX rings, RX rings)
- try to assign 8 TX rings and 8 RX rings to the PF
- if this fails, just assign ${num_rings} TX rings and
${num_rings} RX rings to the PF
- split the remaining RX and TX rings to the number of
configured VFs (example: if there are 16 RX rings and 16 TX
rings for a port with 2 VFs, the driver assigns 8RX/8TX rings
for the PF, and 4RX/4TX rings for each VF).
- if we couldn't assign 8RX/8TX rings for the PF in the
previous step, we don't assign any ring to the VF
So yeah, we have an equal number of RX and TX rings. The driver,
however, only uses 2 RX rings _actively_: one per CPU. The other 6, I
don't know, I guess I can use them for AF_XDP (I haven't looked very
closely at that yet), at the moment they're pretty much unused, even if
reserved and not given to VFs.
quoted
quoted
quoted
quoted
You mean that it's possible to receive a TC_SETUP_QDISC_MQPRIO or
TC_SETUP_QDISC_TAPRIO with num_tc == 1, and we have 2 CPUs?
Not just that, this ndo can be called on arbitrary CPUs after a
redirect. The code just calls through from the XDP receive path so which
CPU it ends up on depends on the RSS+IRQ config of the other device,
which may not even be the same driver; i.e., you have no control over
that... :)
What do you mean by "arbitrary" CPU? You can't plug CPUs in, it's a dual
core system... Why does the source ifindex matter at all? I'm using the
TX ring affined to the CPU that ndo_xdp_xmit is currently running on.
See, this is why I asked 'what mechanism ensures'. Because if that
mechanism is 'this driver is only ever used on a system with fewer CPUs
than TXQs', then that's of course fine :)
But there are drivers that do basically the same thing as what you've
done here, *without* having such an assurance, and just looking at that
function it's not obvious that there's an out-of-band reason why it's
safe. And I literally just came from looking at such a case when I
replied to your initial patch...
Maybe you were confused seeing that this is a PCI device, thinking it's
a plug-in card or something, therefore we don't get to choose the number
of CPUs that the host has. In hindsight, I don't know why you didn't ask
about this, it is pretty strange when you think about it.
It is actually more like a platform device with a PCI front-end - we
found this loophole in the PCI standard where you can create a "root
complex/integrated endpoint" which is basically an ECAM where the config
space contains PFs corresponding to some platform devices in the SoC (in
our case, all 4 Ethernet ports have their own PF, the switch has its own
PF, same thing for the MDIO controller and the 1588 timer). Their
register map is exposed as a number of BARs which use Enhanced
Allocation, so the generic PCI ECAM driver doesn't need to create any
translation windows for these addresses, it just uses what's in there,
which, surprise, is the actual base address of the peripheral in the
SoC's memory space.
We do that because we gain a lot of cool stuff by appearing as PCI
devices to system software, like for example multiple interfaces on top
of a 'shared MAC' are simply mapped over SR-IOV.
So it just 'smells' like PCI, but they're regular memory-mapped devices,
there is no PCI transaction layer or physical layer. At the moment the
LS1028A is the only SoC running Linux that integrates the ENETC block,
so we fully control the environment.
quoted
quoted
quoted
quoted
Well, yeah, I don't know what's the proper way to deal with that. Ideas?
Well the obvious one is just:
tx_ring = priv->tx_ring[smp_processor_id() % num_ring_ids];
and then some kind of locking to deal with multiple CPUs accessing the
same TX ring...
By multiple CPUs accessing the same TX ring, you mean locking between
ndo_xdp_xmit and ndo_start_xmit? Can that even happen if the hardware
architecture is to have at least as many TX rings as CPUs?
Because otherwise, I see that ndo_xdp_xmit is only called from
xdp_do_flush, which is in softirq context, which to my very rudimentary
knowledge run with bottom halves, thus preemption, disabled? So I don't
think it's possible for ndo_xdp_xmit and ndo_xmit, or even two
ndo_xdp_xmit instances, to access the same TX ring?
Yup, I think you're right about that. The "we always have more TXQs than
CPUs" condition was the bit I was missing (and of course you're *sure*
that this would never change sometime in the future, right? ;)).
I'm pretty sure, yeah, we build the SoCs and one of the requirements we
have is that every ENETC PF has enough TX rings in order for every CPU
to have its own one. That helps a lot with avoiding contention and
simplifying the driver. Maybe I'll use this opportunity to talk again to
the hardware design guys and make sure that the next SoCs with Linux
follow the same pattern as LS1028A, although I see no reason why not.
quoted
quoted
Sorry, I'm sure these are trivial questions, but I would like to really
understand what I need to change and why :D
Given the above I think the only potentially breaking thing is the
#RXQ > #TXQ case I outlined. And maybe a comment documenting why indexing
the tx_ring array by smp_processor_id() is safe would be nice? :)
Sure, which part exactly do you think would explain it best? Should I
add a reference to enetc_port_si_configure?
After discussing a bit more with Claudiu, I think we do have a problem,
and it has to do with concurrent ndo_xdp_xmit on one CPU and ndo_start_xmit
on another CPU.
See, even if we have 8 TX rings, they are not really affined to any CPU.
Instead, when we call netif_set_real_num_tx_queues, we allow netdev_pick_tx
to hash amongs the TX queues of the same priority. There are three consequences:
- Traffic with the same hash will be sent to the same TX queue, thus
avoiding reordering for packets belonging to the same stream.
- Traffic with different hashes are distributed to different TX queues.
- If we have two CPUs sending traffic with the same hash, they will
serialize on the TX lock of the same netdev queue.
The last one is a problem because our XDP_REDIRECT tries to associate
one TX ring with one CPU, and, as explained above, that TX ring might
already be used by our ndo_start_xmit on another CPU, selected by
netdev_pick_tx.
The first idea was to implement ndo_select_queue for the network stack,
and select the TX ring based on smp_processor_id(). But we know that
this will break the first two effects of netdev_pick_tx, which are very
much desirable. For example, if we have a user space process sending a
TCP stream, and the scheduler migrates that process from one CPU to
another, then the ndo_select_queue output for that TCP stream will
change, and we will have TX reordering for packets belonging to the same
stream. Not at all ideal.
Another idea is to just crop some TX queues from the network stack, and
basically call netif_set_real_num_tx_queues(6), leaving one TX ring per
CPU dedicated to XDP. This will work just fine for normal qdiscs, except
that with mqprio/taprio we have a problem. Our TX rings have a configurable
strict priority for the hardware egress scheduler. When we don't have
mqprio/taprio, all TX rings have the same priority of 0 (therefore it is
safe to allow hashing to select one at random), but when we have mqprio
or taprio, we enjoy the benefit of configuring the priority of each TX
ring using the "map" option. The problem, of course, is that if we crop
2 TX rings out of what the network stack sees, then we are no longer
able to configure their queue-to-traffic-class mapping through
mqprio/taprio, so we cannot change their prioritization relative to the
network stack queues. In a way, this seems to be in line with the XDP
design because that bypasses anything that has to do with qdiscs, but we
don't really like that. We also have some other qdisc-based offloads
such as Credit Based Shaper, and we would very much like to be able to
set bandwidth profiles for the XDP rings, for AVB/TSN use cases.
Finally there is the option of taking the network stack's TX lock in our
ndo_xdp_xmit, but frankly I would leave that option as a last resort.
Maybe we could make this less expensive by bulk-enqueuing into a
temporary array of buffer descriptors, and only taking the xmit lock
when flushing that array (since that is the only portion that strictly
needs to be protected against concurrency). But the problem with this
approach is that if you have a temporary array, it becomes a lot more
difficult and error-prone to not take more frames than you can enqueue.
For example, the TX ring might have only 20 free entries, and you filled
your BD array with 32 frames, and you told the caller of ndo_xdp_xmit
that you processed all those frames. Now when push comes to shove and
you actually need to enqueue them, you end up in the position that you
must drop them yourself. This seems to be very much against the design
principle of commit fdc13979f91e ("bpf, devmap: Move drop error path to
devmap for XDP_REDIRECT") whose desire is to let XDP handle the dropping
of excess TX frames.
What do you think?
What mechanism guarantees that this won't overflow the array? :)
Which array, the array of TX rings?
Yes.
The problem isn't even accessing an out-of-bounds element in the TX ring array.
As it turns out, I had a relatively superficial understanding of how
things are organized, but let me try to explain.
The number of TX rings is a configurable resource (between PFs and VFs)
and we read the capability at probe time:
enetc_get_si_caps:
val = enetc_rd(hw, ENETC_SICAPR0);
si->num_rx_rings = (val >> 16) & 0xff;
si->num_tx_rings = val & 0xff;
enetc_init_si_rings_params:
priv->num_tx_rings = si->num_tx_rings;
In any case, the TX array is declared as:
struct enetc_ndev_priv {
struct enetc_bdr *tx_ring[16];
struct enetc_bdr *rx_ring[16];
};
because that's the maximum hardware capability.
The priv->tx_ring array is populated in:
enetc_alloc_msix:
/* # of tx rings per int vector */
v_tx_rings = priv->num_tx_rings / priv->bdr_int_num;
for (i = 0; i < priv->bdr_int_num; i++) {
for (j = 0; j < v_tx_rings; j++) {
if (priv->bdr_int_num == ENETC_MAX_BDR_INT)
idx = 2 * j + i; /* 2 CPUs */
else
idx = j + i * v_tx_rings; /* default */
priv->tx_ring[idx] = bdr;
}
}
priv->bdr_int_num is set to "num_online_cpus()".
On LS1028A, it can be either 1 or 2 (and the ENETC_MAX_BDR_INT macro is
equal to 2).
Otherwise said, the convoluted logic above does the following:
- It affines an MSI interrupt vector per CPU
- It affines an RX ring per MSI vector, hence per CPU
- It balances the fixed number of TX rings (say 8) among the available
MSI vectors, hence CPUs (say 2). It does this by iterating with i
through the RX MSI interrupt vectors, and with j through the number of
TX rings per MSI vector.
This logic maps:
- the even TX rings to CPU 0 and the odd TX rings to CPU 1, if 2 CPUs
are used
- all TX rings to CPU 0, if 1 CPU is used
This is done because we have this logic in enetc_poll:
for (i = 0; i < v->count_tx_rings; i++)
if (!enetc_clean_tx_ring(&v->tx_ring[i], budget))
complete = false;
for processing the TX completions of a given group of TX rings in the RX
MSI interrupt handler of a certain CPU.
Otherwise said, priv->tx_ring[i] is always BD ring i, and that mapping
never changes. All 8 TX rings are enabled and available for use.
What I knew about tc-taprio and tc-mqprio is that they only enqueue to
TX queues [0, num_tc-1] because of this, as it turns out:
enetc_xmit:
tx_ring = priv->tx_ring[skb->queue_mapping];
where skb->queue_mapping is given by:
err = netif_set_real_num_tx_queues(ndev, priv->num_tx_rings);
and by this, respectively, from the mqprio code path:
netif_set_real_num_tx_queues(ndev, num_tc);
As for why XDP works, and priv->tx_ring[smp_processor_id()] is:
- TX ring 0 for CPU 0 and TX ring 1 for CPU 1, if 2 CPUs are used
- TX ring 0, if 1 CPU is used
The TX completions in the first case are handled by:
- CPU 0 for TX ring 0 (because it is even) and CPU 1 for TX ring 1
(because it is odd), if 2 CPUs are used, due to the mapping I talked
about earlier
- CPU 0 if only 1 CPU is used
Right - thank you for the details! So what are the constraints on the
configuration. Specifically, given two netdevs on the same device, is it
possible that the system can ever end up in a situation where one device
has two *RXQs* configured, and the other only one *TXQ*. Because then
you could get a redirect from RXQ 1 on one device, which would also end
up trying to transmit on TXQ 1 on the other device; and that would break
if that other device only has TXQ 0 configured... Same thing if a single
device has 2 RXQs but only one TXQ (it can redirect to itself).
I discover more and more of the driver as I talk to you, I like it :D
So I said that there is a maximum number of RX and TX rings splittable
between the PF and its VFs, but I wasn't exactly sure where that
configuration is done. I found it now.
enetc_port_si_configure: (SI == station interface)
- read Port capability register 0 (PCAPR0) to determine how many
RX rings and TX rings the hardware has for this port (PFs + VFs)
in total.
- assign num_rings = min(TX rings, RX rings)
- try to assign 8 TX rings and 8 RX rings to the PF
- if this fails, just assign ${num_rings} TX rings and
${num_rings} RX rings to the PF
- split the remaining RX and TX rings to the number of
configured VFs (example: if there are 16 RX rings and 16 TX
rings for a port with 2 VFs, the driver assigns 8RX/8TX rings
for the PF, and 4RX/4TX rings for each VF).
- if we couldn't assign 8RX/8TX rings for the PF in the
previous step, we don't assign any ring to the VF
So yeah, we have an equal number of RX and TX rings. The driver,
however, only uses 2 RX rings _actively_: one per CPU. The other 6, I
don't know, I guess I can use them for AF_XDP (I haven't looked very
closely at that yet), at the moment they're pretty much unused, even if
reserved and not given to VFs.
quoted
quoted
quoted
quoted
You mean that it's possible to receive a TC_SETUP_QDISC_MQPRIO or
TC_SETUP_QDISC_TAPRIO with num_tc == 1, and we have 2 CPUs?
Not just that, this ndo can be called on arbitrary CPUs after a
redirect. The code just calls through from the XDP receive path so which
CPU it ends up on depends on the RSS+IRQ config of the other device,
which may not even be the same driver; i.e., you have no control over
that... :)
What do you mean by "arbitrary" CPU? You can't plug CPUs in, it's a dual
core system... Why does the source ifindex matter at all? I'm using the
TX ring affined to the CPU that ndo_xdp_xmit is currently running on.
See, this is why I asked 'what mechanism ensures'. Because if that
mechanism is 'this driver is only ever used on a system with fewer CPUs
than TXQs', then that's of course fine :)
But there are drivers that do basically the same thing as what you've
done here, *without* having such an assurance, and just looking at that
function it's not obvious that there's an out-of-band reason why it's
safe. And I literally just came from looking at such a case when I
replied to your initial patch...
Maybe you were confused seeing that this is a PCI device, thinking it's
a plug-in card or something, therefore we don't get to choose the number
of CPUs that the host has. In hindsight, I don't know why you didn't ask
about this, it is pretty strange when you think about it.
It is actually more like a platform device with a PCI front-end - we
found this loophole in the PCI standard where you can create a "root
complex/integrated endpoint" which is basically an ECAM where the config
space contains PFs corresponding to some platform devices in the SoC (in
our case, all 4 Ethernet ports have their own PF, the switch has its own
PF, same thing for the MDIO controller and the 1588 timer). Their
register map is exposed as a number of BARs which use Enhanced
Allocation, so the generic PCI ECAM driver doesn't need to create any
translation windows for these addresses, it just uses what's in there,
which, surprise, is the actual base address of the peripheral in the
SoC's memory space.
We do that because we gain a lot of cool stuff by appearing as PCI
devices to system software, like for example multiple interfaces on top
of a 'shared MAC' are simply mapped over SR-IOV.
So it just 'smells' like PCI, but they're regular memory-mapped devices,
there is no PCI transaction layer or physical layer. At the moment the
LS1028A is the only SoC running Linux that integrates the ENETC block,
so we fully control the environment.
quoted
quoted
quoted
quoted
Well, yeah, I don't know what's the proper way to deal with that. Ideas?
Well the obvious one is just:
tx_ring = priv->tx_ring[smp_processor_id() % num_ring_ids];
and then some kind of locking to deal with multiple CPUs accessing the
same TX ring...
By multiple CPUs accessing the same TX ring, you mean locking between
ndo_xdp_xmit and ndo_start_xmit? Can that even happen if the hardware
architecture is to have at least as many TX rings as CPUs?
Because otherwise, I see that ndo_xdp_xmit is only called from
xdp_do_flush, which is in softirq context, which to my very rudimentary
knowledge run with bottom halves, thus preemption, disabled? So I don't
think it's possible for ndo_xdp_xmit and ndo_xmit, or even two
ndo_xdp_xmit instances, to access the same TX ring?
Yup, I think you're right about that. The "we always have more TXQs than
CPUs" condition was the bit I was missing (and of course you're *sure*
that this would never change sometime in the future, right? ;)).
I'm pretty sure, yeah, we build the SoCs and one of the requirements we
have is that every ENETC PF has enough TX rings in order for every CPU
to have its own one. That helps a lot with avoiding contention and
simplifying the driver. Maybe I'll use this opportunity to talk again to
the hardware design guys and make sure that the next SoCs with Linux
follow the same pattern as LS1028A, although I see no reason why not.
quoted
quoted
Sorry, I'm sure these are trivial questions, but I would like to really
understand what I need to change and why :D
Given the above I think the only potentially breaking thing is the
#RXQ > #TXQ case I outlined. And maybe a comment documenting why indexing
the tx_ring array by smp_processor_id() is safe would be nice? :)
Sure, which part exactly do you think would explain it best? Should I
add a reference to enetc_port_si_configure?
After discussing a bit more with Claudiu, I think we do have a problem,
and it has to do with concurrent ndo_xdp_xmit on one CPU and ndo_start_xmit
on another CPU.
See, even if we have 8 TX rings, they are not really affined to any CPU.
Instead, when we call netif_set_real_num_tx_queues, we allow netdev_pick_tx
to hash amongs the TX queues of the same priority. There are three consequences:
- Traffic with the same hash will be sent to the same TX queue, thus
avoiding reordering for packets belonging to the same stream.
- Traffic with different hashes are distributed to different TX queues.
- If we have two CPUs sending traffic with the same hash, they will
serialize on the TX lock of the same netdev queue.
The last one is a problem because our XDP_REDIRECT tries to associate
one TX ring with one CPU, and, as explained above, that TX ring might
already be used by our ndo_start_xmit on another CPU, selected by
netdev_pick_tx.
The first idea was to implement ndo_select_queue for the network stack,
and select the TX ring based on smp_processor_id(). But we know that
this will break the first two effects of netdev_pick_tx, which are very
much desirable. For example, if we have a user space process sending a
TCP stream, and the scheduler migrates that process from one CPU to
another, then the ndo_select_queue output for that TCP stream will
change, and we will have TX reordering for packets belonging to the same
stream. Not at all ideal.
Another idea is to just crop some TX queues from the network stack, and
basically call netif_set_real_num_tx_queues(6), leaving one TX ring per
CPU dedicated to XDP. This will work just fine for normal qdiscs, except
that with mqprio/taprio we have a problem. Our TX rings have a configurable
strict priority for the hardware egress scheduler. When we don't have
mqprio/taprio, all TX rings have the same priority of 0 (therefore it is
safe to allow hashing to select one at random), but when we have mqprio
or taprio, we enjoy the benefit of configuring the priority of each TX
ring using the "map" option. The problem, of course, is that if we crop
2 TX rings out of what the network stack sees, then we are no longer
able to configure their queue-to-traffic-class mapping through
mqprio/taprio, so we cannot change their prioritization relative to the
network stack queues. In a way, this seems to be in line with the XDP
design because that bypasses anything that has to do with qdiscs, but we
don't really like that. We also have some other qdisc-based offloads
such as Credit Based Shaper, and we would very much like to be able to
set bandwidth profiles for the XDP rings, for AVB/TSN use cases.
You'd not be the first driver to solve this by just carving out a couple
of TX rings for XDP :)
And while I get the desire for being able to configure these things for
XDP as well, I'm not sure that the qdisc interface is the right one to
use for that. There was a general TXQ allocation idea that unfortunately
stalled out, but there is also ongoing work on XDP+TSN - I'm hoping
Jesper can chime in with the details...
Finally there is the option of taking the network stack's TX lock in our
ndo_xdp_xmit, but frankly I would leave that option as a last resort.
Maybe we could make this less expensive by bulk-enqueuing into a
temporary array of buffer descriptors, and only taking the xmit lock
when flushing that array (since that is the only portion that strictly
needs to be protected against concurrency). But the problem with this
approach is that if you have a temporary array, it becomes a lot more
difficult and error-prone to not take more frames than you can enqueue.
For example, the TX ring might have only 20 free entries, and you filled
your BD array with 32 frames, and you told the caller of ndo_xdp_xmit
that you processed all those frames. Now when push comes to shove and
you actually need to enqueue them, you end up in the position that you
must drop them yourself. This seems to be very much against the design
principle of commit fdc13979f91e ("bpf, devmap: Move drop error path to
devmap for XDP_REDIRECT") whose desire is to let XDP handle the dropping
of excess TX frames.
Note that there's already bulking in XDP_REDIRECT: after an XDP program
returns XDP_REDIRECT, the packets will actually be put on a bulk queue
(see bq_enqueue() in devmap.c), and that will be flushed to the TX
driver at the end of the (RX) NAPI cycle. So taking a lock in
ndo_xdp_xmit() may not be quite as much overhead as you think it is -
so maybe it would be worth benchmarking before ruling this out entirely? :)
-Toke
What mechanism guarantees that this won't overflow the array? :)
Which array, the array of TX rings?
Yes.
The problem isn't even accessing an out-of-bounds element in the TX ring array.
As it turns out, I had a relatively superficial understanding of how
things are organized, but let me try to explain.
The number of TX rings is a configurable resource (between PFs and VFs)
and we read the capability at probe time:
enetc_get_si_caps:
val = enetc_rd(hw, ENETC_SICAPR0);
si->num_rx_rings = (val >> 16) & 0xff;
si->num_tx_rings = val & 0xff;
enetc_init_si_rings_params:
priv->num_tx_rings = si->num_tx_rings;
In any case, the TX array is declared as:
struct enetc_ndev_priv {
struct enetc_bdr *tx_ring[16];
struct enetc_bdr *rx_ring[16];
};
because that's the maximum hardware capability.
The priv->tx_ring array is populated in:
enetc_alloc_msix:
/* # of tx rings per int vector */
v_tx_rings = priv->num_tx_rings / priv->bdr_int_num;
for (i = 0; i < priv->bdr_int_num; i++) {
for (j = 0; j < v_tx_rings; j++) {
if (priv->bdr_int_num == ENETC_MAX_BDR_INT)
idx = 2 * j + i; /* 2 CPUs */
else
idx = j + i * v_tx_rings; /* default */
priv->tx_ring[idx] = bdr;
}
}
priv->bdr_int_num is set to "num_online_cpus()".
On LS1028A, it can be either 1 or 2 (and the ENETC_MAX_BDR_INT macro is
equal to 2).
Otherwise said, the convoluted logic above does the following:
- It affines an MSI interrupt vector per CPU
- It affines an RX ring per MSI vector, hence per CPU
- It balances the fixed number of TX rings (say 8) among the available
MSI vectors, hence CPUs (say 2). It does this by iterating with i
through the RX MSI interrupt vectors, and with j through the number of
TX rings per MSI vector.
This logic maps:
- the even TX rings to CPU 0 and the odd TX rings to CPU 1, if 2 CPUs
are used
- all TX rings to CPU 0, if 1 CPU is used
This is done because we have this logic in enetc_poll:
for (i = 0; i < v->count_tx_rings; i++)
if (!enetc_clean_tx_ring(&v->tx_ring[i], budget))
complete = false;
for processing the TX completions of a given group of TX rings in the RX
MSI interrupt handler of a certain CPU.
Otherwise said, priv->tx_ring[i] is always BD ring i, and that mapping
never changes. All 8 TX rings are enabled and available for use.
What I knew about tc-taprio and tc-mqprio is that they only enqueue to
TX queues [0, num_tc-1] because of this, as it turns out:
enetc_xmit:
tx_ring = priv->tx_ring[skb->queue_mapping];
where skb->queue_mapping is given by:
err = netif_set_real_num_tx_queues(ndev, priv->num_tx_rings);
and by this, respectively, from the mqprio code path:
netif_set_real_num_tx_queues(ndev, num_tc);
As for why XDP works, and priv->tx_ring[smp_processor_id()] is:
- TX ring 0 for CPU 0 and TX ring 1 for CPU 1, if 2 CPUs are used
- TX ring 0, if 1 CPU is used
The TX completions in the first case are handled by:
- CPU 0 for TX ring 0 (because it is even) and CPU 1 for TX ring 1
(because it is odd), if 2 CPUs are used, due to the mapping I talked
about earlier
- CPU 0 if only 1 CPU is used
Right - thank you for the details! So what are the constraints on the
configuration. Specifically, given two netdevs on the same device, is it
possible that the system can ever end up in a situation where one device
has two *RXQs* configured, and the other only one *TXQ*. Because then
you could get a redirect from RXQ 1 on one device, which would also end
up trying to transmit on TXQ 1 on the other device; and that would break
if that other device only has TXQ 0 configured... Same thing if a single
device has 2 RXQs but only one TXQ (it can redirect to itself).
I discover more and more of the driver as I talk to you, I like it :D
So I said that there is a maximum number of RX and TX rings splittable
between the PF and its VFs, but I wasn't exactly sure where that
configuration is done. I found it now.
enetc_port_si_configure: (SI == station interface)
- read Port capability register 0 (PCAPR0) to determine how many
RX rings and TX rings the hardware has for this port (PFs + VFs)
in total.
- assign num_rings = min(TX rings, RX rings)
- try to assign 8 TX rings and 8 RX rings to the PF
- if this fails, just assign ${num_rings} TX rings and
${num_rings} RX rings to the PF
- split the remaining RX and TX rings to the number of
configured VFs (example: if there are 16 RX rings and 16 TX
rings for a port with 2 VFs, the driver assigns 8RX/8TX rings
for the PF, and 4RX/4TX rings for each VF).
- if we couldn't assign 8RX/8TX rings for the PF in the
previous step, we don't assign any ring to the VF
So yeah, we have an equal number of RX and TX rings. The driver,
however, only uses 2 RX rings _actively_: one per CPU. The other 6, I
don't know, I guess I can use them for AF_XDP (I haven't looked very
closely at that yet), at the moment they're pretty much unused, even if
reserved and not given to VFs.
quoted
quoted
quoted
quoted
You mean that it's possible to receive a TC_SETUP_QDISC_MQPRIO or
TC_SETUP_QDISC_TAPRIO with num_tc == 1, and we have 2 CPUs?
Not just that, this ndo can be called on arbitrary CPUs after a
redirect. The code just calls through from the XDP receive path so which
CPU it ends up on depends on the RSS+IRQ config of the other device,
which may not even be the same driver; i.e., you have no control over
that... :)
What do you mean by "arbitrary" CPU? You can't plug CPUs in, it's a dual
core system... Why does the source ifindex matter at all? I'm using the
TX ring affined to the CPU that ndo_xdp_xmit is currently running on.
See, this is why I asked 'what mechanism ensures'. Because if that
mechanism is 'this driver is only ever used on a system with fewer CPUs
than TXQs', then that's of course fine :)
But there are drivers that do basically the same thing as what you've
done here, *without* having such an assurance, and just looking at that
function it's not obvious that there's an out-of-band reason why it's
safe. And I literally just came from looking at such a case when I
replied to your initial patch...
Maybe you were confused seeing that this is a PCI device, thinking it's
a plug-in card or something, therefore we don't get to choose the number
of CPUs that the host has. In hindsight, I don't know why you didn't ask
about this, it is pretty strange when you think about it.
It is actually more like a platform device with a PCI front-end - we
found this loophole in the PCI standard where you can create a "root
complex/integrated endpoint" which is basically an ECAM where the config
space contains PFs corresponding to some platform devices in the SoC (in
our case, all 4 Ethernet ports have their own PF, the switch has its own
PF, same thing for the MDIO controller and the 1588 timer). Their
register map is exposed as a number of BARs which use Enhanced
Allocation, so the generic PCI ECAM driver doesn't need to create any
translation windows for these addresses, it just uses what's in there,
which, surprise, is the actual base address of the peripheral in the
SoC's memory space.
We do that because we gain a lot of cool stuff by appearing as PCI
devices to system software, like for example multiple interfaces on top
of a 'shared MAC' are simply mapped over SR-IOV.
So it just 'smells' like PCI, but they're regular memory-mapped devices,
there is no PCI transaction layer or physical layer. At the moment the
LS1028A is the only SoC running Linux that integrates the ENETC block,
so we fully control the environment.
quoted
quoted
quoted
quoted
Well, yeah, I don't know what's the proper way to deal with that. Ideas?
Well the obvious one is just:
tx_ring = priv->tx_ring[smp_processor_id() % num_ring_ids];
and then some kind of locking to deal with multiple CPUs accessing the
same TX ring...
By multiple CPUs accessing the same TX ring, you mean locking between
ndo_xdp_xmit and ndo_start_xmit? Can that even happen if the hardware
architecture is to have at least as many TX rings as CPUs?
Because otherwise, I see that ndo_xdp_xmit is only called from
xdp_do_flush, which is in softirq context, which to my very rudimentary
knowledge run with bottom halves, thus preemption, disabled? So I don't
think it's possible for ndo_xdp_xmit and ndo_xmit, or even two
ndo_xdp_xmit instances, to access the same TX ring?
Yup, I think you're right about that. The "we always have more TXQs than
CPUs" condition was the bit I was missing (and of course you're *sure*
that this would never change sometime in the future, right? ;)).
I'm pretty sure, yeah, we build the SoCs and one of the requirements we
have is that every ENETC PF has enough TX rings in order for every CPU
to have its own one. That helps a lot with avoiding contention and
simplifying the driver. Maybe I'll use this opportunity to talk again to
the hardware design guys and make sure that the next SoCs with Linux
follow the same pattern as LS1028A, although I see no reason why not.
quoted
quoted
Sorry, I'm sure these are trivial questions, but I would like to really
understand what I need to change and why :D
Given the above I think the only potentially breaking thing is the
#RXQ > #TXQ case I outlined. And maybe a comment documenting why indexing
the tx_ring array by smp_processor_id() is safe would be nice? :)
Sure, which part exactly do you think would explain it best? Should I
add a reference to enetc_port_si_configure?
After discussing a bit more with Claudiu, I think we do have a problem,
and it has to do with concurrent ndo_xdp_xmit on one CPU and ndo_start_xmit
on another CPU.
See, even if we have 8 TX rings, they are not really affined to any CPU.
Instead, when we call netif_set_real_num_tx_queues, we allow netdev_pick_tx
to hash amongs the TX queues of the same priority. There are three consequences:
- Traffic with the same hash will be sent to the same TX queue, thus
avoiding reordering for packets belonging to the same stream.
- Traffic with different hashes are distributed to different TX queues.
- If we have two CPUs sending traffic with the same hash, they will
serialize on the TX lock of the same netdev queue.
The last one is a problem because our XDP_REDIRECT tries to associate
one TX ring with one CPU, and, as explained above, that TX ring might
already be used by our ndo_start_xmit on another CPU, selected by
netdev_pick_tx.
The first idea was to implement ndo_select_queue for the network stack,
and select the TX ring based on smp_processor_id(). But we know that
this will break the first two effects of netdev_pick_tx, which are very
much desirable. For example, if we have a user space process sending a
TCP stream, and the scheduler migrates that process from one CPU to
another, then the ndo_select_queue output for that TCP stream will
change, and we will have TX reordering for packets belonging to the same
stream. Not at all ideal.
Another idea is to just crop some TX queues from the network stack, and
basically call netif_set_real_num_tx_queues(6), leaving one TX ring per
CPU dedicated to XDP. This will work just fine for normal qdiscs, except
that with mqprio/taprio we have a problem. Our TX rings have a configurable
strict priority for the hardware egress scheduler. When we don't have
mqprio/taprio, all TX rings have the same priority of 0 (therefore it is
safe to allow hashing to select one at random), but when we have mqprio
or taprio, we enjoy the benefit of configuring the priority of each TX
ring using the "map" option. The problem, of course, is that if we crop
2 TX rings out of what the network stack sees, then we are no longer
able to configure their queue-to-traffic-class mapping through
mqprio/taprio, so we cannot change their prioritization relative to the
network stack queues. In a way, this seems to be in line with the XDP
design because that bypasses anything that has to do with qdiscs, but we
don't really like that. We also have some other qdisc-based offloads
such as Credit Based Shaper, and we would very much like to be able to
set bandwidth profiles for the XDP rings, for AVB/TSN use cases.
You'd not be the first driver to solve this by just carving out a couple
of TX rings for XDP :)
And while I get the desire for being able to configure these things for
XDP as well, I'm not sure that the qdisc interface is the right one to
use for that. There was a general TXQ allocation idea that unfortunately
stalled out, but there is also ongoing work on XDP+TSN - I'm hoping
Jesper can chime in with the details...
See, the reason why I don't like this answer is because when we tried to
upstream our genetlink-based TSN configuration:
https://patchwork.ozlabs.org/project/netdev/patch/1545968945-7290-1-git-send-email-Po.Liu@nxp.com/
we were told that it's a QoS feature and QoS belongs to the qdisc layer.
I get the impression that XDP is largely incompatible with QoS by design,
which sounds to me like a bit of a foot gun. For example, we have some
customers interested in building an AVB application stack on top of AF_XDP,
and for the endpoints (talker/listener) they really need to be able to
configure bandwidth profiles for Stream Reservation classes A and B on
the AF_XDP rings.
To us, tc is mostly just a configuration interface for hardware features,
the deal was that this is fine as long as they have a software counterpart
with identical semantics. I think I understand the basic problem in that
a software shaper would be bypassed by XDP, and therefore, the bandwidth
profile would not be observed properly by the AVB talker if we were to
rely on that. So that sounds indeed like we shouldn't even attempt to
manage any TX queues on which XDP traffic is possible with tc, unless
we're willing to pass XDP_REDIRECT through the qdisc layer (which I'm
not suggesting is a good idea). But with the hardware offload that
wouldn't be the case, so it's almost as if what would work for us would
be to have some 'dummy' TX queues for XDP manageable by tc qdiscs where
we could attach our offloadable filters and shapers and policers. I just
don't want them to be completely invisible as far as tc is concerned.
Managing which TX queues go to XDP, and not letting the driver choose
that, would be even nicer.
quoted
Finally there is the option of taking the network stack's TX lock in our
ndo_xdp_xmit, but frankly I would leave that option as a last resort.
Maybe we could make this less expensive by bulk-enqueuing into a
temporary array of buffer descriptors, and only taking the xmit lock
when flushing that array (since that is the only portion that strictly
needs to be protected against concurrency). But the problem with this
approach is that if you have a temporary array, it becomes a lot more
difficult and error-prone to not take more frames than you can enqueue.
For example, the TX ring might have only 20 free entries, and you filled
your BD array with 32 frames, and you told the caller of ndo_xdp_xmit
that you processed all those frames. Now when push comes to shove and
you actually need to enqueue them, you end up in the position that you
must drop them yourself. This seems to be very much against the design
principle of commit fdc13979f91e ("bpf, devmap: Move drop error path to
devmap for XDP_REDIRECT") whose desire is to let XDP handle the dropping
of excess TX frames.
Note that there's already bulking in XDP_REDIRECT: after an XDP program
returns XDP_REDIRECT, the packets will actually be put on a bulk queue
(see bq_enqueue() in devmap.c), and that will be flushed to the TX
driver at the end of the (RX) NAPI cycle. So taking a lock in
ndo_xdp_xmit() may not be quite as much overhead as you think it is -
so maybe it would be worth benchmarking before ruling this out entirely? :)
If shared TX queues does turn out to be the best alternative - which I'm
not convinced it is - then I'll benchmark it, sure.
What mechanism guarantees that this won't overflow the array? :)
Which array, the array of TX rings?
Yes.
The problem isn't even accessing an out-of-bounds element in the TX ring array.
As it turns out, I had a relatively superficial understanding of how
things are organized, but let me try to explain.
The number of TX rings is a configurable resource (between PFs and VFs)
and we read the capability at probe time:
enetc_get_si_caps:
val = enetc_rd(hw, ENETC_SICAPR0);
si->num_rx_rings = (val >> 16) & 0xff;
si->num_tx_rings = val & 0xff;
enetc_init_si_rings_params:
priv->num_tx_rings = si->num_tx_rings;
In any case, the TX array is declared as:
struct enetc_ndev_priv {
struct enetc_bdr *tx_ring[16];
struct enetc_bdr *rx_ring[16];
};
because that's the maximum hardware capability.
The priv->tx_ring array is populated in:
enetc_alloc_msix:
/* # of tx rings per int vector */
v_tx_rings = priv->num_tx_rings / priv->bdr_int_num;
for (i = 0; i < priv->bdr_int_num; i++) {
for (j = 0; j < v_tx_rings; j++) {
if (priv->bdr_int_num == ENETC_MAX_BDR_INT)
idx = 2 * j + i; /* 2 CPUs */
else
idx = j + i * v_tx_rings; /* default */
priv->tx_ring[idx] = bdr;
}
}
priv->bdr_int_num is set to "num_online_cpus()".
On LS1028A, it can be either 1 or 2 (and the ENETC_MAX_BDR_INT macro is
equal to 2).
Otherwise said, the convoluted logic above does the following:
- It affines an MSI interrupt vector per CPU
- It affines an RX ring per MSI vector, hence per CPU
- It balances the fixed number of TX rings (say 8) among the available
MSI vectors, hence CPUs (say 2). It does this by iterating with i
through the RX MSI interrupt vectors, and with j through the number of
TX rings per MSI vector.
This logic maps:
- the even TX rings to CPU 0 and the odd TX rings to CPU 1, if 2 CPUs
are used
- all TX rings to CPU 0, if 1 CPU is used
This is done because we have this logic in enetc_poll:
for (i = 0; i < v->count_tx_rings; i++)
if (!enetc_clean_tx_ring(&v->tx_ring[i], budget))
complete = false;
for processing the TX completions of a given group of TX rings in the RX
MSI interrupt handler of a certain CPU.
Otherwise said, priv->tx_ring[i] is always BD ring i, and that mapping
never changes. All 8 TX rings are enabled and available for use.
What I knew about tc-taprio and tc-mqprio is that they only enqueue to
TX queues [0, num_tc-1] because of this, as it turns out:
enetc_xmit:
tx_ring = priv->tx_ring[skb->queue_mapping];
where skb->queue_mapping is given by:
err = netif_set_real_num_tx_queues(ndev, priv->num_tx_rings);
and by this, respectively, from the mqprio code path:
netif_set_real_num_tx_queues(ndev, num_tc);
As for why XDP works, and priv->tx_ring[smp_processor_id()] is:
- TX ring 0 for CPU 0 and TX ring 1 for CPU 1, if 2 CPUs are used
- TX ring 0, if 1 CPU is used
The TX completions in the first case are handled by:
- CPU 0 for TX ring 0 (because it is even) and CPU 1 for TX ring 1
(because it is odd), if 2 CPUs are used, due to the mapping I talked
about earlier
- CPU 0 if only 1 CPU is used
Right - thank you for the details! So what are the constraints on the
configuration. Specifically, given two netdevs on the same device, is it
possible that the system can ever end up in a situation where one device
has two *RXQs* configured, and the other only one *TXQ*. Because then
you could get a redirect from RXQ 1 on one device, which would also end
up trying to transmit on TXQ 1 on the other device; and that would break
if that other device only has TXQ 0 configured... Same thing if a single
device has 2 RXQs but only one TXQ (it can redirect to itself).
I discover more and more of the driver as I talk to you, I like it :D
So I said that there is a maximum number of RX and TX rings splittable
between the PF and its VFs, but I wasn't exactly sure where that
configuration is done. I found it now.
enetc_port_si_configure: (SI == station interface)
- read Port capability register 0 (PCAPR0) to determine how many
RX rings and TX rings the hardware has for this port (PFs + VFs)
in total.
- assign num_rings = min(TX rings, RX rings)
- try to assign 8 TX rings and 8 RX rings to the PF
- if this fails, just assign ${num_rings} TX rings and
${num_rings} RX rings to the PF
- split the remaining RX and TX rings to the number of
configured VFs (example: if there are 16 RX rings and 16 TX
rings for a port with 2 VFs, the driver assigns 8RX/8TX rings
for the PF, and 4RX/4TX rings for each VF).
- if we couldn't assign 8RX/8TX rings for the PF in the
previous step, we don't assign any ring to the VF
So yeah, we have an equal number of RX and TX rings. The driver,
however, only uses 2 RX rings _actively_: one per CPU. The other 6, I
don't know, I guess I can use them for AF_XDP (I haven't looked very
closely at that yet), at the moment they're pretty much unused, even if
reserved and not given to VFs.
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You mean that it's possible to receive a TC_SETUP_QDISC_MQPRIO or
TC_SETUP_QDISC_TAPRIO with num_tc == 1, and we have 2 CPUs?
Not just that, this ndo can be called on arbitrary CPUs after a
redirect. The code just calls through from the XDP receive path so which
CPU it ends up on depends on the RSS+IRQ config of the other device,
which may not even be the same driver; i.e., you have no control over
that... :)
What do you mean by "arbitrary" CPU? You can't plug CPUs in, it's a dual
core system... Why does the source ifindex matter at all? I'm using the
TX ring affined to the CPU that ndo_xdp_xmit is currently running on.
See, this is why I asked 'what mechanism ensures'. Because if that
mechanism is 'this driver is only ever used on a system with fewer CPUs
than TXQs', then that's of course fine :)
But there are drivers that do basically the same thing as what you've
done here, *without* having such an assurance, and just looking at that
function it's not obvious that there's an out-of-band reason why it's
safe. And I literally just came from looking at such a case when I
replied to your initial patch...
Maybe you were confused seeing that this is a PCI device, thinking it's
a plug-in card or something, therefore we don't get to choose the number
of CPUs that the host has. In hindsight, I don't know why you didn't ask
about this, it is pretty strange when you think about it.
It is actually more like a platform device with a PCI front-end - we
found this loophole in the PCI standard where you can create a "root
complex/integrated endpoint" which is basically an ECAM where the config
space contains PFs corresponding to some platform devices in the SoC (in
our case, all 4 Ethernet ports have their own PF, the switch has its own
PF, same thing for the MDIO controller and the 1588 timer). Their
register map is exposed as a number of BARs which use Enhanced
Allocation, so the generic PCI ECAM driver doesn't need to create any
translation windows for these addresses, it just uses what's in there,
which, surprise, is the actual base address of the peripheral in the
SoC's memory space.
We do that because we gain a lot of cool stuff by appearing as PCI
devices to system software, like for example multiple interfaces on top
of a 'shared MAC' are simply mapped over SR-IOV.
So it just 'smells' like PCI, but they're regular memory-mapped devices,
there is no PCI transaction layer or physical layer. At the moment the
LS1028A is the only SoC running Linux that integrates the ENETC block,
so we fully control the environment.
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Well, yeah, I don't know what's the proper way to deal with that. Ideas?
Well the obvious one is just:
tx_ring = priv->tx_ring[smp_processor_id() % num_ring_ids];
and then some kind of locking to deal with multiple CPUs accessing the
same TX ring...
By multiple CPUs accessing the same TX ring, you mean locking between
ndo_xdp_xmit and ndo_start_xmit? Can that even happen if the hardware
architecture is to have at least as many TX rings as CPUs?
Because otherwise, I see that ndo_xdp_xmit is only called from
xdp_do_flush, which is in softirq context, which to my very rudimentary
knowledge run with bottom halves, thus preemption, disabled? So I don't
think it's possible for ndo_xdp_xmit and ndo_xmit, or even two
ndo_xdp_xmit instances, to access the same TX ring?
Yup, I think you're right about that. The "we always have more TXQs than
CPUs" condition was the bit I was missing (and of course you're *sure*
that this would never change sometime in the future, right? ;)).
I'm pretty sure, yeah, we build the SoCs and one of the requirements we
have is that every ENETC PF has enough TX rings in order for every CPU
to have its own one. That helps a lot with avoiding contention and
simplifying the driver. Maybe I'll use this opportunity to talk again to
the hardware design guys and make sure that the next SoCs with Linux
follow the same pattern as LS1028A, although I see no reason why not.
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Sorry, I'm sure these are trivial questions, but I would like to really
understand what I need to change and why :D
Given the above I think the only potentially breaking thing is the
#RXQ > #TXQ case I outlined. And maybe a comment documenting why indexing
the tx_ring array by smp_processor_id() is safe would be nice? :)
Sure, which part exactly do you think would explain it best? Should I
add a reference to enetc_port_si_configure?
After discussing a bit more with Claudiu, I think we do have a problem,
and it has to do with concurrent ndo_xdp_xmit on one CPU and ndo_start_xmit
on another CPU.
See, even if we have 8 TX rings, they are not really affined to any CPU.
Instead, when we call netif_set_real_num_tx_queues, we allow netdev_pick_tx
to hash amongs the TX queues of the same priority. There are three consequences:
- Traffic with the same hash will be sent to the same TX queue, thus
avoiding reordering for packets belonging to the same stream.
- Traffic with different hashes are distributed to different TX queues.
- If we have two CPUs sending traffic with the same hash, they will
serialize on the TX lock of the same netdev queue.
The last one is a problem because our XDP_REDIRECT tries to associate
one TX ring with one CPU, and, as explained above, that TX ring might
already be used by our ndo_start_xmit on another CPU, selected by
netdev_pick_tx.
The first idea was to implement ndo_select_queue for the network stack,
and select the TX ring based on smp_processor_id(). But we know that
this will break the first two effects of netdev_pick_tx, which are very
much desirable. For example, if we have a user space process sending a
TCP stream, and the scheduler migrates that process from one CPU to
another, then the ndo_select_queue output for that TCP stream will
change, and we will have TX reordering for packets belonging to the same
stream. Not at all ideal.
Another idea is to just crop some TX queues from the network stack, and
basically call netif_set_real_num_tx_queues(6), leaving one TX ring per
CPU dedicated to XDP. This will work just fine for normal qdiscs, except
that with mqprio/taprio we have a problem. Our TX rings have a configurable
strict priority for the hardware egress scheduler. When we don't have
mqprio/taprio, all TX rings have the same priority of 0 (therefore it is
safe to allow hashing to select one at random), but when we have mqprio
or taprio, we enjoy the benefit of configuring the priority of each TX
ring using the "map" option. The problem, of course, is that if we crop
2 TX rings out of what the network stack sees, then we are no longer
able to configure their queue-to-traffic-class mapping through
mqprio/taprio, so we cannot change their prioritization relative to the
network stack queues. In a way, this seems to be in line with the XDP
design because that bypasses anything that has to do with qdiscs, but we
don't really like that. We also have some other qdisc-based offloads
such as Credit Based Shaper, and we would very much like to be able to
set bandwidth profiles for the XDP rings, for AVB/TSN use cases.
You'd not be the first driver to solve this by just carving out a couple
of TX rings for XDP :)
And while I get the desire for being able to configure these things for
XDP as well, I'm not sure that the qdisc interface is the right one to
use for that. There was a general TXQ allocation idea that unfortunately
stalled out, but there is also ongoing work on XDP+TSN - I'm hoping
Jesper can chime in with the details...
See, the reason why I don't like this answer is because when we tried to
upstream our genetlink-based TSN configuration:
https://patchwork.ozlabs.org/project/netdev/patch/1545968945-7290-1-git-send-email-Po.Liu@nxp.com/
we were told that it's a QoS feature and QoS belongs to the qdisc layer.
I get the impression that XDP is largely incompatible with QoS by design,
which sounds to me like a bit of a foot gun. For example, we have some
customers interested in building an AVB application stack on top of AF_XDP,
and for the endpoints (talker/listener) they really need to be able to
configure bandwidth profiles for Stream Reservation classes A and B on
the AF_XDP rings.
To us, tc is mostly just a configuration interface for hardware features,
the deal was that this is fine as long as they have a software counterpart
with identical semantics. I think I understand the basic problem in that
a software shaper would be bypassed by XDP, and therefore, the bandwidth
profile would not be observed properly by the AVB talker if we were to
rely on that. So that sounds indeed like we shouldn't even attempt to
manage any TX queues on which XDP traffic is possible with tc, unless
we're willing to pass XDP_REDIRECT through the qdisc layer (which I'm
not suggesting is a good idea). But with the hardware offload that
wouldn't be the case, so it's almost as if what would work for us would
be to have some 'dummy' TX queues for XDP manageable by tc qdiscs where
we could attach our offloadable filters and shapers and policers. I just
don't want them to be completely invisible as far as tc is concerned.
Managing which TX queues go to XDP, and not letting the driver choose
that, would be even nicer.
I'm not objecting to being able to configure the hardware queues that
will be used for XDP, I'm just saying that doing so via TC is not a very
good interface for it... Rather, we need an interface for configuring
hardware queues that can be used by *both* XDP and TC.
And yeah, the lack of queueing and bandwidth management is a major
footgun in XDP, which we do want to fix (also for regular XDP_REDIRECT,
not just AF_XDP).
-Toke