From: Stefan Chulski <redacted>
Armada hardware has a pause generation mechanism in GOP (MAC).
The GOP generate flow control frames based on an indication programmed in Ports Control 0 Register. There is a bit per port.
However assertion of the PortX Pause bits in the ports control 0 register only sends a one time pause.
To complement the function the GOP has a mechanism to periodically send pause control messages based on periodic counters.
This mechanism ensures that the pause is effective as long as the Appropriate PortX Pause is asserted.
Problem is that Packet Processor that actually can drop packets due to lack of resources not connected to the GOP flow control generation mechanism.
To solve this issue Armada has firmware running on CM3 CPU dedicated for Flow Control support.
Firmware monitors Packet Processor resources and asserts XON/XOFF by writing to Ports Control 0 Register.
MSS shared SRAM memory used to communicate between CM3 firmware and PP2 driver.
During init PP2 driver informs firmware about used BM pools, RXQs, congestion and depletion thresholds.
The pause frames are generated whenever congestion or depletion in resources is detected.
The back pressure is stopped when the resource reaches a sufficient level.
So the congestion/depletion and sufficient level implement a hysteresis that reduces the XON/XOFF toggle frequency.
Packet Processor v23 hardware introduces support for RX FIFO fill level monitor.
Patch "add PPv23 version definition" to differ between v23 and v22 hardware.
Patch "add TX FC firmware check" verifies that CM3 firmware supports Flow Control monitoring.
v11 --> v12
- Improve warning message in "net: mvpp2: add TX FC firmware check" patch
v10 --> v11
- Improve "net: mvpp2: add CM3 SRAM memory map" comment
- Move condition check to 'net: mvpp2: always compare hw-version vs MVPP21' patch
v9 --> v10
- Add CM3 SRAM description to PPv2 documentation
v8 --> v9
- Replace generic pool allocation with devm_ioremap_resource
v7 --> v8
- Reorder "always compare hw-version vs MVPP21" and "add PPv23 version definition" commits
- Typo fixes
- Remove condition fix from "add RXQ flow control configurations"
v6 --> v7
- Reduce patch set from 18 to 15 patches
- Documentation change combined into a single patch
- RXQ and BM size change combined into a single patch
- Ring size change check moved into "add RXQ flow control configurations" commit
v5 --> v6
- No change
v4 --> v5
- Add missed Signed-off
- Fix warnings in patches 3 and 12
- Add revision requirement to warning message
- Move mss_spinlock into RXQ flow control configurations patch
- Improve FCA RXQ non occupied descriptor threshold commit message
v3 --> v4
- Remove RFC tag
v2 --> v3
- Remove inline functions
- Add PPv2.3 description into marvell-pp2.txt
- Improve mvpp2_interrupts_mask/unmask procedure
- Improve FC enable/disable procedure
- Add priv->sram_pool check
- Remove gen_pool_destroy call
- Reduce Flow Control timer to x100 faster
v1 --> v2
- Add memory requirements information
- Add EPROBE_DEFER if of_gen_pool_get return NULL
- Move Flow control configuration to mvpp2_mac_link_up callback
- Add firmware version info with Flow control support
Konstantin Porotchkin (1):
dts: marvell: add CM3 SRAM memory to cp11x ethernet device tree
Stefan Chulski (14):
doc: marvell: add CM3 address space and PPv2.3 description
net: mvpp2: add CM3 SRAM memory map
net: mvpp2: always compare hw-version vs MVPP21
net: mvpp2: add PPv23 version definition
net: mvpp2: increase BM pool and RXQ size
net: mvpp2: add FCA periodic timer configurations
net: mvpp2: add FCA RXQ non occupied descriptor threshold
net: mvpp2: enable global flow control
net: mvpp2: add RXQ flow control configurations
net: mvpp2: add ethtool flow control configuration support
net: mvpp2: add BM protection underrun feature support
net: mvpp2: add PPv23 RX FIFO flow control
net: mvpp2: set 802.3x GoP Flow Control mode
net: mvpp2: add TX FC firmware check
Documentation/devicetree/bindings/net/marvell-pp2.txt | 6 +-
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 +-
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 124 ++++-
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 523 ++++++++++++++++++--
4 files changed, 606 insertions(+), 49 deletions(-)
--
1.9.1
@@ -12,10 +13,11 @@ Required properties: - common controller registers - LMS registers - one register area per Ethernet port- For "marvell,armada-7k-pp2", must contain the following register+ For "marvell,armada-7k-pp2" used by 7K/8K and CN913X, must contain the following register sets: - packet processor registers - networking interfaces registers+ - CM3 address space used for TX Flow Control - clocks: pointers to the reference clocks for this device, consequently: - main controller clock (for both armada-375-pp2 and armada-7k-pp2)
From: Konstantin Porotchkin <redacted>
CM3 SRAM address space will be used for Flow Control configuration.
Signed-off-by: Stefan Chulski <redacted>
Signed-off-by: Konstantin Porotchkin <redacted>
Acked-by: Marcin Wojtas <redacted>
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
@@ -925,6 +925,7 @@ struct mvpp2 {/* Shared registers' base addresses */void__iomem*lms_base;void__iomem*iface_base;+void__iomem*cm3_base;/* On PPv2.2, each "software thread" can access the base*registerthroughaseparateaddressspace,each64KBapart
@@ -6846,6 +6846,27 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)return0;}+staticintmvpp2_get_sram(structplatform_device*pdev,+structmvpp2*priv)+{+structresource*res;++res=platform_get_resource(pdev,IORESOURCE_MEM,2);+if(!res){+if(has_acpi_companion(&pdev->dev))+dev_warn(&pdev->dev,"ACPI is too old, Flow control not supported\n");+else+dev_warn(&pdev->dev,"DT is too old, Flow control not supported\n");+return0;+}++priv->cm3_base=devm_ioremap_resource(&pdev->dev,res);+if(IS_ERR(priv->cm3_base))+returnPTR_ERR(priv->cm3_base);++return0;+}+staticintmvpp2_probe(structplatform_device*pdev){conststructacpi_device_id*acpi_id;
@@ -6902,6 +6923,11 @@ static int mvpp2_probe(struct platform_device *pdev)priv->iface_base=devm_ioremap_resource(&pdev->dev,res);if(IS_ERR(priv->iface_base))returnPTR_ERR(priv->iface_base);++/* Map CM3 SRAM */+err=mvpp2_get_sram(pdev,priv);+if(err)+dev_warn(&pdev->dev,"Fail to alloc CM3 SRAM\n");}if(priv->hw_version==MVPP22&&dev_of_node(&pdev->dev)){
From: Stefan Chulski <redacted>
Currently we have PP2v1 and PP2v2 hw-versions, with some different
handlers depending upon condition hw_version = MVPP21/MVPP22.
In a future there will be also PP2v3. Let's use now the generic
"if equal/notEqual MVPP21" for all cases instead of "if MVPP22".
This patch does not change any functionality.
It is not intended to introduce PP2v3.
It just modifies MVPP21/MVPP22 check-condition
bringing it to generic and unified form correct for new-code
introducing and PP2v3 net-next generation.
Signed-off-by: Stefan Chulski <redacted>
Acked-by: Marcin Wojtas <redacted>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 38 ++++++++++----------
1 file changed, 19 insertions(+), 19 deletions(-)
@@ -319,7 +319,7 @@ static int mvpp2_get_nrxqs(struct mvpp2 *priv){unsignedintnrxqs;-if(priv->hw_version==MVPP22&&queue_mode==MVPP2_QDIST_SINGLE_MODE)+if(priv->hw_version!=MVPP21&&queue_mode==MVPP2_QDIST_SINGLE_MODE)return1;/* According to the PPv2.2 datasheet and our experiments on
From: Stefan Chulski <redacted>
This patch add PPv23 version definition.
PPv23 is new packet processor in CP115.
Everything that supported by PPv22, also supported by PPv23.
No functional changes in this stage.
Signed-off-by: Stefan Chulski <redacted>
Acked-by: Marcin Wojtas <redacted>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 24 ++++++++++++--------
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 15 ++++++++----
2 files changed, 24 insertions(+), 15 deletions(-)
@@ -469,7 +472,7 @@#define MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1)#define MVPP22_GMAC_INT_SUM_MASK_PTP BIT(2)-/* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,+/* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,*relativetoport->base.*/#define MVPP22_XLG_CTRL0_REG 0x100
@@ -506,7 +509,7 @@#define MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12)#define MVPP22_XLG_CTRL4_EN_IDLE_CHECK BIT(14)-/* SMI registers. PPv2.2 only, relative to priv->iface_base. */+/* SMI registers. PPv2.2 and PPv2.3, relative to priv->iface_base. */#define MVPP22_SMI_MISC_CFG_REG 0x1204#define MVPP22_SMI_POLLING_EN BIT(10)
@@ -927,15 +930,16 @@ struct mvpp2 {void__iomem*iface_base;void__iomem*cm3_base;-/* On PPv2.2, each "software thread" can access the base+/* On PPv2.2 and PPv2.3, each "software thread" can access the base*registerthroughaseparateaddressspace,each64KBapart*fromeachother.Typically,suchaddressspaceswillbe*usedperCPU.*/void__iomem*swth_base[MVPP2_MAX_THREADS];-/* On PPv2.2, some port control registers are located into the system-*controllerspace.Theseregistersareaccessiblethrougharegmap.+/* On PPv2.2 and PPv2.3, some port control registers are located into+*thesystemcontrollerspace.Theseregistersareaccessible+*througharegmap.*/structregmap*sysctrl_base;
@@ -977,7 +981,7 @@ struct mvpp2 {u32tclk;/* HW version */-enum{MVPP21,MVPP22}hw_version;+enum{MVPP21,MVPP22,MVPP23}hw_version;/* Maximum number of RXQs per port */unsignedintmax_port_rxqs;
@@ -1221,7 +1225,7 @@ struct mvpp21_rx_desc {__le32reserved8;};-/* HW TX descriptor for PPv2.2 */+/* HW TX descriptor for PPv2.2 and PPv2.3 */structmvpp22_tx_desc{__le32command;u8packet_offset;
@@ -1233,7 +1237,7 @@ struct mvpp22_tx_desc {__le64buf_cookie_misc;};-/* HW RX descriptor for PPv2.2 */+/* HW RX descriptor for PPv2.2 and PPv2.3 */structmvpp22_rx_desc{__le32status;__le16reserved1;
@@ -384,7 +384,7 @@ static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv,if(!IS_ALIGNED(size,16))return-EINVAL;-/* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16+/* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 and PPv2.3 needs 16*bytesperbufferpointer*/if(priv->hw_version==MVPP21)
@@ -5456,7 +5456,7 @@ static void mvpp2_rx_irqs_setup(struct mvpp2_port *port)return;}-/* Handle the more complicated PPv2.2 case */+/* Handle the more complicated PPv2.2 and PPv2.3 case */for(i=0;i<port->nqvecs;i++){structmvpp2_queue_vector*qv=port->qvecs+i;
@@ -5633,7 +5633,7 @@ static bool mvpp22_port_has_legacy_tx_irqs(struct device_node *port_node,/* Checks if the port dt description has the required Tx interrupts:*-PPv2.1:therearenosuchinterrupts.-*-PPv2.2:+*-PPv2.2andPPv2.3:*-TheoldDTshave:"rx-shared","tx-cpuX"withXin[0...3]*-Thenewoneshave:"hifX"withXin[0..8]*
@@ -6621,7 +6621,7 @@ static void mvpp22_rx_fifo_set_hw(struct mvpp2 *priv, int port, int data_size)mvpp2_write(priv,MVPP2_RX_ATTR_FIFO_SIZE_REG(port),attr_size);}-/* Initialize TX FIFO's: the total FIFO size is 48kB on PPv2.2.+/* Initialize TX FIFO's: the total FIFO size is 48kB on PPv2.2 and PPv2.3.*4kBfixedspacemustbeassignedfortheloopbackport.*Redistributeremainingavialable44kBspaceamongallactiveports.*Guaranteeminimum32kBfor10Gportand8kBforport1,capableof2.5G
@@ -6678,7 +6678,7 @@ static void mvpp22_tx_fifo_set_hw(struct mvpp2 *priv, int port, int size)mvpp2_write(priv,MVPP22_TX_FIFO_THRESH_REG(port),threshold);}-/* Initialize TX FIFO's: the total FIFO size is 19kB on PPv2.2.+/* Initialize TX FIFO's: the total FIFO size is 19kB on PPv2.2 and PPv2.3.*3kBfixedspacemustbeassignedfortheloopbackport.*Redistributeremainingavialable16kBspaceamongallactiveports.*The10Ginterfaceshoulduse10kB(whichismaximumpossiblesize
From: Stefan Chulski <redacted>
BM pool and RXQ size increased to support Firmware Flow Control.
Minimum depletion thresholds to support FC are 1024 buffers.
BM pool size increased to 2048 to have some 1024 buffers
space between depletion thresholds and BM pool size.
Jumbo frames require a 9888B buffer, so memory requirements
for data buffers increased from 7MB to 24MB.
Signed-off-by: Stefan Chulski <redacted>
Acked-by: Marcin Wojtas <redacted>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
@@ -715,8 +715,8 @@#define MVPP2_PORT_MAX_RXQ 32/* Max number of Rx descriptors */-#define MVPP2_MAX_RXD_MAX 1024-#define MVPP2_MAX_RXD_DFLT 128+#define MVPP2_MAX_RXD_MAX 2048+#define MVPP2_MAX_RXD_DFLT 1024/* Max number of Tx descriptors */#define MVPP2_MAX_TXD_MAX 2048
From: Stefan Chulski <redacted>
Flow Control periodic timer would be used if port in
XOFF to transmit periodic XOFF frames.
Signed-off-by: Stefan Chulski <redacted>
Acked-by: Marcin Wojtas <redacted>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 13 ++++++
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 45 ++++++++++++++++++++
2 files changed, 58 insertions(+)
@@ -1280,6 +1280,49 @@ static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)writel(val,mpcs+MVPP22_MPCS_CLK_RESET);}+staticvoidmvpp22_gop_fca_enable_periodic(structmvpp2_port*port,boolen)+{+structmvpp2*priv=port->priv;+void__iomem*fca=priv->iface_base+MVPP22_FCA_BASE(port->gop_id);+u32val;++val=readl(fca+MVPP22_FCA_CONTROL_REG);+val&=~MVPP22_FCA_ENABLE_PERIODIC;+if(en)+val|=MVPP22_FCA_ENABLE_PERIODIC;+writel(val,fca+MVPP22_FCA_CONTROL_REG);+}++staticvoidmvpp22_gop_fca_set_timer(structmvpp2_port*port,u32timer)+{+structmvpp2*priv=port->priv;+void__iomem*fca=priv->iface_base+MVPP22_FCA_BASE(port->gop_id);+u32lsb,msb;++lsb=timer&MVPP22_FCA_REG_MASK;+msb=timer>>MVPP22_FCA_REG_SIZE;++writel(lsb,fca+MVPP22_PERIODIC_COUNTER_LSB_REG);+writel(msb,fca+MVPP22_PERIODIC_COUNTER_MSB_REG);+}++/* Set Flow Control timer x100 faster than pause quanta to ensure that link+*partnerwon'tsendtrafficifportisinXOFFmode.+*/+staticvoidmvpp22_gop_fca_set_periodic_timer(structmvpp2_port*port)+{+u32timer;++timer=(port->priv->tclk/(USEC_PER_SEC*FC_CLK_DIVIDER))+*FC_QUANTA;++mvpp22_gop_fca_enable_periodic(port,false);++mvpp22_gop_fca_set_timer(port,timer);++mvpp22_gop_fca_enable_periodic(port,true);+}+staticintmvpp22_gop_init(structmvpp2_port*port){structmvpp2*priv=port->priv;
@@ -1324,6 +1367,8 @@ static int mvpp22_gop_init(struct mvpp2_port *port)val|=GENCONF_SOFT_RESET1_GOP;regmap_write(priv->sysctrl_base,GENCONF_SOFT_RESET1,val);+mvpp22_gop_fca_set_periodic_timer(port);+unsupported_conf:return0;
From: Stefan Chulski <redacted>
The firmware needs to monitor the RX Non-occupied descriptor
bits for flow control to move to XOFF mode.
These bits need to be unmasked to be functional, but they will
not raise interrupts as we leave the RX exception summary
bit in MVPP2_ISR_RX_TX_MASK_REG clear.
Signed-off-by: Stefan Chulski <redacted>
Acked-by: Marcin Wojtas <redacted>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 3 ++
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 44 ++++++++++++++++----
2 files changed, 40 insertions(+), 7 deletions(-)
@@ -1133,14 +1133,19 @@ static inline void mvpp2_qvec_interrupt_disable(struct mvpp2_queue_vector *qvec)staticvoidmvpp2_interrupts_mask(void*arg){structmvpp2_port*port=arg;+intcpu=smp_processor_id();+u32thread;/* If the thread isn't used, don't do anything */-if(smp_processor_id()>port->priv->nthreads)+if(cpu>port->priv->nthreads)return;-mvpp2_thread_write(port->priv,-mvpp2_cpu_to_thread(port->priv,smp_processor_id()),+thread=mvpp2_cpu_to_thread(port->priv,cpu);++mvpp2_thread_write(port->priv,thread,MVPP2_ISR_RX_TX_MASK_REG(port->id),0);+mvpp2_thread_write(port->priv,thread,+MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),0);}/* Unmask the current thread's Rx/Tx interrupts.
@@ -1150,20 +1155,25 @@ static void mvpp2_interrupts_mask(void *arg)staticvoidmvpp2_interrupts_unmask(void*arg){structmvpp2_port*port=arg;-u32val;+intcpu=smp_processor_id();+u32val,thread;/* If the thread isn't used, don't do anything */-if(smp_processor_id()>port->priv->nthreads)+if(cpu>port->priv->nthreads)return;+thread=mvpp2_cpu_to_thread(port->priv,cpu);+val=MVPP2_CAUSE_MISC_SUM_MASK|MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(port->priv->hw_version);if(port->has_tx_irqs)val|=MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK;-mvpp2_thread_write(port->priv,-mvpp2_cpu_to_thread(port->priv,smp_processor_id()),+mvpp2_thread_write(port->priv,thread,MVPP2_ISR_RX_TX_MASK_REG(port->id),val);+mvpp2_thread_write(port->priv,thread,+MVPP2_ISR_RX_ERR_CAUSE_REG(port->id),+MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK);}staticvoid
@@ -2393,6 +2406,20 @@ static void mvpp2_txp_max_tx_size_set(struct mvpp2_port *port)}}+/* Set the number of non-occupied descriptors threshold */+staticvoidmvpp2_set_rxq_free_tresh(structmvpp2_port*port,+structmvpp2_rx_queue*rxq)+{+u32val;++mvpp2_write(port->priv,MVPP2_RXQ_NUM_REG,rxq->id);++val=mvpp2_read(port->priv,MVPP2_RXQ_THRESH_REG);+val&=~MVPP2_RXQ_NON_OCCUPIED_MASK;+val|=MSS_THRESHOLD_STOP<<MVPP2_RXQ_NON_OCCUPIED_OFFSET;+mvpp2_write(port->priv,MVPP2_RXQ_THRESH_REG,val);+}+/* Set the number of packets that will be received before Rx interrupt*willbegeneratedbyHW.*/
@@ -2648,6 +2675,9 @@ static int mvpp2_rxq_init(struct mvpp2_port *port,mvpp2_rx_pkts_coal_set(port,rxq);mvpp2_rx_time_coal_set(port,rxq);+/* Set the number of non occupied descriptors threshold */+mvpp2_set_rxq_free_tresh(port,rxq);+/* Add number of descriptors ready for receiving packets */mvpp2_rxq_status_update(port,rxq->id,0,rxq->size);
From: Stefan Chulski <redacted>
This patch enables global flow control in FW and in the phylink validate mask.
Signed-off-by: Stefan Chulski <redacted>
Acked-by: Marcin Wojtas <redacted>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 11 +++++--
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 30 +++++++++++++++++++-
2 files changed, 37 insertions(+), 4 deletions(-)
@@ -6951,7 +6966,7 @@ static int mvpp2_probe(struct platform_device *pdev)structresource*res;void__iomem*base;inti,shared;-interr;+interr,val;priv=devm_kzalloc(&pdev->dev,sizeof(*priv),GFP_KERNEL);if(!priv)
@@ -7003,6 +7018,10 @@ static int mvpp2_probe(struct platform_device *pdev)err=mvpp2_get_sram(pdev,priv);if(err)dev_warn(&pdev->dev,"Fail to alloc CM3 SRAM\n");++/* Enable global Flow Control only if handler to SRAM not NULL */+if(priv->cm3_base)+priv->global_tx_fc=true;}if(priv->hw_version!=MVPP21&&dev_of_node(&pdev->dev)){
@@ -7168,6 +7187,15 @@ static int mvpp2_probe(struct platform_device *pdev)gotoerr_port_probe;}+/* Enable global flow control. In this stage global+*flowcontrolenabled,butstilldisabledperport.+*/+if(priv->global_tx_fc&&priv->hw_version!=MVPP21){+val=mvpp2_cm3_read(priv,MSS_FC_COM_REG);+val|=FLOW_CONTROL_ENABLE_BIT;+mvpp2_cm3_write(priv,MSS_FC_COM_REG,val);+}+mvpp2_dbgfs_init(priv,pdev->name);platform_set_drvdata(pdev,priv);
@@ -1022,6 +1049,9 @@ struct mvpp2 {/* Global TX Flow Control config */boolglobal_tx_fc;++/* Spinlocks for CM3 shared memory configuration */+spinlock_tmss_spinlock;};structmvpp2_pcpu_stats{
@@ -1184,6 +1214,9 @@ struct mvpp2_port {boolrx_hwtstamp;enumhwtstamp_tx_typestx_hwtstamp_type;structmvpp2_hwtstamp_queuetx_hwtstamp_queue[2];++/* Firmware TX flow control */+booltx_fc;};/* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
@@ -741,6 +741,110 @@ static void *mvpp2_buf_alloc(struct mvpp2_port *port,returndata;}+/* Routine enable flow control for RXQs condition */+staticvoidmvpp2_rxq_enable_fc(structmvpp2_port*port)+{+intval,cm3_state,host_id,q;+intfq=port->first_rxq;+unsignedlongflags;++spin_lock_irqsave(&port->priv->mss_spinlock,flags);++/* Remove Flow control enable bit to prevent race between FW and Kernel+*IfFlowcontrolwasenabled,itwouldbere-enabled.+*/+val=mvpp2_cm3_read(port->priv,MSS_FC_COM_REG);+cm3_state=(val&FLOW_CONTROL_ENABLE_BIT);+val&=~FLOW_CONTROL_ENABLE_BIT;+mvpp2_cm3_write(port->priv,MSS_FC_COM_REG,val);++/* Set same Flow control for all RXQs */+for(q=0;q<port->nrxqs;q++){+/* Set stop and start Flow control RXQ thresholds */+val=MSS_THRESHOLD_START;+val|=(MSS_THRESHOLD_STOP<<MSS_RXQ_TRESH_STOP_OFFS);+mvpp2_cm3_write(port->priv,MSS_RXQ_TRESH_REG(q,fq),val);++val=mvpp2_cm3_read(port->priv,MSS_RXQ_ASS_REG(q,fq));+/* Set RXQ port ID */+val&=~(MSS_RXQ_ASS_PORTID_MASK<<MSS_RXQ_ASS_Q_BASE(q,fq));+val|=(port->id<<MSS_RXQ_ASS_Q_BASE(q,fq));+val&=~(MSS_RXQ_ASS_HOSTID_MASK<<(MSS_RXQ_ASS_Q_BASE(q,fq)++MSS_RXQ_ASS_HOSTID_OFFS));++/* Calculate RXQ host ID:+*InSinglequeuemode:HostIDequaltoHostIDusedfor+*sharedRXinterrupt+*InMultiqueuemode:HostIDequaltonumberof+*RXQID/numberofCoSqueues+*InSingleresourcemode:HostIDalwaysequalto0+*/+if(queue_mode==MVPP2_QDIST_SINGLE_MODE)+host_id=port->nqvecs;+elseif(queue_mode==MVPP2_QDIST_MULTI_MODE)+host_id=q;+else+host_id=0;++/* Set RXQ host ID */+val|=(host_id<<(MSS_RXQ_ASS_Q_BASE(q,fq)++MSS_RXQ_ASS_HOSTID_OFFS));++mvpp2_cm3_write(port->priv,MSS_RXQ_ASS_REG(q,fq),val);+}++/* Notify Firmware that Flow control config space ready for update */+val=mvpp2_cm3_read(port->priv,MSS_FC_COM_REG);+val|=FLOW_CONTROL_UPDATE_COMMAND_BIT;+val|=cm3_state;+mvpp2_cm3_write(port->priv,MSS_FC_COM_REG,val);++spin_unlock_irqrestore(&port->priv->mss_spinlock,flags);+}++/* Routine disable flow control for RXQs condition */+staticvoidmvpp2_rxq_disable_fc(structmvpp2_port*port)+{+intval,cm3_state,q;+unsignedlongflags;+intfq=port->first_rxq;++spin_lock_irqsave(&port->priv->mss_spinlock,flags);++/* Remove Flow control enable bit to prevent race between FW and Kernel+*IfFlowcontrolwasenabled,itwouldbere-enabled.+*/+val=mvpp2_cm3_read(port->priv,MSS_FC_COM_REG);+cm3_state=(val&FLOW_CONTROL_ENABLE_BIT);+val&=~FLOW_CONTROL_ENABLE_BIT;+mvpp2_cm3_write(port->priv,MSS_FC_COM_REG,val);++/* Disable Flow control for all RXQs */+for(q=0;q<port->nrxqs;q++){+/* Set threshold 0 to disable Flow control */+val=0;+val|=(0<<MSS_RXQ_TRESH_STOP_OFFS);+mvpp2_cm3_write(port->priv,MSS_RXQ_TRESH_REG(q,fq),val);++val=mvpp2_cm3_read(port->priv,MSS_RXQ_ASS_REG(q,fq));++val&=~(MSS_RXQ_ASS_PORTID_MASK<<MSS_RXQ_ASS_Q_BASE(q,fq));++val&=~(MSS_RXQ_ASS_HOSTID_MASK<<(MSS_RXQ_ASS_Q_BASE(q,fq)++MSS_RXQ_ASS_HOSTID_OFFS));++mvpp2_cm3_write(port->priv,MSS_RXQ_ASS_REG(q,fq),val);+}++/* Notify Firmware that Flow control config space ready for update */+val=mvpp2_cm3_read(port->priv,MSS_FC_COM_REG);+val|=FLOW_CONTROL_UPDATE_COMMAND_BIT;+val|=cm3_state;+mvpp2_cm3_write(port->priv,MSS_FC_COM_REG,val);++spin_unlock_irqrestore(&port->priv->mss_spinlock,flags);+}+/* Release buffer to BM */staticinlinevoidmvpp2_bm_pool_put(structmvpp2_port*port,intpool,dma_addr_tbuf_dma_addr,
@@ -3005,6 +3109,9 @@ static void mvpp2_cleanup_rxqs(struct mvpp2_port *port)for(queue=0;queue<port->nrxqs;queue++)mvpp2_rxq_deinit(port,port->rxqs[queue]);++if(port->tx_fc)+mvpp2_rxq_disable_fc(port);}/* Init all Rx queues for port */
@@ -3017,6 +3124,10 @@ static int mvpp2_setup_rxqs(struct mvpp2_port *port)if(err)gotoerr_cleanup;}++if(port->tx_fc)+mvpp2_rxq_enable_fc(port);+return0;err_cleanup:
@@ -4316,6 +4427,8 @@ static int mvpp2_check_ringparam_valid(struct net_device *dev,if(ring->rx_pending>MVPP2_MAX_RXD_MAX)new_rx_pending=MVPP2_MAX_RXD_MAX;+elseif(ring->rx_pending<MSS_THRESHOLD_START)+new_rx_pending=MSS_THRESHOLD_START;elseif(!IS_ALIGNED(ring->rx_pending,16))new_rx_pending=ALIGN(ring->rx_pending,16);
From: Stefan Chulski <redacted>
This patch add ethtool flow control configuration support.
Tx flow control retrieved correctly by ethtool get function.
FW per port ethtool configuration capability added.
Patch also takes care about mtu change procedure, if PPv2 switch
BM pools during mtu change.
Signed-off-by: Stefan Chulski <redacted>
Acked-by: Marcin Wojtas <redacted>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 13 +++
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 98 ++++++++++++++++++++
2 files changed, 111 insertions(+)
@@ -845,6 +845,59 @@ static void mvpp2_rxq_disable_fc(struct mvpp2_port *port)spin_unlock_irqrestore(&port->priv->mss_spinlock,flags);}+/* Routine disable/enable flow control for BM pool condition */+staticvoidmvpp2_bm_pool_update_fc(structmvpp2_port*port,+structmvpp2_bm_pool*pool,+boolen)+{+intval,cm3_state;+unsignedlongflags;++spin_lock_irqsave(&port->priv->mss_spinlock,flags);++/* Remove Flow control enable bit to prevent race between FW and Kernel+*IfFlowcontrolwereenabled,itwouldbere-enabled.+*/+val=mvpp2_cm3_read(port->priv,MSS_FC_COM_REG);+cm3_state=(val&FLOW_CONTROL_ENABLE_BIT);+val&=~FLOW_CONTROL_ENABLE_BIT;+mvpp2_cm3_write(port->priv,MSS_FC_COM_REG,val);++/* Check if BM pool should be enabled/disable */+if(en){+/* Set BM pool start and stop thresholds per port */+val=mvpp2_cm3_read(port->priv,MSS_BUF_POOL_REG(pool->id));+val|=MSS_BUF_POOL_PORT_OFFS(port->id);+val&=~MSS_BUF_POOL_START_MASK;+val|=(MSS_THRESHOLD_START<<MSS_BUF_POOL_START_OFFS);+val&=~MSS_BUF_POOL_STOP_MASK;+val|=MSS_THRESHOLD_STOP;+mvpp2_cm3_write(port->priv,MSS_BUF_POOL_REG(pool->id),val);+}else{+/* Remove BM pool from the port */+val=mvpp2_cm3_read(port->priv,MSS_BUF_POOL_REG(pool->id));+val&=~MSS_BUF_POOL_PORT_OFFS(port->id);++/* Zero BM pool start and stop thresholds to disable pool+*flowcontrolifpoolempty(notusedbyanyport)+*/+if(!pool->buf_num){+val&=~MSS_BUF_POOL_START_MASK;+val&=~MSS_BUF_POOL_STOP_MASK;+}++mvpp2_cm3_write(port->priv,MSS_BUF_POOL_REG(pool->id),val);+}++/* Notify Firmware that Flow control config space ready for update */+val=mvpp2_cm3_read(port->priv,MSS_FC_COM_REG);+val|=FLOW_CONTROL_UPDATE_COMMAND_BIT;+val|=cm3_state;+mvpp2_cm3_write(port->priv,MSS_FC_COM_REG,val);++spin_unlock_irqrestore(&port->priv->mss_spinlock,flags);+}+/* Release buffer to BM */staticinlinevoidmvpp2_bm_pool_put(structmvpp2_port*port,intpool,dma_addr_tbuf_dma_addr,
@@ -1175,6 +1228,16 @@ static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)new_long_pool=MVPP2_BM_LONG;if(new_long_pool!=port->pool_long->id){+if(port->tx_fc){+if(pkt_size>MVPP2_BM_LONG_PKT_SIZE)+mvpp2_bm_pool_update_fc(port,+port->pool_short,+false);+else+mvpp2_bm_pool_update_fc(port,port->pool_long,+false);+}+/* Remove port from old short & long pool */port->pool_long=mvpp2_bm_pool_use(port,port->pool_long->id,port->pool_long->pkt_size);
@@ -1192,6 +1255,25 @@ static int mvpp2_bm_update_mtu(struct net_device *dev, int mtu)mvpp2_swf_bm_pool_init(port);mvpp2_set_hw_csum(port,new_long_pool);++if(port->tx_fc){+if(pkt_size>MVPP2_BM_LONG_PKT_SIZE)+mvpp2_bm_pool_update_fc(port,port->pool_long,+true);+else+mvpp2_bm_pool_update_fc(port,port->pool_short,+true);+}++/* Update L4 checksum when jumbo enable/disable on port */+if(new_long_pool==MVPP2_BM_JUMBO&&port->id!=0){+dev->features&=~(NETIF_F_IP_CSUM|NETIF_F_IPV6_CSUM);+dev->hw_features&=~(NETIF_F_IP_CSUM|+NETIF_F_IPV6_CSUM);+}else{+dev->features|=NETIF_F_IP_CSUM|NETIF_F_IPV6_CSUM;+dev->hw_features|=NETIF_F_IP_CSUM|NETIF_F_IPV6_CSUM;+}}out_set:
From: Stefan Chulski <redacted>
New FIFO flow control feature was added in PPv23.
PPv2 FIFO polled by HW and trigger pause frame if FIFO
fill level is below threshold.
FIFO HW flow control enabled with CM3 RXQ&BM flow
control with ethtool.
Current FIFO thresholds is:
9KB for port with maximum speed 10Gb/s port
4KB for port with maximum speed 5Gb/s port
2KB for port with maximum speed 1Gb/s port
Signed-off-by: Stefan Chulski <redacted>
Acked-by: Marcin Wojtas <redacted>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 15 ++++++
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 53 ++++++++++++++++++++
2 files changed, 68 insertions(+)
From: Stefan Chulski <redacted>
The PP2v23 hardware supports a feature allowing to double the
size of BPPI by decreasing number of pools from 16 to 8.
Increasing of BPPI size protect BM drop from BPPI underrun.
Underrun could occurred due to stress on DDR and as result slow buffer
transition from BPPE to BPPI.
New BPPI threshold recommended by spec is:
BPPI low threshold - 640 buffers
BPPI high threshold - 832 buffers
Supported only in PPv23.
Signed-off-by: Stefan Chulski <redacted>
Acked-by: Marcin Wojtas <redacted>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 8 +++++
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 35 +++++++++++++++++++-
2 files changed, 42 insertions(+), 1 deletion(-)
From: Stefan Chulski <redacted>
Patch check that TX FC firmware is running in CM3.
If not, global TX FC would be disabled.
Signed-off-by: Stefan Chulski <redacted>
Acked-by: Marcin Wojtas <redacted>
---
drivers/net/ethernet/marvell/mvpp2/mvpp2.h | 1 +
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 39 ++++++++++++++++----
2 files changed, 33 insertions(+), 7 deletions(-)
@@ -931,6 +931,34 @@ static void mvpp2_bm_pool_update_fc(struct mvpp2_port *port,spin_unlock_irqrestore(&port->priv->mss_spinlock,flags);}+staticintmvpp2_enable_global_fc(structmvpp2*priv)+{+intval,timeout=0;++/* Enable global flow control. In this stage global+*flowcontrolenabled,butstilldisabledperport.+*/+val=mvpp2_cm3_read(priv,MSS_FC_COM_REG);+val|=FLOW_CONTROL_ENABLE_BIT;+mvpp2_cm3_write(priv,MSS_FC_COM_REG,val);++/* Check if Firmware running and disable FC if not*/+val|=FLOW_CONTROL_UPDATE_COMMAND_BIT;+mvpp2_cm3_write(priv,MSS_FC_COM_REG,val);++while(timeout<MSS_FC_MAX_TIMEOUT){+val=mvpp2_cm3_read(priv,MSS_FC_COM_REG);++if(!(val&FLOW_CONTROL_UPDATE_COMMAND_BIT))+return0;+usleep_range(10,20);+timeout++;+}++priv->global_tx_fc=false;+return-EOPNOTSUPP;+}+/* Release buffer to BM */staticinlinevoidmvpp2_bm_pool_put(structmvpp2_port*port,intpool,dma_addr_tbuf_dma_addr,
@@ -7263,7 +7291,7 @@ static int mvpp2_probe(struct platform_device *pdev)structresource*res;void__iomem*base;inti,shared;-interr,val;+interr;priv=devm_kzalloc(&pdev->dev,sizeof(*priv),GFP_KERNEL);if(!priv)
@@ -7487,13 +7515,10 @@ static int mvpp2_probe(struct platform_device *pdev)gotoerr_port_probe;}-/* Enable global flow control. In this stage global-*flowcontrolenabled,butstilldisabledperport.-*/if(priv->global_tx_fc&&priv->hw_version!=MVPP21){-val=mvpp2_cm3_read(priv,MSS_FC_COM_REG);-val|=FLOW_CONTROL_ENABLE_BIT;-mvpp2_cm3_write(priv,MSS_FC_COM_REG,val);+err=mvpp2_enable_global_fc(priv);+if(err)+dev_warn(&pdev->dev,"Minimum of CM3 firmware 18.09 and chip revision B0 required for flow control\n");}mvpp2_dbgfs_init(priv,pdev->name);
Ok, I would remove new module parameters.
By the way why new module parameters forbitten?
Historically, module parameters are a bad interface for
configuration. Vendors have stuffed all sorts of random junk into
module parameters. There is little documentation. Different drivers
can have similar looking module parameters which do different
things. Or different module parameters, which actually do the same
thing. But maybe with slightly different parameters.
We get a much better overall result if you stop and think for a
while. How can this be made a generic configuration knob which
multiple vendors could use? And then add it to ethtool. Extend the
ethtool -h text and the man page. Maybe even hack some other vendors
driver to make use of it.
Or we have also found out, that pushing back on parameters like this,
the developers goes back and looks at the code, and sometimes figures
out a way to automatically do the right thing, removing the
configuration knob, and just making it all simpler for the user to
use.
Andrew
Ok, I would remove new module parameters.
By the way why new module parameters forbitten?
Historically, module parameters are a bad interface for
configuration. Vendors have stuffed all sorts of random junk into
module parameters. There is little documentation. Different drivers
can have similar looking module parameters which do different
things. Or different module parameters, which actually do the same
thing. But maybe with slightly different parameters.
We get a much better overall result if you stop and think for a
while. How can this be made a generic configuration knob which
multiple vendors could use? And then add it to ethtool. Extend the
ethtool -h text and the man page. Maybe even hack some other vendors
driver to make use of it.
Or we have also found out, that pushing back on parameters like this,
the developers goes back and looks at the code, and sometimes figures
out a way to automatically do the right thing, removing the
configuration knob, and just making it all simpler for the user to
use.
I think of 2 alternatives:
* `ethtool --set-priv-flags` - in such case there is a question if
switching this particular feature in runtime is a good idea.
* New DT/ACPI property - it is a hardware feature after all, so maybe
let the user decide whether to enable it on the platform description
level.
What do you think?
Best regards,
Marcin
From: Andrew Lunn <andrew@lunn.ch> Date: 2021-02-12 13:53:59
quoted
Or we have also found out, that pushing back on parameters like this,
the developers goes back and looks at the code, and sometimes figures
out a way to automatically do the right thing, removing the
configuration knob, and just making it all simpler for the user to
use.
I think of 2 alternatives:
* `ethtool --set-priv-flags` - in such case there is a question if
switching this particular feature in runtime is a good idea.
* New DT/ACPI property - it is a hardware feature after all, so maybe
let the user decide whether to enable it on the platform description
level.
Does this even need to be configurable? What is the cost of turning it
on? How does having less pools affect the system? Does average latency
go up? When would i consider an underrun actually a good thing?
Maybe it should just be hard coded on? Or we should try to detect when
underruns are happening a lot, and dynamically turn it on for a while?
Andrew
From: Stefan Chulski <hidden> Date: 2021-02-14 09:23:39
quoted
quoted
Or we have also found out, that pushing back on parameters like
this, the developers goes back and looks at the code, and sometimes
figures out a way to automatically do the right thing, removing the
configuration knob, and just making it all simpler for the user to
use.
I think of 2 alternatives:
* `ethtool --set-priv-flags` - in such case there is a question if
switching this particular feature in runtime is a good idea.
* New DT/ACPI property - it is a hardware feature after all, so maybe
let the user decide whether to enable it on the platform description
level.
Does this even need to be configurable? What is the cost of turning it on?
How does having less pools affect the system? Does average latency go up?
When would i consider an underrun actually a good thing?
Maybe it should just be hard coded on? Or we should try to detect when
underruns are happening a lot, and dynamically turn it on for a while?
Andrew
The cost of this change is that the number of pools reduced from 16 to 8.
The current driver uses only 4pools, but some future features like QoS can use over 4 pools.
Regards,
Stefan.
From: Andrew Lunn <andrew@lunn.ch> Date: 2021-02-15 00:39:46
quoted
Does this even need to be configurable? What is the cost of turning it on?
How does having less pools affect the system? Does average latency go up?
When would i consider an underrun actually a good thing?
Maybe it should just be hard coded on? Or we should try to detect when
underruns are happening a lot, and dynamically turn it on for a while?
The cost of this change is that the number of pools reduced from 16 to 8.
The current driver uses only 4pools, but some future features like QoS can use over 4 pools.
So you are saying, there is currently no cost for turning it on. So it
seems like you should just turn it on, and forget the module
parameter. When QoS features are added which require more than 8 pools
you can then address the issue of if this should be configurable.
Andrew