[PATCH 00/16] net: stmmac: Add DW MAC GPIOs and Baikal-T1 GMAC support

@@ -0,0 +1,150 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/baikal,bt1-gmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Baikal-T1 DW GMAC Network Interface
+
+maintainers:
+  - Serge Semin <fancer.lancer@gmail.com>
+
+description:
+  Baikal-T1 is equipped with two DW GMAC v3.73a network interfaces. Each of
+  them doesn't have any on-SoC PHY attached, but instead exports RGMII
+  interface to connect any compatible physical layer transceiver.
+
+select:
+  properties:
+    compatible:
+      contains:
+        const: baikal,bt1-gmac
+
+  required:
+    - compatible
+
+allOf:
+  - $ref: "snps,dwmac.yaml#"
+
+properties:
+  compatible:
+    items:
+      - const: baikal,bt1-gmac
+      - const: snps,dwmac-3.73a
+      - const: snps,dwmac
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  interrupt-names:
+    const: macirq
+
+  clocks:
+    minItems: 4
+    maxItems: 4
+
+  clock-names:
+    minItems: 4
+    maxItems: 4
+    contains:
+      enum:
+        - stmmaceth
+        - pclk
+        - tx
+        - ptp_ref
+
+  ngpios:
+    description:
+      Baikal-T1 GMAC have been created with one GPI and one GPO ports
+      enabled. So there are total two GPIOs available.
+    const: 2
+
+  gpio-controller: true
+
+  "#gpio-cells":
+    const: 2
+
+  tx-internal-delay-ps:
+    description:
+      DW MAC Tx clocks generator has been designed to always add 2ns delay
+      of TXC with respect to TXD.
+    const: 2000
+
+  rx-fifo-depth:
+    const: 16384
+
+  tx-fifo-depth:
+    const: 16384
+
+  axi-config:
+    type: object
+
+    properties:
+      snps,wr_osr_lmt:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: Maximum write outstanding requests is limited with 4
+        maximum: 3
+
+      snps,rd_osr_lmt:
+        $ref: /schemas/types.yaml#/definitions/uint32
+        description: Maximum read outstanding requests is limited with 4
+        maximum: 3
+
+      snps,blen:
+        $ref: /schemas/types.yaml#/definitions/uint32-array
+        description: AXI-bus burst length width is limited with just 4 bits
+        items:
+          enum: [16, 8, 4, 0]
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - interrupt-names
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - phy-mode
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    ethernet@1f05e000 {
+      compatible = "baikal,bt1-dwmac", "snps,dwmac-3.73a", "snps,dwmac";
+      reg = <0x1f05e000 0x2000>;
+      #address-cells = <1>;
+      #size-cells = <2>;
+
+      interrupts = <72>;
+      interrupt-names = "macirq";
+
+      clocks = <&ccu_sys 1>, <&ccu_axi 3>, <&ccu_sys 2>, <&ccu_sys 3>;
+      clock-names = "pclk", "stmmaceth", "tx", "ptp_ref";
+
+      resets = <&ccu_axi 3>;
+      reset-names = "stmmaceth";
+
+      ngpios = <2>;
+
+      gpio-controller;
+      #gpio-cells = <2>;
+
+      phy-mode = "rgmii-rxid";
+      tx-internal-delay-ps = <2000>;
+
+      rx-fifo-depth = <16384>;
+      tx-fifo-depth = <16384>;
+
+      axi-config {
+        snps,wr_osr_lmt = <0x3>;
+        snps,rd_osr_lmt = <0x3>;
+        snps,blen = <0 0 0 0 16 8 4>;
+      };
+    };
+...

@@ -110,6 +110,23 @@ properties:
   reset-names:
     const: stmmaceth
 
+  ngpios:
+    description:
+      Total number of GPIOs the MAC supports. The property shall include both
+      the GPI and GPO ports width.
+    minimum: 1
+    maximum: 32
+
+  gpio-controller: true
+
+  "#gpio-cells":
+    const: 2
+
+  interrupt-controller: true
+
+  "#interrupt-cells":
+    const: 2
+
   mac-mode:
     $ref: ethernet-controller.yaml#/properties/phy-connection-type
     description:

@@ -820,6 +820,23 @@ static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 	}
 }
 
+static void dwmac4_enable_mtl_irq(void __iomem *ioaddr, u32 chan,
+				  bool rx, bool tx)
+{
+	u32 value = 0;
+
+	/* Enable just MTL RX overflow IRQ for now */
+	if (rx)
+		value |= MTL_RX_OVERFLOW_INT_EN;
+
+	writel(value, ioaddr + MTL_CHAN_INT_CTRL(chan));
+}
+
+static void dwmac4_disable_mtl_irq(void __iomem *ioaddr, u32 chan)
+{
+	writel(0, ioaddr + MTL_CHAN_INT_CTRL(chan));
+}
+
 static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
 {
 	void __iomem *ioaddr = hw->pcsr;

@@ -1190,6 +1207,8 @@ const struct stmmac_ops dwmac4_ops = {
 	.enable_mac_irq = dwmac4_enable_mac_irq,
 	.disable_mac_irq = dwmac4_disable_mac_irq,
 	.host_irq_status = dwmac4_irq_status,
+	.enable_mtl_irq = dwmac4_enable_mtl_irq,
+	.disable_mtl_irq = dwmac4_disable_mtl_irq,
 	.host_mtl_irq_status = dwmac4_irq_mtl_status,
 	.flow_ctrl = dwmac4_flow_ctrl,
 	.pmt = dwmac4_pmt,

@@ -1234,6 +1253,8 @@ const struct stmmac_ops dwmac410_ops = {
 	.enable_mac_irq = dwmac4_enable_mac_irq,
 	.disable_mac_irq = dwmac4_disable_mac_irq,
 	.host_irq_status = dwmac4_irq_status,
+	.enable_mtl_irq = dwmac4_enable_mtl_irq,
+	.disable_mtl_irq = dwmac4_disable_mtl_irq,
 	.host_mtl_irq_status = dwmac4_irq_mtl_status,
 	.flow_ctrl = dwmac4_flow_ctrl,
 	.pmt = dwmac4_pmt,

@@ -1281,6 +1302,8 @@ const struct stmmac_ops dwmac510_ops = {
 	.enable_mac_irq = dwmac4_enable_mac_irq,
 	.disable_mac_irq = dwmac4_disable_mac_irq,
 	.host_irq_status = dwmac4_irq_status,
+	.enable_mtl_irq = dwmac4_enable_mtl_irq,
+	.disable_mtl_irq = dwmac4_disable_mtl_irq,
 	.host_mtl_irq_status = dwmac4_irq_mtl_status,
 	.flow_ctrl = dwmac4_flow_ctrl,
 	.pmt = dwmac4_pmt,

@@ -201,7 +201,7 @@ static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode,
 				       u32 channel, int fifosz, u8 qmode)
 {
 	unsigned int rqs = fifosz / 256 - 1;
-	u32 mtl_rx_op, mtl_rx_int;
+	u32 mtl_rx_op;
 
 	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));
 

@@ -262,11 +262,6 @@ static void dwmac4_dma_rx_chan_op_mode(void __iomem *ioaddr, int mode,
 	}
 
 	writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));
-
-	/* Enable MTL RX overflow */
-	mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));
-	writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN,
-	       ioaddr + MTL_CHAN_INT_CTRL(channel));
 }
 
 static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode,

@@ -285,6 +285,23 @@ static int dwxgmac2_host_irq_status(struct mac_device_info *hw,
 	return ret;
 }
 
+static void dwxgmac2_enable_mtl_irq(void __iomem *ioaddr, u32 chan,
+				    bool rx, bool tx)
+{
+	u32 value = 0;
+
+	/* Enable just MTL RX overflow IRQ for now */
+	if (rx)
+		value |= XGMAC_RXOIE;
+
+	writel(value, ioaddr + XGMAC_MTL_QINTEN(chan));
+}
+
+static void dwxgmac2_disable_mtl_irq(void __iomem *ioaddr, u32 chan)
+{
+	writel(0, ioaddr + XGMAC_MTL_QINTEN(chan));
+}
+
 static int dwxgmac2_host_mtl_irq_status(struct mac_device_info *hw, u32 chan)
 {
 	void __iomem *ioaddr = hw->pcsr;

@@ -1476,6 +1493,8 @@ const struct stmmac_ops dwxgmac210_ops = {
 	.enable_mac_irq = dwxgmac2_enable_mac_irq,
 	.disable_mac_irq = dwxgmac2_disable_mac_irq,
 	.host_irq_status = dwxgmac2_host_irq_status,
+	.enable_mtl_irq = dwxgmac2_enable_mtl_irq,
+	.disable_mtl_irq = dwxgmac2_disable_mtl_irq,
 	.host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,
 	.flow_ctrl = dwxgmac2_flow_ctrl,
 	.pmt = dwxgmac2_pmt,

@@ -1539,6 +1558,8 @@ const struct stmmac_ops dwxlgmac2_ops = {
 	.enable_mac_irq = dwxgmac2_enable_mac_irq,
 	.disable_mac_irq = dwxgmac2_disable_mac_irq,
 	.host_irq_status = dwxgmac2_host_irq_status,
+	.enable_mtl_irq = dwxgmac2_enable_mtl_irq,
+	.disable_mtl_irq = dwxgmac2_disable_mtl_irq,
 	.host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,
 	.flow_ctrl = dwxgmac2_flow_ctrl,
 	.pmt = dwxgmac2_pmt,

@@ -198,10 +198,6 @@ static void dwxgmac2_dma_rx_mode(void __iomem *ioaddr, int mode,
 	}
 
 	writel(value, ioaddr + XGMAC_MTL_RXQ_OPMODE(channel));
-
-	/* Enable MTL RX overflow */
-	value = readl(ioaddr + XGMAC_MTL_QINTEN(channel));
-	writel(value | XGMAC_RXOIE, ioaddr + XGMAC_MTL_QINTEN(channel));
 }
 
 static void dwxgmac2_dma_tx_mode(void __iomem *ioaddr, int mode,

@@ -332,6 +332,10 @@ struct stmmac_ops {
 	/* Handle extra events on specific interrupts hw dependent */
 	int (*host_irq_status)(struct mac_device_info *hw,
 			       struct stmmac_extra_stats *x);
+	/* Enable/Disable MTL interrupts */
+	void (*enable_mtl_irq)(void __iomem *ioaddr, u32 chan,
+			       bool rx, bool tx);
+	void (*disable_mtl_irq)(void __iomem *ioaddr, u32 chan);
 	/* Handle MTL interrupts */
 	int (*host_mtl_irq_status)(struct mac_device_info *hw, u32 chan);
 	/* Multicast filter setting */

@@ -442,6 +446,10 @@ struct stmmac_ops {
 	stmmac_do_void_callback(__priv, mac, disable_mac_irq, __args)
 #define stmmac_host_irq_status(__priv, __args...) \
 	stmmac_do_callback(__priv, mac, host_irq_status, __args)
+#define stmmac_enable_mtl_irq(__priv, __args...) \
+	stmmac_do_void_callback(__priv, mac, enable_mtl_irq, __args)
+#define stmmac_disable_mtl_irq(__priv, __args...) \
+	stmmac_do_void_callback(__priv, mac, disable_mtl_irq, __args)
 #define stmmac_host_mtl_irq_status(__priv, __args...) \
 	stmmac_do_callback(__priv, mac, host_mtl_irq_status, __args)
 #define stmmac_set_filter(__priv, __args...) \

@@ -4129,6 +4129,7 @@ static int stmmac_set_features(struct net_device *netdev,
 static void stmmac_enable_irq(struct stmmac_priv *priv)
 {
 	u32 chan, maxq;
+	bool rx, tx;
 
 	/* The main IRQ signal needs to be masked while the IRQs enable/disable
 	 * procedure is in progress, because the individual IRQs handlers can

@@ -4138,9 +4139,15 @@ static void stmmac_enable_irq(struct stmmac_priv *priv)
 
 	maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use);
 
-	for (chan = 0; chan < maxq; ++chan)
+	for (chan = 0; chan < maxq; ++chan) {
 		stmmac_enable_dma_irq(priv, priv->ioaddr, chan);
 
+		rx = (chan < priv->plat->rx_queues_to_use);
+		tx = (chan < priv->plat->tx_queues_to_use);
+
+		stmmac_enable_mtl_irq(priv, priv->ioaddr, chan, rx, tx);
+	}
+
 	stmmac_enable_mac_irq(priv, priv->hw);
 
 	enable_irq(priv->dev->irq);

@@ -4163,8 +4170,11 @@ static void stmmac_disable_irq(struct stmmac_priv *priv)
 
 	stmmac_disable_mac_irq(priv, priv->hw);
 
-	for (chan = 0; chan < maxq; ++chan)
+	for (chan = 0; chan < maxq; ++chan) {
+		stmmac_disable_mtl_irq(priv, priv->ioaddr, chan);
+
 		stmmac_disable_dma_irq(priv, priv->ioaddr, chan);
+	}
 
 	enable_irq(priv->dev->irq);
 }

@@ -246,6 +246,7 @@ static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt,
 
 const struct stmmac_dma_ops dwmac1000_dma_ops = {
 	.reset = dwmac_dma_reset,
+	.clean = dwmac_dma_clean,
 	.init = dwmac1000_dma_init,
 	.init_rx_chan = dwmac_dma_init_rx,
 	.init_tx_chan = dwmac_dma_init_tx,

@@ -145,5 +145,6 @@ void dwmac_dma_stop_rx(void __iomem *ioaddr, u32 chan);
 int dwmac_dma_interrupt(void __iomem *ioaddr, struct stmmac_extra_stats *x,
 			u32 chan);
 int dwmac_dma_reset(void __iomem *ioaddr);
+void dwmac_dma_clean(void __iomem *ioaddr);
 
 #endif /* __DWMAC_DMA_H__ */

@@ -26,6 +26,18 @@ int dwmac_dma_reset(void __iomem *ioaddr)
 				 10000, 200000);
 }
 
+void dwmac_dma_clean(void __iomem *ioaddr)
+{
+	/* Clean the basic DMA registers up */
+	writel(0, ioaddr + DMA_INTR_ENA);
+	writel(0x00020100, ioaddr + DMA_BUS_MODE);
+	writel(0, ioaddr + DMA_RCV_BASE_ADDR);
+	writel(0, ioaddr + DMA_TX_BASE_ADDR);
+	writel(0x00100000, ioaddr + DMA_CONTROL);
+	writel(0x00110001, ioaddr + DMA_AXI_BUS_MODE);
+	writel(0x0001FFFF, ioaddr + DMA_STATUS);
+}
+
 /* CSR1 enables the transmit DMA to check for new descriptor */
 void dwmac_enable_dma_transmission(void __iomem *ioaddr)
 {

@@ -169,6 +169,7 @@ struct dma_features;
 struct stmmac_dma_ops {
 	/* DMA core initialization */
 	int (*reset)(void __iomem *ioaddr);
+	void (*clean)(void __iomem *ioaddr);
 	void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,
 		     int atds);
 	void (*init_chan)(void __iomem *ioaddr,

@@ -219,6 +220,8 @@ struct stmmac_dma_ops {
 
 #define stmmac_reset(__priv, __args...) \
 	stmmac_do_callback(__priv, dma, reset, __args)
+#define stmmac_dma_clean(__priv, __args...) \
+	stmmac_do_void_callback(__priv, dma, clean, __args)
 #define stmmac_dma_init(__priv, __args...) \
 	stmmac_do_void_callback(__priv, dma, init, __args)
 #define stmmac_init_chan(__priv, __args...) \

@@ -263,6 +263,7 @@ int stmmac_dvr_remove(struct device *dev);
 int stmmac_dvr_probe(struct device *device,
 		     struct plat_stmmacenet_data *plat_dat,
 		     struct stmmac_resources *res);
+bool stmmac_is_up(struct stmmac_priv *priv);
 void stmmac_disable_eee_mode(struct stmmac_priv *priv);
 bool stmmac_eee_init(struct stmmac_priv *priv);
 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt);

@@ -402,7 +402,9 @@ static void stmmac_ethtool_setmsglevel(struct net_device *dev, u32 level)
 
 static int stmmac_check_if_running(struct net_device *dev)
 {
-	if (!netif_running(dev))
+	struct stmmac_priv *priv = netdev_priv(dev);
+
+	if (!stmmac_is_up(priv))
 		return -EBUSY;
 	return 0;
 }

@@ -2804,6 +2804,20 @@ static void stmmac_hw_teardown(struct net_device *dev)
 	stmmac_mac_set(priv, priv->ioaddr, false);
 }
 
+/**
+ * stmmac_is_up - test STMMAC state
+ *  @priv: driver private structure
+ *  Description:
+ *  Detects the current network adapter state just by testing the MAC
+ *  initialization completion flag.
+ *  Return value:
+ *  true if the STMMAC network is setup, false otherwise.
+ */
+bool stmmac_is_up(struct stmmac_priv *priv)
+{
+	return test_bit(STMMAC_UP, &priv->state);
+}
+
 /**
  *  stmmac_open - open entry point of the driver
  *  @dev : pointer to the device structure.

@@ -4046,7 +4060,7 @@ static int stmmac_change_mtu(struct net_device *dev, int new_mtu)
 
 	txfifosz /= priv->plat->tx_queues_to_use;
 
-	if (netif_running(dev)) {
+	if (stmmac_is_up(priv)) {
 		netdev_err(priv->dev, "must be stopped to change its MTU\n");
 		return -EBUSY;
 	}

@@ -4217,7 +4231,7 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
 		pm_wakeup_event(priv->device, 0);
 
 	/* Check if adapter is up */
-	if (!test_bit(STMMAC_UP, &priv->state))
+	if (!stmmac_is_up(priv))
 		return IRQ_HANDLED;
 	/* Check if a fatal error happened */
 	if (stmmac_safety_feat_interrupt(priv))

@@ -4290,7 +4304,7 @@ static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 	struct stmmac_priv *priv = netdev_priv (dev);
 	int ret = -EOPNOTSUPP;
 
-	if (!netif_running(dev))
+	if (!stmmac_is_up(priv))
 		return -EINVAL;
 
 	switch (cmd) {

@@ -4743,7 +4757,7 @@ static const struct net_device_ops stmmac_netdev_ops = {
 
 static void stmmac_reset_subtask(struct stmmac_priv *priv)
 {
-	if (!test_bit(STMMAC_UP, &priv->state))
+	if (!stmmac_is_up(priv))
 		return;
 
 	netdev_err(priv->dev, "Reset adapter.\n");

@@ -4915,7 +4929,7 @@ int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt)
 	struct stmmac_priv *priv = netdev_priv(dev);
 	int ret = 0;
 
-	if (netif_running(dev))
+	if (stmmac_is_up(priv))
 		stmmac_release(dev);
 
 	stmmac_napi_del(dev);

@@ -4925,7 +4939,7 @@ int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt)
 
 	stmmac_napi_add(dev);
 
-	if (netif_running(dev))
+	if (stmmac_is_up(priv))
 		ret = stmmac_open(dev);
 
 	return ret;

@@ -4936,13 +4950,13 @@ int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size)
 	struct stmmac_priv *priv = netdev_priv(dev);
 	int ret = 0;
 
-	if (netif_running(dev))
+	if (stmmac_is_up(priv))
 		stmmac_release(dev);
 
 	priv->dma_rx_size = rx_size;
 	priv->dma_tx_size = tx_size;
 
-	if (netif_running(dev))
+	if (stmmac_is_up(priv))
 		ret = stmmac_open(dev);
 
 	return ret;

@@ -5253,7 +5267,7 @@ int stmmac_suspend(struct device *dev)
 	struct stmmac_priv *priv = netdev_priv(ndev);
 	u32 chan;
 
-	if (!ndev || !netif_running(ndev))
+	if (!stmmac_is_up(priv))
 		return 0;
 
 	phylink_mac_change(priv->phylink, false);

@@ -5343,7 +5357,7 @@ int stmmac_resume(struct device *dev)
 	struct stmmac_priv *priv = netdev_priv(ndev);
 	int ret;
 
-	if (!netif_running(ndev))
+	if (!stmmac_is_up(priv))
 		return 0;
 
 	/* Power Down bit, into the PM register, is cleared

@@ -2274,8 +2274,6 @@ static void stmmac_mmc_setup(struct stmmac_priv *priv)
 	unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET |
 			    MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET;
 
-	stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
-
 	if (priv->dma_cap.rmon) {
 		stmmac_mmc_ctrl(priv, priv->mmcaddr, mode);
 		memset(&priv->mmc, 0, sizeof(struct stmmac_counters));

@@ -4182,6 +4180,8 @@ static void stmmac_disable_irq(struct stmmac_priv *priv)
 	if (priv->dma_cap.asp)
 		stmmac_disable_safety_feat_irq(priv, priv->ioaddr);
 
+	stmmac_mmc_intr_all_mask(priv, priv->mmcaddr);
+
 	enable_irq(priv->dev->irq);
 }
 

@@ -2810,9 +2810,6 @@ static int stmmac_hw_setup(struct net_device *dev, bool init_ptp)
 	netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use);
 	netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use);
 
-	/* Enable MAC/MTL/DMA/etc IRQs */
-	stmmac_enable_irq(priv);
-
 	/* Start the ball rolling... */
 	stmmac_start_all_dma(priv);
 

@@ -2825,8 +2822,6 @@ static void stmmac_hw_teardown(struct net_device *dev)
 
 	stmmac_stop_all_dma(priv);
 
-	stmmac_disable_irq(priv);
-
 	stmmac_release_ptp(priv);
 
 	stmmac_mac_set(priv, priv->ioaddr, false);

@@ -2929,57 +2924,13 @@ static int stmmac_open(struct net_device *dev)
 	/* We may have called phylink_speed_down before */
 	phylink_speed_up(priv->phylink);
 
-	/* Request the IRQ lines */
-	ret = request_irq(dev->irq, stmmac_interrupt,
-			  IRQF_SHARED, dev->name, dev);
-	if (unlikely(ret < 0)) {
-		netdev_err(priv->dev,
-			   "%s: ERROR: allocating the IRQ %d (error: %d)\n",
-			   __func__, dev->irq, ret);
-		goto irq_error;
-	}
-
-	/* Request the Wake IRQ in case of another line is used for WoL */
-	if (priv->wol_irq != dev->irq) {
-		ret = request_irq(priv->wol_irq, stmmac_interrupt,
-				  IRQF_SHARED, dev->name, dev);
-		if (unlikely(ret < 0)) {
-			netdev_err(priv->dev,
-				   "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
-				   __func__, priv->wol_irq, ret);
-			goto wolirq_error;
-		}
-	}
-
-	/* Request the IRQ lines */
-	if (priv->lpi_irq > 0) {
-		ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
-				  dev->name, dev);
-		if (unlikely(ret < 0)) {
-			netdev_err(priv->dev,
-				   "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
-				   __func__, priv->lpi_irq, ret);
-			goto lpiirq_error;
-		}
-	}
+	stmmac_enable_irq(priv);
 
 	stmmac_enable_all_queues(priv);
 	netif_tx_start_all_queues(priv->dev);
 
 	return 0;
 
-lpiirq_error:
-	if (priv->wol_irq != dev->irq)
-		free_irq(priv->wol_irq, dev);
-wolirq_error:
-	free_irq(dev->irq, dev);
-irq_error:
-	phylink_stop(priv->phylink);
-
-	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
-		hrtimer_cancel(&priv->tx_queue[chan].txtimer);
-
-	stmmac_hw_teardown(dev);
 init_error:
 	free_dma_desc_resources(priv);
 dma_desc_error:

@@ -3009,12 +2960,8 @@ static int stmmac_release(struct net_device *dev)
 	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
 		hrtimer_cancel(&priv->tx_queue[chan].txtimer);
 
-	/* Free the IRQ lines */
-	free_irq(dev->irq, dev);
-	if (priv->wol_irq != dev->irq)
-		free_irq(priv->wol_irq, dev);
-	if (priv->lpi_irq > 0)
-		free_irq(priv->lpi_irq, dev);
+	/* Disable the network IRQs */
+	stmmac_disable_irq(priv);
 
 	if (priv->eee_enabled) {
 		priv->tx_path_in_lpi_mode = false;

@@ -4252,19 +4199,21 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
 	u32 queue;
 	bool xmac;
 
-	xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
-	queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
+	/* Check if adapter is up */
+	if (!stmmac_is_up(priv))
+		return IRQ_HANDLED;
 
+	/* Wake up the system if PMT is available and has been enabled */
 	if (priv->irq_wake)
 		pm_wakeup_event(priv->device, 0);
 
-	/* Check if adapter is up */
-	if (!stmmac_is_up(priv))
-		return IRQ_HANDLED;
 	/* Check if a fatal error happened */
 	if (stmmac_safety_feat_interrupt(priv))
 		return IRQ_HANDLED;
 
+	xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac;
+	queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt;
+
 	/* To handle GMAC own interrupts */
 	if ((priv->plat->has_gmac) || xmac) {
 		int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats);

@@ -4306,6 +4255,76 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
 	return IRQ_HANDLED;
 }
 
+/**
+ * stmmac_request_irq - request DW MAC IRQs
+ * @priv: driver private structure
+ * Description : setup the ISR for all available interrupt signals.
+ *  Return value:
+ *  0 on success and an appropriate (-)ve integer as defined in errno.h
+ *  file on failure.
+ */
+static int stmmac_request_irq(struct stmmac_priv *priv)
+{
+	struct net_device *dev = priv->dev;
+	int ret;
+
+	ret = request_irq(dev->irq, stmmac_interrupt,
+			  IRQF_SHARED, dev->name, dev);
+	if (unlikely(ret < 0)) {
+		netdev_err(priv->dev,
+			   "%s: ERROR: allocating the IRQ %d (error: %d)\n",
+			   __func__, dev->irq, ret);
+		return ret;
+	}
+
+	if (priv->wol_irq != dev->irq) {
+		ret = request_irq(priv->wol_irq, stmmac_interrupt,
+				  IRQF_SHARED, dev->name, dev);
+		if (unlikely(ret < 0)) {
+			netdev_err(priv->dev,
+				   "%s: ERROR: allocating the WoL IRQ %d (%d)\n",
+				   __func__, priv->wol_irq, ret);
+			goto wolirq_error;
+		}
+	}
+
+	if (priv->lpi_irq > 0) {
+		ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED,
+				  dev->name, dev);
+		if (unlikely(ret < 0)) {
+			netdev_err(priv->dev,
+				   "%s: ERROR: allocating the LPI IRQ %d (%d)\n",
+				   __func__, priv->lpi_irq, ret);
+			goto lpiirq_error;
+		}
+	}
+
+	return 0;
+
+lpiirq_error:
+	if (priv->wol_irq != dev->irq)
+		free_irq(priv->wol_irq, dev);
+
+wolirq_error:
+	free_irq(dev->irq, dev);
+
+	return ret;
+}
+
+/**
+ * stmmac_request_irq - free DW MAC IRQs
+ * @priv: driver private structure
+ * Description : free the main/WoL/LPI IRQs.
+ */
+static void stmmac_free_irq(struct stmmac_priv *priv)
+{
+	free_irq(priv->dev->irq, priv->dev);
+	if (priv->wol_irq != priv->dev->irq)
+		free_irq(priv->wol_irq, priv->dev);
+	if (priv->lpi_irq > 0)
+		free_irq(priv->lpi_irq, priv->dev);
+}
+
 #ifdef CONFIG_NET_POLL_CONTROLLER
 /* Polling receive - used by NETCONSOLE and other diagnostic tools
  * to allow network I/O with interrupts disabled.

@@ -4906,6 +4925,13 @@ static int stmmac_hw_init(struct stmmac_priv *priv)
 			 "Enable RX Mitigation via HW Watchdog Timer\n");
 	}
 
+	/* Disable all the device IRQs on HW initialization stage in case if
+	 * the NIC has been used by another software before the kernel and
+	 * the reset control capability isn't provided so further IRQs setup
+	 * wouldn't end up with handling spurious interrupts.
+	 */
+	stmmac_disable_irq(priv);
+
 	return 0;
 }
 

@@ -5190,6 +5216,10 @@ int stmmac_dvr_probe(struct device *device,
 
 	stmmac_check_pcs_mode(priv);
 
+	ret = stmmac_request_irq(priv);
+	if (ret)
+		goto error_request_irq;
+
 	if (priv->hw->pcs != STMMAC_PCS_TBI &&
 	    priv->hw->pcs != STMMAC_PCS_RTBI) {
 		/* MDIO bus Registration */

@@ -5238,6 +5268,8 @@ int stmmac_dvr_probe(struct device *device,
 	    priv->hw->pcs != STMMAC_PCS_RTBI)
 		stmmac_mdio_unregister(ndev);
 error_mdio_register:
+	stmmac_free_irq(priv);
+error_request_irq:
 	stmmac_napi_del(ndev);
 error_hw_init:
 	destroy_workqueue(priv->wq);

@@ -5274,6 +5306,7 @@ int stmmac_dvr_remove(struct device *dev)
 	if (priv->hw->pcs != STMMAC_PCS_TBI &&
 	    priv->hw->pcs != STMMAC_PCS_RTBI)
 		stmmac_mdio_unregister(ndev);
+	stmmac_free_irq(priv);
 	reset_control_assert(priv->plat->stmmac_rst);
 	destroy_workqueue(priv->wq);
 	mutex_destroy(&priv->lock);

@@ -5440,6 +5473,8 @@ int stmmac_resume(struct device *dev)
 
 	stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw);
 
+	stmmac_enable_irq(priv);
+
 	stmmac_enable_all_queues(priv);
 
 	mutex_unlock(&priv->lock);

@@ -21,6 +21,38 @@
 #include "stmmac_pcs.h"
 #include "dwmac1000.h"
 
+static void dwmac1000_core_clean(void __iomem *ioaddr)
+{
+	int idx;
+
+	/* Clean the basic MAC registers up. Note the MAC interrupts are
+	 * enabled by default after reset. Let's mask them out so not to have
+	 * any spurious MAC-related IRQ generated during the cleanup
+	 * procedure.
+	 */
+	writel(0x7FF, ioaddr + GMAC_INT_MASK);
+	writel(0, ioaddr + GMAC_CONTROL);
+	writel(0, ioaddr + GMAC_FRAME_FILTER);
+	writel(0, ioaddr + GMAC_HASH_HIGH);
+	writel(0, ioaddr + GMAC_HASH_LOW);
+	writel(0, ioaddr + GMAC_FLOW_CTRL);
+	writel(0, ioaddr + GMAC_VLAN_TAG);
+	writel(0, ioaddr + GMAC_DEBUG);
+	writel(0x80000000, ioaddr + GMAC_PMT);
+	writel(0, ioaddr + LPI_CTRL_STATUS);
+	writel(0x03e80000, ioaddr + LPI_TIMER_CTRL);
+	for (idx = 0; idx < 15; ++idx) {
+		writel(0x0000ffff, ioaddr + GMAC_ADDR_HIGH(idx));
+		writel(0xffffffff, ioaddr + GMAC_ADDR_LOW(idx));
+	}
+	writel(0, ioaddr + GMAC_PCS_BASE);
+	writel(0, ioaddr + GMAC_RGSMIIIS);
+	writel(0x1, ioaddr + GMAC_MMC_CTRL);
+	readl(ioaddr + GMAC_INT_STATUS);
+	readl(ioaddr + GMAC_PMT);
+	readl(ioaddr + LPI_CTRL_STATUS);
+}
+
 static void dwmac1000_core_init(struct mac_device_info *hw,
 				struct net_device *dev)
 {

@@ -511,6 +543,7 @@ static void dwmac1000_set_mac_loopback(void __iomem *ioaddr, bool enable)
 }
 
 const struct stmmac_ops dwmac1000_ops = {
+	.core_clean = dwmac1000_core_clean,
 	.core_init = dwmac1000_core_init,
 	.set_mac = stmmac_set_mac,
 	.rx_ipc = dwmac1000_rx_ipc_enable,

@@ -287,6 +287,8 @@ struct stmmac_est;
 
 /* Helpers to program the MAC core */
 struct stmmac_ops {
+	/* MAC core cleanup */
+	void (*core_clean)(void __iomem *ioaddr);
 	/* MAC core initialization */
 	void (*core_init)(struct mac_device_info *hw, struct net_device *dev);
 	/* Enable the MAC RX/TX */

@@ -396,6 +398,8 @@ struct stmmac_ops {
 			      bool enable);
 };
 
+#define stmmac_core_clean(__priv, __args...) \
+	stmmac_do_void_callback(__priv, mac, core_clean, __args)
 #define stmmac_core_init(__priv, __args...) \
 	stmmac_do_void_callback(__priv, mac, core_init, __args)
 #define stmmac_mac_set(__priv, __args...) \

@@ -95,14 +95,6 @@ static void dwmac1000_core_init(struct mac_device_info *hw,
 
 	writel(value, ioaddr + GMAC_CONTROL);
 
-	/* Mask GMAC interrupts */
-	value = GMAC_INT_DEFAULT_MASK;
-
-	if (hw->pcs)
-		value &= ~GMAC_INT_DISABLE_PCS;
-
-	writel(value, ioaddr + GMAC_INT_MASK);
-
 #ifdef STMMAC_VLAN_TAG_USED
 	/* Tag detection without filtering */
 	writel(0x0, ioaddr + GMAC_VLAN_TAG);

@@ -302,6 +294,24 @@ static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
 	writel(pmt, ioaddr + GMAC_PMT);
 }
 
+static void dwmac1000_enable_mac_irq(struct mac_device_info *hw)
+{
+	void __iomem *ioaddr = hw->pcsr;
+	u32 value = GMAC_INT_DEFAULT_MASK;
+
+	if (hw->pcs)
+		value &= ~GMAC_INT_DISABLE_PCS;
+
+	writel(value, ioaddr + GMAC_INT_MASK);
+}
+
+static void dwmac1000_disable_mac_irq(struct mac_device_info *hw)
+{
+	void __iomem *ioaddr = hw->pcsr;
+
+	writel(0x7FF, ioaddr + GMAC_INT_MASK);
+}
+
 /* RGMII or SMII interface */
 static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 {

@@ -548,6 +558,8 @@ const struct stmmac_ops dwmac1000_ops = {
 	.set_mac = stmmac_set_mac,
 	.rx_ipc = dwmac1000_rx_ipc_enable,
 	.dump_regs = dwmac1000_dump_regs,
+	.enable_mac_irq = dwmac1000_enable_mac_irq,
+	.disable_mac_irq = dwmac1000_disable_mac_irq,
 	.host_irq_status = dwmac1000_irq_status,
 	.set_filter = dwmac1000_set_filter,
 	.flow_ctrl = dwmac1000_flow_ctrl,

@@ -46,14 +46,6 @@ static void dwmac4_core_init(struct mac_device_info *hw,
 	}
 
 	writel(value, ioaddr + GMAC_CONFIG);
-
-	/* Enable GMAC interrupts */
-	value = GMAC_INT_DEFAULT_ENABLE;
-
-	if (hw->pcs)
-		value |= GMAC_PCS_IRQ_DEFAULT;
-
-	writel(value, ioaddr + GMAC_INT_EN);
 }
 
 static void dwmac4_rx_queue_enable(struct mac_device_info *hw,

@@ -777,6 +769,24 @@ static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
 	dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
 }
 
+static void dwmac4_enable_mac_irq(struct mac_device_info *hw)
+{
+	void __iomem *ioaddr = hw->pcsr;
+	u32 value = GMAC_INT_DEFAULT_ENABLE;
+
+	if (hw->pcs)
+		value |= GMAC_PCS_IRQ_DEFAULT;
+
+	writel(value, ioaddr + GMAC_INT_EN);
+}
+
+static void dwmac4_disable_mac_irq(struct mac_device_info *hw)
+{
+	void __iomem *ioaddr = hw->pcsr;
+
+	writel(0, ioaddr + GMAC_INT_EN);
+}
+
 /* RGMII or SMII interface */
 static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
 {

@@ -1177,6 +1187,8 @@ const struct stmmac_ops dwmac4_ops = {
 	.map_mtl_to_dma = dwmac4_map_mtl_dma,
 	.config_cbs = dwmac4_config_cbs,
 	.dump_regs = dwmac4_dump_regs,
+	.enable_mac_irq = dwmac4_enable_mac_irq,
+	.disable_mac_irq = dwmac4_disable_mac_irq,
 	.host_irq_status = dwmac4_irq_status,
 	.host_mtl_irq_status = dwmac4_irq_mtl_status,
 	.flow_ctrl = dwmac4_flow_ctrl,

@@ -1219,6 +1231,8 @@ const struct stmmac_ops dwmac410_ops = {
 	.map_mtl_to_dma = dwmac4_map_mtl_dma,
 	.config_cbs = dwmac4_config_cbs,
 	.dump_regs = dwmac4_dump_regs,
+	.enable_mac_irq = dwmac4_enable_mac_irq,
+	.disable_mac_irq = dwmac4_disable_mac_irq,
 	.host_irq_status = dwmac4_irq_status,
 	.host_mtl_irq_status = dwmac4_irq_mtl_status,
 	.flow_ctrl = dwmac4_flow_ctrl,

@@ -1264,6 +1278,8 @@ const struct stmmac_ops dwmac510_ops = {
 	.map_mtl_to_dma = dwmac4_map_mtl_dma,
 	.config_cbs = dwmac4_config_cbs,
 	.dump_regs = dwmac4_dump_regs,
+	.enable_mac_irq = dwmac4_enable_mac_irq,
+	.disable_mac_irq = dwmac4_disable_mac_irq,
 	.host_irq_status = dwmac4_irq_status,
 	.host_mtl_irq_status = dwmac4_irq_mtl_status,
 	.flow_ctrl = dwmac4_flow_ctrl,

@@ -44,7 +44,6 @@ static void dwxgmac2_core_init(struct mac_device_info *hw,
 
 	writel(tx, ioaddr + XGMAC_TX_CONFIG);
 	writel(rx, ioaddr + XGMAC_RX_CONFIG);
-	writel(XGMAC_INT_DEFAULT_EN, ioaddr + XGMAC_INT_EN);
 }
 
 static void dwxgmac2_set_mac(void __iomem *ioaddr, bool enable)

@@ -239,6 +238,16 @@ static void dwxgmac2_dump_regs(struct mac_device_info *hw, u32 *reg_space)
 		reg_space[i] = readl(ioaddr + i * 4);
 }
 
+static void dwxgmac2_enable_mac_irq(struct mac_device_info *hw)
+{
+	writel(XGMAC_INT_DEFAULT_EN, hw->pcsr + XGMAC_INT_EN);
+}
+
+static void dwxgmac2_disable_mac_irq(struct mac_device_info *hw)
+{
+	writel(0, hw->pcsr + XGMAC_INT_EN);
+}
+
 static int dwxgmac2_host_irq_status(struct mac_device_info *hw,
 				    struct stmmac_extra_stats *x)
 {

@@ -1464,6 +1473,8 @@ const struct stmmac_ops dwxgmac210_ops = {
 	.map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,
 	.config_cbs = dwxgmac2_config_cbs,
 	.dump_regs = dwxgmac2_dump_regs,
+	.enable_mac_irq = dwxgmac2_enable_mac_irq,
+	.disable_mac_irq = dwxgmac2_disable_mac_irq,
 	.host_irq_status = dwxgmac2_host_irq_status,
 	.host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,
 	.flow_ctrl = dwxgmac2_flow_ctrl,

@@ -1525,6 +1536,8 @@ const struct stmmac_ops dwxlgmac2_ops = {
 	.map_mtl_to_dma = dwxgmac2_map_mtl_to_dma,
 	.config_cbs = dwxgmac2_config_cbs,
 	.dump_regs = dwxgmac2_dump_regs,
+	.enable_mac_irq = dwxgmac2_enable_mac_irq,
+	.disable_mac_irq = dwxgmac2_disable_mac_irq,
 	.host_irq_status = dwxgmac2_host_irq_status,
 	.host_mtl_irq_status = dwxgmac2_host_mtl_irq_status,
 	.flow_ctrl = dwxgmac2_flow_ctrl,