[PATCH] net: axienet: add of_phy_connect call for XAE_PHY_TYPE_MII case

This IP core has support for mii connectivity to the phy, so be ready to
connect to it when this is the case.

Signed-off-by: Alvaro Gamez Machado <redacted>
---
 drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 33c595f4691d..9b3f55449b5e 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c

@@ -935,7 +935,11 @@ static int axienet_open(struct net_device *ndev)
 		return ret;
 
 	if (lp->phy_node) {
-		if (lp->phy_type == XAE_PHY_TYPE_GMII) {
+		if (lp->phy_type == XAE_PHY_TYPE_MII) {
+			phydev = of_phy_connect(lp->ndev, lp->phy_node,
+						axienet_adjust_link, 0,
+						PHY_INTERFACE_MODE_MII);
+		} else if (lp->phy_type == XAE_PHY_TYPE_GMII) {
 			phydev = of_phy_connect(lp->ndev, lp->phy_node,
 						axienet_adjust_link, 0,
 						PHY_INTERFACE_MODE_GMII);

-- 
2.11.0

On 06/30/2017 02:25 AM, Alvaro Gamez Machado wrote:

Seems like this could be simplified even further if the values of
lp->phy_type directly mapped to those of phy_interface_t.
-- 
Florian

On Fri, Jun 30, 2017 at 10:30:38AM -0700, Florian Fainelli wrote:

On 06/30/2017 02:25 AM, Alvaro Gamez Machado wrote:

quoted

 	if (lp->phy_node) {
-		if (lp->phy_type == XAE_PHY_TYPE_GMII) {
+		if (lp->phy_type == XAE_PHY_TYPE_MII) {
+			phydev = of_phy_connect(lp->ndev, lp->phy_node,
+						axienet_adjust_link, 0,
+						PHY_INTERFACE_MODE_MII);
+		} else if (lp->phy_type == XAE_PHY_TYPE_GMII) {
 			phydev = of_phy_connect(lp->ndev, lp->phy_node,
 						axienet_adjust_link, 0,
 						PHY_INTERFACE_MODE_GMII);

Seems like this could be simplified even further if the values of
lp->phy_type directly mapped to those of phy_interface_t.

Sadly, that's not the case. PHY_INTERFACE_MODE_* belong to a enum of twenty
different values, of which only _MII and _GMII overlap with XAW_PHY_*
values, but XAE_PHY_TYPE_RGMII_2_0 doesn't match
PHY_INTERFACE_MODE_RGMII_ID.

Regards
-- 
Alvaro G. M.

On July 2, 2017 3:19:14 AM PDT, Alvaro Gamez Machado [off-list ref] wrote:

On Fri, Jun 30, 2017 at 10:30:38AM -0700, Florian Fainelli wrote:

quoted

On 06/30/2017 02:25 AM, Alvaro Gamez Machado wrote:

quoted

 	if (lp->phy_node) {
-		if (lp->phy_type == XAE_PHY_TYPE_GMII) {
+		if (lp->phy_type == XAE_PHY_TYPE_MII) {
+			phydev = of_phy_connect(lp->ndev, lp->phy_node,
+						axienet_adjust_link, 0,
+						PHY_INTERFACE_MODE_MII);
+		} else if (lp->phy_type == XAE_PHY_TYPE_GMII) {
 			phydev = of_phy_connect(lp->ndev, lp->phy_node,
 						axienet_adjust_link, 0,
 						PHY_INTERFACE_MODE_GMII);

Seems like this could be simplified even further if the values of
lp->phy_type directly mapped to those of phy_interface_t.

Sadly, that's not the case. PHY_INTERFACE_MODE_* belong to a enum of
twenty
different values, of which only _MII and _GMII overlap with XAW_PHY_*
values, but XAE_PHY_TYPE_RGMII_2_0 doesn't match
PHY_INTERFACE_MODE_RGMII_ID.

There are four different rgmii types to account for rx or tx delay, is not there one that really matches? If the driver is using of_get_phy_mode() to retrieve the standard 'phy-mode' / 'phy-connection-type' values then this internal representation is not needed anymore.

-- 
Florian

On Tue, Jul 04, 2017 at 09:24:03AM -0700, Florian Fainelli wrote:

On July 2, 2017 3:19:14 AM PDT, Alvaro Gamez Machado [off-list ref] wrote:

quoted

On Fri, Jun 30, 2017 at 10:30:38AM -0700, Florian Fainelli wrote:

quoted

On 06/30/2017 02:25 AM, Alvaro Gamez Machado wrote:

quoted

 	if (lp->phy_node) {
-		if (lp->phy_type == XAE_PHY_TYPE_GMII) {
+		if (lp->phy_type == XAE_PHY_TYPE_MII) {
+			phydev = of_phy_connect(lp->ndev, lp->phy_node,
+						axienet_adjust_link, 0,
+						PHY_INTERFACE_MODE_MII);
+		} else if (lp->phy_type == XAE_PHY_TYPE_GMII) {
 			phydev = of_phy_connect(lp->ndev, lp->phy_node,
 						axienet_adjust_link, 0,
 						PHY_INTERFACE_MODE_GMII);

Seems like this could be simplified even further if the values of
lp->phy_type directly mapped to those of phy_interface_t.

Sadly, that's not the case. PHY_INTERFACE_MODE_* belong to a enum of
twenty
different values, of which only _MII and _GMII overlap with XAW_PHY_*
values, but XAE_PHY_TYPE_RGMII_2_0 doesn't match
PHY_INTERFACE_MODE_RGMII_ID.

There are four different rgmii types to account for rx or tx delay, is not
there one that really matches?  If the driver is using of_get_phy_mode()
to retrieve the standard 'phy-mode' / 'phy-connection-type' values then
this internal representation is not needed anymore.

Instead of the standard 'phy-mode' / 'phy-connection-type' values, the
driver uses of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &lp->phy_type).

I think the reason for this is that Xilinx provides a utility to generate
device trees from a Vivado/ISE project, which outputs something similar to:

axi_ethernet_eth: ethernet@40c00000 {
	axistream-connected = <&axi_ethernet_0_dma>;
	axistream-control-connected = <&axi_ethernet_0_dma>;
	clock-frequency = <83250000>;
	clocks = <&clk_bus_0>;
	compatible = "xlnx,axi-ethernet-1.00.a";
	device_type = "network";
	interrupt-parent = <&microblaze_0_axi_intc>;
	interrupts = <2 0>;
	phy-mode = "mii";
	reg = <0x40c00000 0x40000>;
	xlnx = <0x0>;
	xlnx,axiliteclkrate = <0x0>;
	xlnx,axisclkrate = <0x0>;
	xlnx,gt-type = <0x0>;
	xlnx,gtinex = <0x0>;
	xlnx,phy-type = <0x0>;
	xlnx,phyaddr = <0x1>;
	xlnx,rable = <0x0>;
	xlnx,rxcsum = <0x2>;
	xlnx,rxlane0-placement = <0x0>;
	xlnx,rxlane1-placement = <0x0>;
	xlnx,rxmem = <0x800>;
	xlnx,rxnibblebitslice0used = <0x1>;
	xlnx,tx-in-upper-nibble = <0x1>;
	xlnx,txcsum = <0x2>;
	xlnx,txlane0-placement = <0x0>;
	xlnx,txlane1-placement = <0x0>;
	phy-handle = <&phy0>;
	axi_ethernetlite_0_mdio: mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		phy0: phy@0 {
			device_type = "ethernet-phy";
			reg = <1>;
		};
	};
};

Basically, every 'xlnx,' attribute is taken, both name and value, directly
from the IP core configuration, even if they are not needed (or even of
remote interest to any possible driver).

So, migrating this to standard of_get_phy_mode is feasible, but I'd say
it's pretty inconvenient from the point of view of the HDL system
designer, and would break existing DTS files people may be using right
now.



-- 
Alvaro G. M.

Instead of the standard 'phy-mode' / 'phy-connection-type' values, the
driver uses of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &lp->phy_type).

I think the reason for this is that Xilinx provides a utility to generate
device trees from a Vivado/ISE project, which outputs something similar to:

axi_ethernet_eth: ethernet@40c00000 {
	axistream-connected = <&axi_ethernet_0_dma>;
	axistream-control-connected = <&axi_ethernet_0_dma>;
	clock-frequency = <83250000>;
	clocks = <&clk_bus_0>;
	compatible = "xlnx,axi-ethernet-1.00.a";
	device_type = "network";
	interrupt-parent = <&microblaze_0_axi_intc>;
	interrupts = <2 0>;
	phy-mode = "mii";
	reg = <0x40c00000 0x40000>;
	xlnx = <0x0>;
	xlnx,axiliteclkrate = <0x0>;
	xlnx,axisclkrate = <0x0>;
	xlnx,gt-type = <0x0>;
	xlnx,gtinex = <0x0>;
	xlnx,phy-type = <0x0>;
	xlnx,phyaddr = <0x1>;
	xlnx,rable = <0x0>;
	xlnx,rxcsum = <0x2>;
	xlnx,rxlane0-placement = <0x0>;
	xlnx,rxlane1-placement = <0x0>;
	xlnx,rxmem = <0x800>;
	xlnx,rxnibblebitslice0used = <0x1>;
	xlnx,tx-in-upper-nibble = <0x1>;
	xlnx,txcsum = <0x2>;
	xlnx,txlane0-placement = <0x0>;
	xlnx,txlane1-placement = <0x0>;
	phy-handle = <&phy0>;
	axi_ethernetlite_0_mdio: mdio {
		#address-cells = <1>;
		#size-cells = <0>;
		phy0: phy@0 {
			device_type = "ethernet-phy";
			reg = <1>;
		};
	};
};

Basically, every 'xlnx,' attribute is taken, both name and value, directly
from the IP core configuration, even if they are not needed (or even of
remote interest to any possible driver).

And it appears none of these are documented in a binding documentation. 

So, migrating this to standard of_get_phy_mode is feasible, but I'd say
it's pretty inconvenient from the point of view of the HDL system
designer, and would break existing DTS files people may be using right
now.

There i disagree. Xilinx should make their tools follow the Linux
standards, not do something proprietary. And the driver can be made to
do the right thing. At the moment, it only seems to be using:

ll_temac_main.c:    p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
ll_temac_main.c:    p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
xilinx_axienet_main.c:	ret = of_property_read_u32(pdev->dev.of_node, "xlnx,txcsum", &value);
xilinx_axienet_main.c:	ret = of_property_read_u32(pdev->dev.of_node, "xlnx,rxcsum", &value);
xilinx_axienet_main.c:	of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem);
xilinx_axienet_main.c:	of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &lp->phy_type);
xilinx_emaclite.c:	lp->tx_ping_pong = get_bool(ofdev, "xlnx,tx-ping-pong");
xilinx_emaclite.c:	lp->rx_ping_pong = get_bool(ofdev, "xlnx,rx-ping-pong");

So the only property which is currently wrong is xlnx,phy-type. As you
said, all the others are garbage. So i would suggest something like:

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
index 33c595f4691d..34a514d3288a 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c

@@ -1539,7 +1539,38 @@ static int axienet_probe(struct platform_device *pdev)
         * the device-tree and accordingly set flags.
         */
        of_property_read_u32(pdev->dev.of_node, "xlnx,rxmem", &lp->rxmem);
-       of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &lp->phy_type);
+
+       /* Start with the proprietary, and broken phy_type */
+       err = of_property_read_u32(pdev->dev.of_node, "xlnx,phy-type", &phy_type);
+       if (!err) {
+               netdev_warn(ndev, "Please upgrade your device tree binary blob to use phy-mode");
+               switch (phy_type) {
+               case XAE_PHY_TYPE_MII:
+                       lp->phy_mode = PHY_INTERFACE_MODE_MII;
+                       break;
+               case XAE_PHY_TYPE_GMII:
+                       lp->phy_mode = PHY_INTERFACE_MODE_GMII;
+                       break;
+               case XAE_PHY_TYPE_RGMII_2_0:
+                       lp->phy_mode = PHY_INTERFACE_MODE_RGMII;
+                       break;
+               case XAE_PHY_TYPE_SGMII:
+                       lp->pht_mode = PHY_INTERFACE_MODE_SGMII;
+                       break;
+               case XAE_PHY_TYPE_1000BASE_X:
+                       lp->pht_mode = PHY_INTERFACE_MODE_1000BASEX;
+                       break;
+               default:
+                       ret = -EINVAL;
+                       goto free_netdev;
+               }
+       } else {
+               lp->phy_mode = of_get_phy_mode(pdev->dev.of_node);
+               if (lp->phy_mode < 0) {
+                       ret = -EINVAL;
+                       goto free_netdev;
+               }
+       }
 
        /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
        np = of_parse_phandle(pdev->dev.of_node, "axistream-connected", 0);

	Andrew

On Wed, Jul 05, 2017 at 04:34:36PM +0200, Andrew Lunn wrote:

That sounds really respectful with current users and sets the basis for a
future removal of that proprietary parameter without causing more harm than
needed, so I like that a lot.

-- 
Alvaro G. M.

That sounds really respectful with current users and sets the basis for a
future removal of that proprietary parameter without causing more harm than
needed, so I like that a lot.

Please feel free to turn it into a real patch and submit it.

       Andrew