[PATCH 0/3] sh_eth: E-DMAC interrupt mask cleanups

STALE3495d

Revision v1 of 2 in this series.

10 messages, 2 authors, 2017-01-24 · open the first message on its own page

[PATCH 0/3] sh_eth: E-DMAC interrupt mask cleanups

From: Sergei Shtylyov <hidden>
Date: 2017-01-22 19:17:25

Hello.

   Here's a set of 3 patches against DaveM's 'net-next.git' repo. The main goal
of this set is to stop using the bare numbers for the E-DMAC interrupt masks.

[1/3] sh_eth: rename EESIPR bits
[2/3] sh_eth: add missing EESIPR bits
[3/3] sh_eth: stop using bare numbers for EESIPR values

MBR, Sergei

[PATCH 1/3] sh_eth: rename EESIPR bits

From: Sergei Shtylyov <hidden>
Date: 2017-01-22 19:18:26

Since the  commit  b0ca2a21f769 ("sh_eth: Add support of SH7763 to sh_eth")
the *enum* declaring the EESIPR bits (interrupt mask) went out of sync with
the *enum* declaring the EESR bits (interrupt status) WRT  bit naming  and
formatting. I'd like to restore the consistency by using EESIPR as the bit
name prefix, renaming the *enum* to EESIPR_BIT, and (finally) renaming the
bits according to the available  Renesas SH77{34|63} manuals...

Signed-off-by: Sergei Shtylyov <redacted>

---
 drivers/net/ethernet/renesas/sh_eth.c |   22 ++++++++++----------
 drivers/net/ethernet/renesas/sh_eth.h |   36 +++++++++++++++++++++-------------
 2 files changed, 34 insertions(+), 24 deletions(-)

Index: net-next/drivers/net/ethernet/renesas/sh_eth.c
===================================================================

--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c
+++ net-next/drivers/net/ethernet/renesas/sh_eth.c

@@ -556,7 +556,7 @@ static struct sh_eth_cpu_data r8a7740_da
 
 	.ecsr_value	= ECSR_ICD | ECSR_MPD,
 	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
-	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff,
 
 	.tx_check	= EESR_TC1 | EESR_FTC,
 	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |

@@ -702,7 +702,7 @@ static struct sh_eth_cpu_data sh7757_dat
 
 	.register_type	= SH_ETH_REG_FAST_SH4,
 
-	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff,
 
 	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |

@@ -769,7 +769,7 @@ static struct sh_eth_cpu_data sh7757_dat
 
 	.ecsr_value	= ECSR_ICD | ECSR_MPD,
 	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
-	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff,
 
 	.tx_check	= EESR_TC1 | EESR_FTC,
 	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |

@@ -800,7 +800,7 @@ static struct sh_eth_cpu_data sh7734_dat
 
 	.ecsr_value	= ECSR_ICD | ECSR_MPD,
 	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
-	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003f07ff,
 
 	.tx_check	= EESR_TC1 | EESR_FTC,
 	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |

@@ -830,7 +830,7 @@ static struct sh_eth_cpu_data sh7763_dat
 
 	.ecsr_value	= ECSR_ICD | ECSR_MPD,
 	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
-	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003f07ff,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003f07ff,
 
 	.tx_check	= EESR_TC1 | EESR_FTC,
 	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |

@@ -851,7 +851,7 @@ static struct sh_eth_cpu_data sh7763_dat
 static struct sh_eth_cpu_data sh7619_data = {
 	.register_type	= SH_ETH_REG_FAST_SH3_SH2,
 
-	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff,
 
 	.apr		= 1,
 	.mpr		= 1,

@@ -862,7 +862,7 @@ static struct sh_eth_cpu_data sh7619_dat
 static struct sh_eth_cpu_data sh771x_data = {
 	.register_type	= SH_ETH_REG_FAST_SH3_SH2,
 
-	.eesipr_value	= DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff,
 	.tsu		= 1,
 };

@@ -1547,10 +1547,10 @@ static void sh_eth_emac_interrupt(struct
 			sh_eth_rcv_snd_disable(ndev);
 		} else {
 			/* Link Up */
-			sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, 0);
+			sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
 			/* clear int */
 			sh_eth_modify(ndev, ECSR, 0, 0);
-			sh_eth_modify(ndev, EESIPR, DMAC_M_ECI, DMAC_M_ECI);
+			sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
 			/* enable tx and rx */
 			sh_eth_rcv_snd_enable(ndev);
 		}

@@ -1652,7 +1652,7 @@ static irqreturn_t sh_eth_interrupt(int
 	 * bit...
 	 */
 	intr_enable = sh_eth_read(ndev, EESIPR);
-	intr_status &= intr_enable | DMAC_M_ECI;
+	intr_status &= intr_enable | EESIPR_ECIIP;
 	if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
 			   cd->eesr_err_check))
 		ret = IRQ_HANDLED;

@@ -3199,7 +3199,7 @@ static int sh_eth_wol_setup(struct net_d
 	/* Only allow ECI interrupts */
 	synchronize_irq(ndev->irq);
 	napi_disable(&mdp->napi);
-	sh_eth_write(ndev, DMAC_M_ECI, EESIPR);
+	sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
 
 	/* Enable MagicPacket */
 	sh_eth_modify(ndev, ECMR, 0, ECMR_MPDE);

Index: net-next/drivers/net/ethernet/renesas/sh_eth.h
===================================================================

--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.h
+++ net-next/drivers/net/ethernet/renesas/sh_eth.h

@@ -268,19 +268,29 @@ enum EESR_BIT {
 				 EESR_TFE | EESR_TDE)
 
 /* EESIPR */
-enum DMAC_IM_BIT {
-	DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
-	DMAC_M_RABT = 0x02000000,
-	DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
-	DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
-	DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
-	DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
-	DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
-	DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
-	DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
-	DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
-	DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
-	DMAC_M_RINT1 = 0x00000001,
+enum EESIPR_BIT {
+	EESIPR_TWBIP	= 0x40000000,
+	EESIPR_TABTIP	= 0x04000000,
+	EESIPR_RABTIP	= 0x02000000,
+	EESIPR_RFCOFIP	= 0x01000000,
+	EESIPR_ADEIP	= 0x00800000,
+	EESIPR_ECIIP	= 0x00400000,
+	EESIPR_FTCIP	= 0x00200000,
+	EESIPR_TDEIP	= 0x00100000,
+	EESIPR_TFUFIP	= 0x00080000,
+	EESIPR_FRIP	= 0x00040000,
+	EESIPR_RDEIP	= 0x00020000,
+	EESIPR_RFOFIP	= 0x00010000,
+	EESIPR_CNDIP	= 0x00000800,
+	EESIPR_DLCIP	= 0x00000400,
+	EESIPR_CDIP	= 0x00000200,
+	EESIPR_TROIP	= 0x00000100,
+	EESIPR_RMAFIP	= 0x00000080,
+	EESIPR_RRFIP	= 0x00000010,
+	EESIPR_RTLFIP	= 0x00000008,
+	EESIPR_RTSFIP	= 0x00000004,
+	EESIPR_PREIP	= 0x00000002,
+	EESIPR_CERFIP	= 0x00000001,
 };
 
 /* Receive descriptor 0 bits */

[PATCH 2/3] sh_eth: add missing EESIPR bits

From: Sergei Shtylyov <hidden>
Date: 2017-01-22 19:18:57

Renesas SH77{34|63} manuals  describe more EESIPR bits than the current
driver. Declare the new bits with the end goal of using the bit names
instead of the bare numbers  for  the 'sh_eth_cpu_data::eesipr_value'
initializers...

Signed-off-by: Sergei Shtylyov <redacted>

---
 drivers/net/ethernet/renesas/sh_eth.h |   10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

Index: net-next/drivers/net/ethernet/renesas/sh_eth.h
===================================================================

--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.h
+++ net-next/drivers/net/ethernet/renesas/sh_eth.h

@@ -269,13 +269,17 @@ enum EESR_BIT {
 
 /* EESIPR */
 enum EESIPR_BIT {
-	EESIPR_TWBIP	= 0x40000000,
+	EESIPR_TWB1IP	= 0x80000000,
+	EESIPR_TWBIP	= 0x40000000,	/* same as TWB0IP */
+	EESIPR_TC1IP	= 0x20000000,
+	EESIPR_TUCIP	= 0x10000000,
+	EESIPR_ROCIP	= 0x08000000,
 	EESIPR_TABTIP	= 0x04000000,
 	EESIPR_RABTIP	= 0x02000000,
 	EESIPR_RFCOFIP	= 0x01000000,
 	EESIPR_ADEIP	= 0x00800000,
 	EESIPR_ECIIP	= 0x00400000,
-	EESIPR_FTCIP	= 0x00200000,
+	EESIPR_FTCIP	= 0x00200000,	/* same as TC0IP */
 	EESIPR_TDEIP	= 0x00100000,
 	EESIPR_TFUFIP	= 0x00080000,
 	EESIPR_FRIP	= 0x00040000,

@@ -286,6 +290,8 @@ enum EESIPR_BIT {
 	EESIPR_CDIP	= 0x00000200,
 	EESIPR_TROIP	= 0x00000100,
 	EESIPR_RMAFIP	= 0x00000080,
+	EESIPR_CEEFIP	= 0x00000040,
+	EESIPR_CELFIP	= 0x00000020,
 	EESIPR_RRFIP	= 0x00000010,
 	EESIPR_RTLFIP	= 0x00000008,
 	EESIPR_RTSFIP	= 0x00000004,

[PATCH 3/3] sh_eth: stop using bare numbers for EESIPR values

From: Sergei Shtylyov <hidden>
Date: 2017-01-22 19:19:40

Now  that we  have almost all EESIPR bits declared (and those that  are
still not are most probably reserved anyway) we can at last replace the
bare  numbers used for 'sh_eth_cpu_data::eesipr_value' initializers with
the bit names ORed together...

Signed-off-by: Sergei Shtylyov <redacted>

---
 drivers/net/ethernet/renesas/sh_eth.c |   89 +++++++++++++++++++++++++++++-----
 1 file changed, 78 insertions(+), 11 deletions(-)

Index: net-next/drivers/net/ethernet/renesas/sh_eth.c
===================================================================

--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c
+++ net-next/drivers/net/ethernet/renesas/sh_eth.c

@@ -518,7 +518,14 @@ static struct sh_eth_cpu_data r7s72100_d
 
 	.ecsr_value	= ECSR_ICD,
 	.ecsipr_value	= ECSIPR_ICDIP,
-	.eesipr_value	= 0xe77f009f,
+	.eesipr_value	= EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
+			  EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
+			  EESIPR_ECIIP |
+			  EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+			  EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
+			  EESIPR_RMAFIP | EESIPR_RRFIP |
+			  EESIPR_RTLFIP | EESIPR_RTSFIP |
+			  EESIPR_PREIP | EESIPR_CERFIP,
 
 	.tx_check	= EESR_TC1 | EESR_FTC,
 	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |

@@ -556,7 +563,14 @@ static struct sh_eth_cpu_data r8a7740_da
 
 	.ecsr_value	= ECSR_ICD | ECSR_MPD,
 	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
-	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
+			  EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+			  EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
+			  0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
+			  EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
+			  EESIPR_CEEFIP | EESIPR_CELFIP |
+			  EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
+			  EESIPR_PREIP | EESIPR_CERFIP,
 
 	.tx_check	= EESR_TC1 | EESR_FTC,
 	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |

@@ -603,7 +617,12 @@ static struct sh_eth_cpu_data r8a777x_da
 
 	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
-	.eesipr_value	= 0x01ff009f,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
+			  EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+			  EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
+			  EESIPR_RMAFIP | EESIPR_RRFIP |
+			  EESIPR_RTLFIP | EESIPR_RTSFIP |
+			  EESIPR_PREIP | EESIPR_CERFIP,
 
 	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |

@@ -626,7 +645,12 @@ static struct sh_eth_cpu_data r8a779x_da
 	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
 	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
 			  ECSIPR_MPDIP,
-	.eesipr_value	= 0x01ff009f,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
+			  EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+			  EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
+			  EESIPR_RMAFIP | EESIPR_RRFIP |
+			  EESIPR_RTLFIP | EESIPR_RTSFIP |
+			  EESIPR_PREIP | EESIPR_CERFIP,
 
 	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |

@@ -667,7 +691,12 @@ static struct sh_eth_cpu_data sh7724_dat
 
 	.ecsr_value	= ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
 	.ecsipr_value	= ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
-	.eesipr_value	= 0x01ff009f,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
+			  EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+			  EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
+			  EESIPR_RMAFIP | EESIPR_RRFIP |
+			  EESIPR_RTLFIP | EESIPR_RTSFIP |
+			  EESIPR_PREIP | EESIPR_CERFIP,
 
 	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |

@@ -702,7 +731,14 @@ static struct sh_eth_cpu_data sh7757_dat
 
 	.register_type	= SH_ETH_REG_FAST_SH4,
 
-	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
+			  EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+			  EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
+			  0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
+			  EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
+			  EESIPR_CEEFIP | EESIPR_CELFIP |
+			  EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
+			  EESIPR_PREIP | EESIPR_CERFIP,
 
 	.tx_check	= EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
 	.eesr_err_check	= EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |

@@ -769,7 +805,14 @@ static struct sh_eth_cpu_data sh7757_dat
 
 	.ecsr_value	= ECSR_ICD | ECSR_MPD,
 	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
-	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
+			  EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+			  EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
+			  0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
+			  EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
+			  EESIPR_CEEFIP | EESIPR_CELFIP |
+			  EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
+			  EESIPR_PREIP | EESIPR_CERFIP,
 
 	.tx_check	= EESR_TC1 | EESR_FTC,
 	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |

@@ -800,7 +843,12 @@ static struct sh_eth_cpu_data sh7734_dat
 
 	.ecsr_value	= ECSR_ICD | ECSR_MPD,
 	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
-	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003f07ff,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
+			  EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+			  EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
+			  EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
+			  EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
+			  EESIPR_PREIP | EESIPR_CERFIP,
 
 	.tx_check	= EESR_TC1 | EESR_FTC,
 	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |

@@ -830,7 +878,12 @@ static struct sh_eth_cpu_data sh7763_dat
 
 	.ecsr_value	= ECSR_ICD | ECSR_MPD,
 	.ecsipr_value	= ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
-	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003f07ff,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
+			  EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+			  EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
+			  EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
+			  EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
+			  EESIPR_PREIP | EESIPR_CERFIP,
 
 	.tx_check	= EESR_TC1 | EESR_FTC,
 	.eesr_err_check	= EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |

@@ -851,7 +904,14 @@ static struct sh_eth_cpu_data sh7763_dat
 static struct sh_eth_cpu_data sh7619_data = {
 	.register_type	= SH_ETH_REG_FAST_SH3_SH2,
 
-	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
+			  EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+			  EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
+			  0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
+			  EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
+			  EESIPR_CEEFIP | EESIPR_CELFIP |
+			  EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
+			  EESIPR_PREIP | EESIPR_CERFIP,
 
 	.apr		= 1,
 	.mpr		= 1,

@@ -862,7 +922,14 @@ static struct sh_eth_cpu_data sh7619_dat
 static struct sh_eth_cpu_data sh771x_data = {
 	.register_type	= SH_ETH_REG_FAST_SH3_SH2,
 
-	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003fffff,
+	.eesipr_value	= EESIPR_RFCOFIP | EESIPR_ECIIP |
+			  EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+			  EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
+			  0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
+			  EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
+			  EESIPR_CEEFIP | EESIPR_CELFIP |
+			  EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
+			  EESIPR_PREIP | EESIPR_CERFIP,
 	.tsu		= 1,
 };

Re: [PATCH 1/3] sh_eth: rename EESIPR bits

From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: 2017-01-23 07:39:36

Hi Sergei,

On Sun, Jan 22, 2017 at 8:18 PM, Sergei Shtylyov
[off-list ref] wrote:

Since the  commit  b0ca2a21f769 ("sh_eth: Add support of SH7763 to sh_eth")
the *enum* declaring the EESIPR bits (interrupt mask) went out of sync with
the *enum* declaring the EESR bits (interrupt status) WRT  bit naming  and
formatting. I'd like to restore the consistency by using EESIPR as the bit
name prefix, renaming the *enum* to EESIPR_BIT, and (finally) renaming the
bits according to the available  Renesas SH77{34|63} manuals...

Which versions of the SH77{34|63} manuals did you use?
Several registers are called slightly different in mine, and also in my
r8a7740 manual.

quoted hunk

--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.h
+++ net-next/drivers/net/ethernet/renesas/sh_eth.h

@@ -268,19 +268,29 @@ enum EESR_BIT {
                                 EESR_TFE | EESR_TDE)

 /* EESIPR */
-enum DMAC_IM_BIT {
-       DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
-       DMAC_M_RABT = 0x02000000,
-       DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
-       DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
-       DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
-       DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
-       DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
-       DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
-       DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
-       DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
-       DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
-       DMAC_M_RINT1 = 0x00000001,
+enum EESIPR_BIT {
+       EESIPR_TWBIP    = 0x40000000,

TWBIP is actually two bits in my manual: TWB1IP and TWB0IP

+       EESIPR_ADEIP    = 0x00800000,

Nonexistent bit in my manual.

+       EESIPR_CNDIP    = 0x00000800,

Nonexistent bit in my manual.

Gr{oetje,eeting}s,

                        Geert

Re: [PATCH 2/3] sh_eth: add missing EESIPR bits

From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: 2017-01-23 07:41:12

On Sun, Jan 22, 2017 at 8:18 PM, Sergei Shtylyov
[off-list ref] wrote:

Renesas SH77{34|63} manuals  describe more EESIPR bits than the current
driver. Declare the new bits with the end goal of using the bit names
instead of the bare numbers  for  the 'sh_eth_cpu_data::eesipr_value'
initializers...

Signed-off-by: Sergei Shtylyov <redacted>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

quoted hunk

---
 drivers/net/ethernet/renesas/sh_eth.h |   10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

Index: net-next/drivers/net/ethernet/renesas/sh_eth.h
===================================================================

--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.h
+++ net-next/drivers/net/ethernet/renesas/sh_eth.h

@@ -269,13 +269,17 @@ enum EESR_BIT {

 /* EESIPR */
 enum EESIPR_BIT {
-       EESIPR_TWBIP    = 0x40000000,
+       EESIPR_TWB1IP   = 0x80000000,
+       EESIPR_TWBIP    = 0x40000000,   /* same as TWB0IP */

Ah, your adding it here ;-)

Gr{oetje,eeting}s,

                        Geert

Re: [PATCH 3/3] sh_eth: stop using bare numbers for EESIPR values

From: Geert Uytterhoeven <geert@linux-m68k.org>
Date: 2017-01-23 08:00:51

Hi Sergei,

On Sun, Jan 22, 2017 at 8:19 PM, Sergei Shtylyov
[off-list ref] wrote:

quoted hunk

Now  that we  have almost all EESIPR bits declared (and those that  are
still not are most probably reserved anyway) we can at last replace the
bare  numbers used for 'sh_eth_cpu_data::eesipr_value' initializers with
the bit names ORed together...

Signed-off-by: Sergei Shtylyov <redacted>

---
 drivers/net/ethernet/renesas/sh_eth.c |   89 +++++++++++++++++++++++++++++-----
 1 file changed, 78 insertions(+), 11 deletions(-)

Index: net-next/drivers/net/ethernet/renesas/sh_eth.c
===================================================================

--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c
+++ net-next/drivers/net/ethernet/renesas/sh_eth.c

quoted hunk

@@ -800,7 +843,12 @@ static struct sh_eth_cpu_data sh7734_dat

        .ecsr_value     = ECSR_ICD | ECSR_MPD,
        .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
-       .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003f07ff,
+       .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
+                         EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+                         EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |

Missing:

        EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |

quoted hunk

+                         EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
+                         EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
+                         EESIPR_PREIP | EESIPR_CERFIP,

        .tx_check       = EESR_TC1 | EESR_FTC,
        .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |

@@ -830,7 +878,12 @@ static struct sh_eth_cpu_data sh7763_dat

        .ecsr_value     = ECSR_ICD | ECSR_MPD,
        .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
-       .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003f07ff,
+       .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
+                         EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+                         EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |

Likewise

+                         EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
+                         EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
+                         EESIPR_PREIP | EESIPR_CERFIP,

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/3] sh_eth: rename EESIPR bits

From: Sergei Shtylyov <hidden>
Date: 2017-01-24 15:47:41

Hello!

On 01/23/2017 10:39 AM, Geert Uytterhoeven wrote:

quoted

Since the  commit  b0ca2a21f769 ("sh_eth: Add support of SH7763 to sh_eth")
the *enum* declaring the EESIPR bits (interrupt mask) went out of sync with
the *enum* declaring the EESR bits (interrupt status) WRT  bit naming  and
formatting. I'd like to restore the consistency by using EESIPR as the bit
name prefix, renaming the *enum* to EESIPR_BIT, and (finally) renaming the
bits according to the available  Renesas SH77{34|63} manuals...

Which versions of the SH77{34|63} manuals did you use?
Several registers are called slightly different in mine, and also in my
r8a7740 manual.

    SH7734 User's Manual: Hardware, Rev.1.00 Jun 2012.
    SH7763 User’s Manual: Hardware, Rev.3.00 Mar 2012

quoted

--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.h
+++ net-next/drivers/net/ethernet/renesas/sh_eth.h

@@ -268,19 +268,29 @@ enum EESR_BIT {
                                 EESR_TFE | EESR_TDE)

 /* EESIPR */
-enum DMAC_IM_BIT {
-       DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
-       DMAC_M_RABT = 0x02000000,
-       DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
-       DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
-       DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
-       DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
-       DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
-       DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
-       DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
-       DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
-       DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
-       DMAC_M_RINT1 = 0x00000001,
+enum EESIPR_BIT {
+       EESIPR_TWBIP    = 0x40000000,

TWBIP is actually two bits in my manual: TWB1IP and TWB0IP

    Yes. I'm adding TWB1 in the next patch.

quoted

+       EESIPR_ADEIP    = 0x00800000,

Nonexistent bit in my manual.

    In mine as well. I used EESR *enum* as a source of info in this case.
Note that this bit is documented for R-Car gen2 (but called differently).

quoted

+       EESIPR_CNDIP    = 0x00000800,

Nonexistent bit in my manual.

    I used the EESR *enum* again.

Gr{oetje,eeting}s,

                        Geert

MBR, Sergei

Re: [PATCH 2/3] sh_eth: add missing EESIPR bits

From: Sergei Shtylyov <hidden>
Date: 2017-01-24 15:51:20

On 01/23/2017 10:41 AM, Geert Uytterhoeven wrote:

quoted

Renesas SH77{34|63} manuals  describe more EESIPR bits than the current
driver. Declare the new bits with the end goal of using the bit names
instead of the bare numbers  for  the 'sh_eth_cpu_data::eesipr_value'
initializers...

Signed-off-by: Sergei Shtylyov <redacted>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

quoted

---
 drivers/net/ethernet/renesas/sh_eth.h |   10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

Index: net-next/drivers/net/ethernet/renesas/sh_eth.h
===================================================================

--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.h
+++ net-next/drivers/net/ethernet/renesas/sh_eth.h

@@ -269,13 +269,17 @@ enum EESR_BIT {

 /* EESIPR */
 enum EESIPR_BIT {
-       EESIPR_TWBIP    = 0x40000000,
+       EESIPR_TWB1IP   = 0x80000000,
+       EESIPR_TWBIP    = 0x40000000,   /* same as TWB0IP */

Ah, your adding it here ;-)

    Do you want me to add such comment in the 1st patch instead?

Gr{oetje,eeting}s,

                        Geert

MRB, Sergei

Re: [PATCH 3/3] sh_eth: stop using bare numbers for EESIPR values

From: Sergei Shtylyov <hidden>
Date: 2017-01-24 15:54:48

On 01/23/2017 11:00 AM, Geert Uytterhoeven wrote:

quoted

Now  that we  have almost all EESIPR bits declared (and those that  are
still not are most probably reserved anyway) we can at last replace the
bare  numbers used for 'sh_eth_cpu_data::eesipr_value' initializers with
the bit names ORed together...

Signed-off-by: Sergei Shtylyov <redacted>

---
 drivers/net/ethernet/renesas/sh_eth.c |   89 +++++++++++++++++++++++++++++-----
 1 file changed, 78 insertions(+), 11 deletions(-)

Index: net-next/drivers/net/ethernet/renesas/sh_eth.c
===================================================================

--- net-next.orig/drivers/net/ethernet/renesas/sh_eth.c
+++ net-next/drivers/net/ethernet/renesas/sh_eth.c

quoted

@@ -800,7 +843,12 @@ static struct sh_eth_cpu_data sh7734_dat

        .ecsr_value     = ECSR_ICD | ECSR_MPD,
        .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
-       .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003f07ff,
+       .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
+                         EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+                         EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |

Missing:

        EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |

    Hm, I thought I'd double-checked all the initializers... TY!

quoted

+                         EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
+                         EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
+                         EESIPR_PREIP | EESIPR_CERFIP,

        .tx_check       = EESR_TC1 | EESR_FTC,
        .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |

@@ -830,7 +878,12 @@ static struct sh_eth_cpu_data sh7763_dat

        .ecsr_value     = ECSR_ICD | ECSR_MPD,
        .ecsipr_value   = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
-       .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP | 0x003f07ff,
+       .eesipr_value   = EESIPR_RFCOFIP | EESIPR_ECIIP |
+                         EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
+                         EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |

Likewise

:-<

quoted

+                         EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
+                         EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
+                         EESIPR_PREIP | EESIPR_CERFIP,

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

    Will add, thanks again...

Gr{oetje,eeting}s,

                        Geert

MBR, Sergei

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