[PATCH] ARM: shmobile: Lager: add Micrel KSZ8041 PHY fixup

Currently on the Lager board NFS timeouts/delays are seen when booting.  That
turned out to happen because the SoC's ETH_LINK signal turns on and off after
each packet.  It is connected to Micrel KSZ8041 PHY's LED0 signal. Ether LEDs
on the Lager board are named LINK and ACTIVE which corresponds to non-default
01 setting of the PHY control register 1 bits 14-15. The 'sh_eth' driver resets
the PHY when opening the network device, so we have to set the mentioned bits
back to 01 from the default 00 value which causes bouncing of ETH_LINK.  That
can be achieved using the PHY platform fixup mechanism if we also modify the
driver to use it..

Signed-off-by: Sergei Shtylyov <redacted>

---
This patch is against the recent Linus' tree. Its effect on NFS issue depends
on the 'sh_eth' driver patch I've posted earlier. 
Simon, please update your 'master' and/or 'fixes' branches since currently it's
impossible to apply fixes to your tree.

 arch/arm/mach-shmobile/board-lager.c |   27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

Index: linux/arch/arm/mach-shmobile/board-lager.c
===================================================================

--- linux.orig/arch/arm/mach-shmobile/board-lager.c
+++ linux/arch/arm/mach-shmobile/board-lager.c

@@ -29,6 +29,7 @@
 #include <linux/pinctrl/machine.h>
 #include <linux/platform_data/gpio-rcar.h>
 #include <linux/platform_device.h>
+#include <linux/phy.h>
 #include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/sh_eth.h>

@@ -155,6 +156,30 @@ static void __init lager_add_standard_de
 					  &ether_pdata, sizeof(ether_pdata));
 }
 
+/*
+ * Ether LEDs on the Lager board are named LINK and ACTIVE which corresponds
+ * to non-default 01 setting of the Micrel KSZ8041 PHY control register 1 bits
+ * 14-15. We have to set them back to 01 from the default 00 value each time
+ * the PHY is reset. It's also important because the PHY's LED0 signal is
+ * connected to SoC's ETH_LINK signal and in the PHY's default mode it will
+ * bounce on and off after each packet, which we apparently want to avoid.
+ */
+static int lager_ksz8041_fixup(struct phy_device *phydev)
+{
+	u16 phyctrl1 = phy_read(phydev, 0x1e);
+
+	phyctrl1 &= ~0xc000;
+	phyctrl1 |= 0x4000;
+	return phy_write(phydev, 0x1e, phyctrl1);
+}
+
+static void __init lager_init(void)
+{
+	lager_add_standard_devices();
+
+	phy_register_fixup_for_id("r8a7790-ether-ff:01", lager_ksz8041_fixup);
+}
+
 static const char *lager_boards_compat_dt[] __initdata = {
 	"renesas,lager",
 	NULL,

@@ -163,6 +188,6 @@ static const char *lager_boards_compat_d
 DT_MACHINE_START(LAGER_DT, "lager")
 	.init_early	= r8a7790_init_delay,
 	.init_time	= r8a7790_timer_init,
-	.init_machine	= lager_add_standard_devices,
+	.init_machine	= lager_init,
 	.dt_compat	= lager_boards_compat_dt,
 MACHINE_END

On Sat, Sep 14, 2013 at 04:29:22AM +0400, Sergei Shtylyov wrote:

Currently on the Lager board NFS timeouts/delays are seen when booting.  That
turned out to happen because the SoC's ETH_LINK signal turns on and off after
each packet.  It is connected to Micrel KSZ8041 PHY's LED0 signal. Ether LEDs
on the Lager board are named LINK and ACTIVE which corresponds to non-default
01 setting of the PHY control register 1 bits 14-15. The 'sh_eth' driver resets
the PHY when opening the network device, so we have to set the mentioned bits
back to 01 from the default 00 value which causes bouncing of ETH_LINK.  That
can be achieved using the PHY platform fixup mechanism if we also modify the
driver to use it..

Signed-off-by: Sergei Shtylyov <redacted>

---
This patch is against the recent Linus' tree. Its effect on NFS issue depends
on the 'sh_eth' driver patch I've posted earlier. 
Simon, please update your 'master' and/or 'fixes' branches since currently it's
impossible to apply fixes to your tree.

Now that rc-1 is out I plan to rebase my tree.
But as I am travelling this week it will have to wait until next week.

On Sat, Sep 14, 2013 at 04:29:22AM +0400, Sergei Shtylyov wrote:

Currently on the Lager board NFS timeouts/delays are seen when booting.  That
turned out to happen because the SoC's ETH_LINK signal turns on and off after
each packet.  It is connected to Micrel KSZ8041 PHY's LED0 signal. Ether LEDs
on the Lager board are named LINK and ACTIVE which corresponds to non-default
01 setting of the PHY control register 1 bits 14-15. The 'sh_eth' driver resets
the PHY when opening the network device, so we have to set the mentioned bits
back to 01 from the default 00 value which causes bouncing of ETH_LINK.  That
can be achieved using the PHY platform fixup mechanism if we also modify the
driver to use it..

Signed-off-by: Sergei Shtylyov <redacted>

---
This patch is against the recent Linus' tree. Its effect on NFS issue depends
on the 'sh_eth' driver patch I've posted earlier. 
Simon, please update your 'master' and/or 'fixes' branches since currently it's
impossible to apply fixes to your tree.

 arch/arm/mach-shmobile/board-lager.c |   27 ++++++++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

Thanks, I have rebased my tree and applied this change to
the fixes-for-v3.12 branch.

And I will push the new tree either in the next
half hour or some time next week - I have to jump on a plane shortly.

On Fri, Sep 13, 2013 at 5:29 PM, Sergei Shtylyov
[off-list ref] wrote:

Currently on the Lager board NFS timeouts/delays are seen when booting.  That
turned out to happen because the SoC's ETH_LINK signal turns on and off after
each packet.  It is connected to Micrel KSZ8041 PHY's LED0 signal. Ether LEDs
on the Lager board are named LINK and ACTIVE which corresponds to non-default
01 setting of the PHY control register 1 bits 14-15. The 'sh_eth' driver resets
the PHY when opening the network device, so we have to set the mentioned bits
back to 01 from the default 00 value which causes bouncing of ETH_LINK.  That
can be achieved using the PHY platform fixup mechanism if we also modify the
driver to use it..

Signed-off-by: Sergei Shtylyov <redacted>

Hi Sergei,

Thanks for your efforts on this. Nice to see that Ethernet for Lager
board support is improving.

Can you please share with us with link speeds you tested? I suspect
that this patch is only needed for some case, like for instance 100
MBit Full Duplex. Fixing the PHY settings makes sense even though only
a single mode needs it, but knowing which link speeds that are known
to work would help a lot.

Cheers,

/ magnus

Hello.

On 09/26/2013 10:50 AM, Magnus Damm wrote:

quoted

Currently on the Lager board NFS timeouts/delays are seen when booting.  That
turned out to happen because the SoC's ETH_LINK signal turns on and off after
each packet.  It is connected to Micrel KSZ8041 PHY's LED0 signal. Ether LEDs
on the Lager board are named LINK and ACTIVE which corresponds to non-default
01 setting of the PHY control register 1 bits 14-15. The 'sh_eth' driver resets
the PHY when opening the network device, so we have to set the mentioned bits
back to 01 from the default 00 value which causes bouncing of ETH_LINK.  That
can be achieved using the PHY platform fixup mechanism if we also modify the
driver to use it..

quoted

Signed-off-by: Sergei Shtylyov <redacted>

Hi Sergei,

Thanks for your efforts on this. Nice to see that Ethernet for Lager
board support is improving.

Can you please share with us with link speeds you tested? I suspect

    100 Mbit/s, full duplex.

that this patch is only needed for some case, like for instance 100
MBit Full Duplex.

    Hm, why? :-O

Fixing the PHY settings makes sense even though only
a single mode needs it, but knowing which link speeds that are known
to work would help a lot.

    This patch should not depend on the link speed and duplex settings.

Cheers,

/ magnus

WBR, Sergei

On Wed, Sep 25, 2013 at 11:50:45PM -0700, Magnus Damm wrote:

On Fri, Sep 13, 2013 at 5:29 PM, Sergei Shtylyov
[off-list ref] wrote:

quoted

Currently on the Lager board NFS timeouts/delays are seen when booting.  That
turned out to happen because the SoC's ETH_LINK signal turns on and off after
each packet.  It is connected to Micrel KSZ8041 PHY's LED0 signal. Ether LEDs
on the Lager board are named LINK and ACTIVE which corresponds to non-default
01 setting of the PHY control register 1 bits 14-15. The 'sh_eth' driver resets
the PHY when opening the network device, so we have to set the mentioned bits
back to 01 from the default 00 value which causes bouncing of ETH_LINK.  That
can be achieved using the PHY platform fixup mechanism if we also modify the
driver to use it..

Signed-off-by: Sergei Shtylyov <redacted>

Hi Sergei,

Thanks for your efforts on this. Nice to see that Ethernet for Lager
board support is improving.

Can you please share with us with link speeds you tested? I suspect
that this patch is only needed for some case, like for instance 100
MBit Full Duplex. Fixing the PHY settings makes sense even though only
a single mode needs it, but knowing which link speeds that are known
to work would help a lot.

Magnus,

I currently have this queued up as a fix for v3.12.
Let me know if you would like me to drop it for now.