On Sun, Mar 04, 2012 at 03:11:53PM +0100, Matthew D. Smith wrote:
Hello - have a question about CPU port configuration in the net/dsa
driver code. Can't seem to work out how to bring up the CPU connected
port on the switch (in our case this is Port 4 hardware strapped with
its embedded PHY enabled).
Hello! I know of at least a couple of platforms that have a DSA chip
connected to the CPU via an MDI type link, but I'm not sure why it's
not working for you. I'd suggest double-checking all the port 5 PHY
registers against the chip documentation..
thanks,
Lennert
Le 2012-03-05 18:12, Lennert Buytenhek a écrit :
On Sun, Mar 04, 2012 at 03:11:53PM +0100, Matthew D. Smith wrote:
quoted
Hello - have a question about CPU port configuration in the net/dsa
driver code. Can't seem to work out how to bring up the CPU
connected
port on the switch (in our case this is Port 4 hardware strapped
with
its embedded PHY enabled).
Hello! I know of at least a couple of platforms that have a DSA chip
connected to the CPU via an MDI type link, but I'm not sure why it's
not working for you. I'd suggest double-checking all the port 5 PHY
registers against the chip documentation..
Hi - perhaps I misunderstood something about the built-in PHY on Port
4. We expected to see the PHY enabled in hardware by setting logic on
the P4_MODE pins. But this doesn't seem to be sufficient as I guess one
still has to enable the PHY in the driver code (like how you do it for
the LAN interfaces in net/dsa/slave.c).
So, after digging through the net/dsa source I found that there is
nothing explicit in the code to enable the CPU port if it needs a PHY. I
would like to say that way it is written assumes that it is always RGMII
so I guess the other platforms you refer to above use customized
(non-mainline) driver code?
I have managed to get the DSA switch working by making the following
changes:
--- ./kernel/linux-source-3.2-csb1724/net/dsa/dsa.c
+++ ./kernel/linux-source-3.2-csb1724/net/dsa/dsa.c (unsaved)
@@ -124,7 +124,6 @@
}
dst->cpu_switch = index;
dst->cpu_port = i;
+ ds->phys_port_mask |= 1 << i;
} else if (!strcmp(name, "dsa")) {
ds->dsa_port_mask |= 1 << i;
} else {
--- ./kernel/linux-source-3.2-csb1724/net/dsa/mv88e6123_61_65.c
+++ ./kernel/linux-source-3.2-csb1724/net/dsa/mv88e6123_61_65.c (unsaved)
@@ -193,7 +193,12 @@
* full duplex.
*/
if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p)) {
- REG_WRITE(addr, 0x01, 0x003e);
+ REG_WRITE(addr, 0x01, 0x0003);
}
else
REG_WRITE(addr, 0x01, 0x0003);
Basically this tells the DSA driver to create an interface for the CPU
port. Perhaps overkill but it does bring up the built-in PHY in the same
way it brings up the LAN slave interfaces. As slave.c sets autoneg on I
needed to change the register value from 1000FD to autoneg. Likewise for
the CPU GE01 port in my platform init code.
I don't really like this, but it works. Is there a better way?
regards
Matthew
On Thu, Mar 08, 2012 at 02:57:57PM +0100, mdsmith@partychief.com wrote:
quoted
quoted
Hello - have a question about CPU port configuration in the net/dsa
driver code. Can't seem to work out how to bring up the CPU
connected
port on the switch (in our case this is Port 4 hardware strapped
with
its embedded PHY enabled).
Hello! I know of at least a couple of platforms that have a DSA chip
connected to the CPU via an MDI type link, but I'm not sure why it's
not working for you. I'd suggest double-checking all the port 5 PHY
registers against the chip documentation..
Hi - perhaps I misunderstood something about the built-in PHY on
Port 4. We expected to see the PHY enabled in hardware by setting
logic on the P4_MODE pins. But this doesn't seem to be sufficient as
I guess one still has to enable the PHY in the driver code (like how
you do it for the LAN interfaces in net/dsa/slave.c).
So, after digging through the net/dsa source I found that there is
nothing explicit in the code to enable the CPU port if it needs a
PHY. I would like to say that way it is written assumes that it is
always RGMII so I guess the other platforms you refer to above use
customized (non-mainline) driver code?
The platform I work on the most configures the CPU PHY port via the
EEPROM and/or handles it in the bootloader (I'm not entirely sure as
I haven't worked on that piece of the system) -- this may work for
you as well.