Re: [RFC 5/5] [powerpc] Implement a p1010rdb clock source.

On Mon, Aug 08, 2011 at 10:37:58AM +0200, Wolfgang Grandegger wrote:

On 08/06/2011 04:34 PM, Robin Holt wrote:

quoted

flexcan driver needs the clk_get, clk_get_rate, etc functions
to work.  This patch provides the minimum functionality.

This needs some more general thoughts... apart from the question where
the code should go.

Like for the MSCAN on the MPC5200, the user should be *able* to select
an appropriate clock source and divider via DTS node properties.
Currently it seems, that the DTS properties must match some
pre-configured values, most likely set by the boot loader. Please
correct me if I'm wrong. For me this is generic and should go into the
Flexcan driver. From there, a platform specific function, e.g.
flexcan_set_clock() might be called.

OK.  Dug a bit more.  The p1010 built-in clocksource seems to be the
periphereal clock frequency which is system bus frequency divided
by 2.  The clock source can not be changed, but the clock divider can
by freezing the interface and setting the CTRL register.  This appears
to only be done by the boot loader.  I do not see why we can not leave
that functionality in the boot loader and then go back to a variation
on my earlier flexcan_clk_* patch.  Is that close to the direction you
think we should go or have I completely misunderstood your wishes?

Thanks,
Robin

On 08/08/2011 01:31 PM, Robin Holt wrote:

OK.  Dug a bit more.  The p1010 built-in clocksource seems to be the
periphereal clock frequency which is system bus frequency divided
by 2.  The clock source can not be changed, but the clock divider can

On arm the clock source is selected by bit 13 of CTRL:

This bit selects the clock source to the CAN protocol interface (CPI)
to be either the peripheral clock (driven by the PLL) or the crystal
oscillator clock. The selected clock is the one fed to the prescaler
to generate the SCLK (SCLK). In order to guarantee reliable
operation, this bit must only be changed while the module is in
disable mode. See Section 24.4.8.4, “Protocol Timing,” for more
information.

0 The CAN engine clock source is the oscillator clock (24.576 MHz)
1 The CAN engine clock source is the bus clock (66.5 MHz)

cheers, Marc

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