[PATCH 30/41]bnx2x: Optimize chip MPS configuration
DORMANTno replies
From: Eilon Greenstein <hidden>
Date: 2009-02-12 18:38:20
Subsystem:
networking drivers, the rest · Maintainers:
Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
Subject: [PATCH 30/41]bnx2x: Optimize chip MPS configuration Signed-off-by: Eilon Greenstein <redacted> --- drivers/net/bnx2x_init.h | 21 +++++++++++---------- 1 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/drivers/net/bnx2x_init.h b/drivers/net/bnx2x_init.h
index 021438f..6fcd1dc 100644
--- a/drivers/net/bnx2x_init.h
+++ b/drivers/net/bnx2x_init.h@@ -655,17 +655,18 @@ static void bnx2x_init_pxp(struct bnx2x *bp) REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); if (CHIP_IS_E1H(bp)) { - REG_WR(bp, PXP2_REG_WR_HC_MPS, w_order+1); - REG_WR(bp, PXP2_REG_WR_USDM_MPS, w_order+1); - REG_WR(bp, PXP2_REG_WR_CSDM_MPS, w_order+1); - REG_WR(bp, PXP2_REG_WR_TSDM_MPS, w_order+1); - REG_WR(bp, PXP2_REG_WR_XSDM_MPS, w_order+1); - REG_WR(bp, PXP2_REG_WR_QM_MPS, w_order+1); - REG_WR(bp, PXP2_REG_WR_TM_MPS, w_order+1); - REG_WR(bp, PXP2_REG_WR_SRC_MPS, w_order+1); - REG_WR(bp, PXP2_REG_WR_DBG_MPS, w_order+1); + val = ((w_order == 0) ? 2 : 3); + REG_WR(bp, PXP2_REG_WR_HC_MPS, val); + REG_WR(bp, PXP2_REG_WR_USDM_MPS, val); + REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val); + REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val); + REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val); + REG_WR(bp, PXP2_REG_WR_QM_MPS, val); + REG_WR(bp, PXP2_REG_WR_TM_MPS, val); + REG_WR(bp, PXP2_REG_WR_SRC_MPS, val); + REG_WR(bp, PXP2_REG_WR_DBG_MPS, val); REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */ - REG_WR(bp, PXP2_REG_WR_CDU_MPS, w_order+1); + REG_WR(bp, PXP2_REG_WR_CDU_MPS, val); } }
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1.5.4.3