RE: [PATCH 03/22] ixgb: Write RA register high word first, increment version

Jeff Garzik wrote:

quoted

-		IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
+		/* Write high reg first to disable the AV bit first */
 		IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
+		IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);

Are you sure the order is guaranteed even after this code change, when
considering all manner of CPU and bus posted writes?

ACK if yes

AFAIK, yes, because a bus controller should not be able to write combine
address sequence 4,0,12,8 into 0-12, because that would be reordering
writes.

I've only seen a strangely configured AMD 8132 bridge write combine
*linear* writes like this 0,4,8,12 into 0-12, so you can either reorder
the writes *or* put in a write flush between linear writes to work
around any issues created by write combining register writes.

In any case I believe this work around to be okay.
--
Jesse