2 messages, 2 authors, 2004-06-30 · open the first message on its own page
From: Andriy Korud <hidden>
Date: 2004-06-30 08:52:31
Hi, i've noticed that on some platforms (noticed on PPC/XScale embedded) PCI cacheline size is not initialized properly and therefore card uses slow "PCI read memory" command instead of optimal "PCI read memory line", which cause serious bendwidth limitations in case of 3+ cards on single PCI bus. Attached patch that fix this issue - please merge review. regards, -- Andriy Korud
From: Jeff Garzik <hidden>
Date: 2004-06-30 09:01:41
Andriy Korud wrote:
Hi, i've noticed that on some platforms (noticed on PPC/XScale embedded) PCI cacheline size is not initialized properly and therefore card uses slow "PCI read memory" command instead of optimal "PCI read memory line", which cause serious bendwidth limitations in case of 3+ cards on single PCI bus. Attached patch that fix this issue - please merge review.
See pci_set_mwi() Jeff