--- v1
+++ v2
@@ -1,351 +1,350 @@
-Marvell chips with controllable PPU have 2 bits to identify the PPU
-state. Chips without PPU control have their PPU enable by default and
-have only 1 bit to read the PPU state.
+Some Marvell chips can enable/disable the PPU on demand. This is needed
+to access the PHY registers when there is no indirection mechanism.
-The only state we care about is the PPU active and polling state
-(meaning PortStatus registers are available for reading).
-
-Add a .ppu_polling op check this state and use it in the PPU
-enable/disable routines. It will also be used later in the switch reset
-code.
+Add two new ppu_enable and ppu_disable ops to describe this and finally
+get rid of the MV88E6XXX_FLAG_PPU* flags.
Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com>
---
- drivers/net/dsa/mv88e6xxx/chip.c | 70 +++++++++++++++++++++++------------
- drivers/net/dsa/mv88e6xxx/global1.c | 33 +++++++++++++++++
+ drivers/net/dsa/mv88e6xxx/chip.c | 78 +++++++++--------------------------
+ drivers/net/dsa/mv88e6xxx/global1.c | 57 +++++++++++++++++++++++++
drivers/net/dsa/mv88e6xxx/global1.h | 3 ++
- drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 13 ++++---
- 4 files changed, 89 insertions(+), 30 deletions(-)
+ drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 19 ++-------
+ 4 files changed, 83 insertions(+), 74 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
-index 6bb7571..db4014c 100644
+index a2fcbcc..8191070 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
-@@ -525,10 +525,32 @@ int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
- return mv88e6xxx_write(chip, addr, reg, val);
- }
-
-+static int mv88e6xxx_ppu_wait(struct mv88e6xxx_chip *chip, bool state)
-+{
-+ bool polling;
-+ int i, err;
-+
-+ if (!chip->info->ops->ppu_polling)
+@@ -527,58 +527,18 @@ int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
+
+ static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
+ {
+- u16 val;
+- int i, err;
++ if (!chip->info->ops->ppu_disable)
+ return 0;
-+
-+ for (i = 0; i < 16; i++) {
-+ err = chip->info->ops->ppu_polling(chip, &polling);
-+ if (err)
-+ return err;
-+
-+ usleep_range(1000, 2000);
-+
-+ if (polling == state)
-+ return 0;
-+ }
-+
-+ return -ETIMEDOUT;
-+}
-+
- static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
- {
- u16 val;
-- int i, err;
-+ int err;
-
- err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
- if (err)
-@@ -539,23 +561,13 @@ static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
- if (err)
- return err;
-
+
+- err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
+- if (err)
+- return err;
+-
+- err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
+- val & ~GLOBAL_CONTROL_PPU_ENABLE);
+- if (err)
+- return err;
+-
- for (i = 0; i < 16; i++) {
- err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
- if (err)
- return err;
-
- usleep_range(1000, 2000);
-- if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING)
+- val &= GLOBAL_STATUS_PPU_STATE_MASK;
+- if (val != GLOBAL_STATUS_PPU_STATE_POLLING)
- return 0;
- }
-
- return -ETIMEDOUT;
-+ return mv88e6xxx_ppu_wait(chip, false);
++ return chip->info->ops->ppu_disable(chip);
}
static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
{
- u16 val;
+- u16 val;
- int i, err;
-+ int err;
-
- err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
- if (err)
-@@ -566,17 +578,7 @@ static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
- if (err)
- return err;
-
++ if (!chip->info->ops->ppu_enable)
++ return 0;
+
+- err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
+- if (err)
+- return err;
+-
+- err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL,
+- val | GLOBAL_CONTROL_PPU_ENABLE);
+- if (err)
+- return err;
+-
- for (i = 0; i < 16; i++) {
- err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val);
- if (err)
- return err;
-
- usleep_range(1000, 2000);
-- if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING)
+- val &= GLOBAL_STATUS_PPU_STATE_MASK;
+- if (val == GLOBAL_STATUS_PPU_STATE_POLLING)
- return 0;
- }
-
- return -ETIMEDOUT;
-+ return mv88e6xxx_ppu_wait(chip, true);
++ return chip->info->ops->ppu_enable(chip);
}
static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
-@@ -3212,6 +3214,7 @@ static const struct mv88e6xxx_ops mv88e6085_ops = {
- .stats_get_sset_count = mv88e6095_stats_get_sset_count,
+@@ -2746,22 +2706,12 @@ static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip)
+ {
+ struct dsa_switch *ds = chip->ds;
+ u32 upstream_port = dsa_upstream_port(ds);
+- u16 reg;
+ int err;
+
+ /* Enable the PHY Polling Unit if present, don't discard any packets,
+ * and mask all interrupt sources.
+ */
+- err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®);
+- if (err < 0)
+- return err;
+-
+- reg &= ~GLOBAL_CONTROL_PPU_ENABLE;
+- if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
+- mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
+- reg |= GLOBAL_CONTROL_PPU_ENABLE;
+-
+- err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg);
++ err = mv88e6xxx_ppu_enable(chip);
+ if (err)
+ return err;
+
+@@ -3223,6 +3173,8 @@ static const struct mv88e6xxx_ops mv88e6085_ops = {
+ .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
+ .g1_set_egress_port = mv88e6095_g1_set_egress_port,
+ .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
++ .ppu_enable = mv88e6185_g1_ppu_enable,
++ .ppu_disable = mv88e6185_g1_ppu_disable,
+ .reset = mv88e6185_g1_reset,
+ };
+
+@@ -3241,6 +3193,8 @@ static const struct mv88e6xxx_ops mv88e6095_ops = {
.stats_get_strings = mv88e6095_stats_get_strings,
.stats_get_stats = mv88e6095_stats_get_stats,
-+ .ppu_polling = mv88e6185_g1_ppu_polling,
- .reset = mv88e6185_g1_reset,
- };
-
-@@ -3227,6 +3230,7 @@ static const struct mv88e6xxx_ops mv88e6095_ops = {
- .stats_get_sset_count = mv88e6095_stats_get_sset_count,
- .stats_get_strings = mv88e6095_stats_get_strings,
- .stats_get_stats = mv88e6095_stats_get_stats,
-+ .ppu_polling = mv88e6185_g1_ppu_polling,
- .reset = mv88e6185_g1_reset,
- };
-
-@@ -3242,6 +3246,7 @@ static const struct mv88e6xxx_ops mv88e6097_ops = {
- .stats_get_sset_count = mv88e6095_stats_get_sset_count,
- .stats_get_strings = mv88e6095_stats_get_strings,
- .stats_get_stats = mv88e6095_stats_get_stats,
-+ .ppu_polling = mv88e6185_g1_ppu_polling,
- .reset = mv88e6185_g1_reset,
- };
-
-@@ -3272,6 +3277,7 @@ static const struct mv88e6xxx_ops mv88e6131_ops = {
- .stats_get_sset_count = mv88e6095_stats_get_sset_count,
- .stats_get_strings = mv88e6095_stats_get_strings,
- .stats_get_stats = mv88e6095_stats_get_stats,
-+ .ppu_polling = mv88e6185_g1_ppu_polling,
- .reset = mv88e6185_g1_reset,
- };
-
-@@ -3318,6 +3324,7 @@ static const struct mv88e6xxx_ops mv88e6171_ops = {
- .stats_get_sset_count = mv88e6095_stats_get_sset_count,
- .stats_get_strings = mv88e6095_stats_get_strings,
- .stats_get_stats = mv88e6095_stats_get_stats,
-+ .ppu_polling = mv88e6352_g1_ppu_polling,
- .reset = mv88e6352_g1_reset,
- };
-
-@@ -3336,6 +3343,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
- .stats_get_sset_count = mv88e6095_stats_get_sset_count,
- .stats_get_strings = mv88e6095_stats_get_strings,
- .stats_get_stats = mv88e6095_stats_get_stats,
-+ .ppu_polling = mv88e6352_g1_ppu_polling,
- .reset = mv88e6352_g1_reset,
- };
-
-@@ -3352,6 +3360,7 @@ static const struct mv88e6xxx_ops mv88e6175_ops = {
- .stats_get_sset_count = mv88e6095_stats_get_sset_count,
- .stats_get_strings = mv88e6095_stats_get_strings,
- .stats_get_stats = mv88e6095_stats_get_stats,
-+ .ppu_polling = mv88e6352_g1_ppu_polling,
- .reset = mv88e6352_g1_reset,
- };
-
-@@ -3370,6 +3379,7 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {
- .stats_get_sset_count = mv88e6095_stats_get_sset_count,
- .stats_get_strings = mv88e6095_stats_get_strings,
- .stats_get_stats = mv88e6095_stats_get_stats,
-+ .ppu_polling = mv88e6352_g1_ppu_polling,
- .reset = mv88e6352_g1_reset,
- };
-
-@@ -3385,6 +3395,7 @@ static const struct mv88e6xxx_ops mv88e6185_ops = {
- .stats_get_sset_count = mv88e6095_stats_get_sset_count,
- .stats_get_strings = mv88e6095_stats_get_strings,
- .stats_get_stats = mv88e6095_stats_get_stats,
-+ .ppu_polling = mv88e6185_g1_ppu_polling,
- .reset = mv88e6185_g1_reset,
- };
-
-@@ -3402,6 +3413,7 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {
- .stats_get_sset_count = mv88e6320_stats_get_sset_count,
- .stats_get_strings = mv88e6320_stats_get_strings,
- .stats_get_stats = mv88e6390_stats_get_stats,
-+ .ppu_polling = mv88e6352_g1_ppu_polling,
- .reset = mv88e6352_g1_reset,
- };
-
-@@ -3419,6 +3431,7 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {
- .stats_get_sset_count = mv88e6320_stats_get_sset_count,
- .stats_get_strings = mv88e6320_stats_get_strings,
- .stats_get_stats = mv88e6390_stats_get_stats,
-+ .ppu_polling = mv88e6352_g1_ppu_polling,
- .reset = mv88e6352_g1_reset,
- };
-
-@@ -3436,6 +3449,7 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {
- .stats_get_sset_count = mv88e6320_stats_get_sset_count,
- .stats_get_strings = mv88e6320_stats_get_strings,
- .stats_get_stats = mv88e6390_stats_get_stats,
-+ .ppu_polling = mv88e6352_g1_ppu_polling,
- .reset = mv88e6352_g1_reset,
- };
-
-@@ -3454,6 +3468,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
- .stats_get_sset_count = mv88e6095_stats_get_sset_count,
- .stats_get_strings = mv88e6095_stats_get_strings,
- .stats_get_stats = mv88e6095_stats_get_stats,
-+ .ppu_polling = mv88e6352_g1_ppu_polling,
- .reset = mv88e6352_g1_reset,
- };
-
-@@ -3471,6 +3486,7 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {
- .stats_get_sset_count = mv88e6320_stats_get_sset_count,
- .stats_get_strings = mv88e6320_stats_get_strings,
- .stats_get_stats = mv88e6390_stats_get_stats,
-+ .ppu_polling = mv88e6352_g1_ppu_polling,
- .reset = mv88e6352_g1_reset,
- };
-
-@@ -3521,6 +3537,7 @@ static const struct mv88e6xxx_ops mv88e6350_ops = {
- .stats_get_sset_count = mv88e6095_stats_get_sset_count,
- .stats_get_strings = mv88e6095_stats_get_strings,
- .stats_get_stats = mv88e6095_stats_get_stats,
-+ .ppu_polling = mv88e6352_g1_ppu_polling,
- .reset = mv88e6352_g1_reset,
- };
-
-@@ -3537,6 +3554,7 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {
- .stats_get_sset_count = mv88e6095_stats_get_sset_count,
- .stats_get_strings = mv88e6095_stats_get_strings,
- .stats_get_stats = mv88e6095_stats_get_stats,
-+ .ppu_polling = mv88e6352_g1_ppu_polling,
- .reset = mv88e6352_g1_reset,
- };
-
-@@ -3555,6 +3573,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
- .stats_get_sset_count = mv88e6095_stats_get_sset_count,
- .stats_get_strings = mv88e6095_stats_get_strings,
- .stats_get_stats = mv88e6095_stats_get_stats,
-+ .ppu_polling = mv88e6352_g1_ppu_polling,
- .reset = mv88e6352_g1_reset,
- };
-
-@@ -3572,6 +3591,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops = {
- .stats_get_sset_count = mv88e6320_stats_get_sset_count,
- .stats_get_strings = mv88e6320_stats_get_strings,
- .stats_get_stats = mv88e6390_stats_get_stats,
-+ .ppu_polling = mv88e6352_g1_ppu_polling,
- .reset = mv88e6352_g1_reset,
- };
-
-@@ -3589,6 +3609,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
- .stats_get_sset_count = mv88e6320_stats_get_sset_count,
- .stats_get_strings = mv88e6320_stats_get_strings,
- .stats_get_stats = mv88e6390_stats_get_stats,
-+ .ppu_polling = mv88e6352_g1_ppu_polling,
- .reset = mv88e6352_g1_reset,
- };
-
-@@ -3606,6 +3627,7 @@ static const struct mv88e6xxx_ops mv88e6391_ops = {
- .stats_get_sset_count = mv88e6320_stats_get_sset_count,
- .stats_get_strings = mv88e6320_stats_get_strings,
- .stats_get_stats = mv88e6390_stats_get_stats,
-+ .ppu_polling = mv88e6352_g1_ppu_polling,
- .reset = mv88e6352_g1_reset,
- };
+ .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
++ .ppu_enable = mv88e6185_g1_ppu_enable,
++ .ppu_disable = mv88e6185_g1_ppu_disable,
+ .reset = mv88e6185_g1_reset,
+ };
+
+@@ -3266,6 +3220,8 @@ static const struct mv88e6xxx_ops mv88e6097_ops = {
+ .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
+ .g1_set_egress_port = mv88e6095_g1_set_egress_port,
+ .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
++ .ppu_enable = mv88e6185_g1_ppu_enable,
++ .ppu_disable = mv88e6185_g1_ppu_disable,
+ .reset = mv88e6185_g1_reset,
+ };
+
+@@ -3311,6 +3267,8 @@ static const struct mv88e6xxx_ops mv88e6131_ops = {
+ .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
+ .g1_set_egress_port = mv88e6095_g1_set_egress_port,
+ .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
++ .ppu_enable = mv88e6185_g1_ppu_enable,
++ .ppu_disable = mv88e6185_g1_ppu_disable,
+ .reset = mv88e6185_g1_reset,
+ };
+
+@@ -3483,6 +3441,8 @@ static const struct mv88e6xxx_ops mv88e6185_ops = {
+ .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
+ .g1_set_egress_port = mv88e6095_g1_set_egress_port,
+ .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
++ .ppu_enable = mv88e6185_g1_ppu_enable,
++ .ppu_disable = mv88e6185_g1_ppu_disable,
+ .reset = mv88e6185_g1_reset,
+ };
+
+@@ -4262,13 +4222,13 @@ static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
+
+ static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip)
+ {
+- if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
++ if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
+ mv88e6xxx_ppu_state_init(chip);
+ }
+
+ static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip)
+ {
+- if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
++ if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable)
+ mv88e6xxx_ppu_state_destroy(chip);
+ }
diff --git a/drivers/net/dsa/mv88e6xxx/global1.c b/drivers/net/dsa/mv88e6xxx/global1.c
-index 27f37a7..371d96a 100644
+index c868eb0..75af86a 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.c
+++ b/drivers/net/dsa/mv88e6xxx/global1.c
-@@ -33,6 +33,39 @@ int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
- return mv88e6xxx_wait(chip, chip->info->global1_addr, reg, mask);
- }
-
-+/* Offset 0x00: Switch Global Status Register */
-+
-+int mv88e6185_g1_ppu_polling(struct mv88e6xxx_chip *chip, bool *polling)
+@@ -35,6 +35,27 @@ int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask)
+
+ /* Offset 0x00: Switch Global Status Register */
+
++static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
+{
+ u16 state;
++ int i, err;
++
++ for (i = 0; i < 16; i++) {
++ err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &state);
++ if (err)
++ return err;
++
++ /* Check the value of the PPUState bits 15:14 */
++ state &= GLOBAL_STATUS_PPU_STATE_MASK;
++ if (state != GLOBAL_STATUS_PPU_STATE_POLLING)
++ return 0;
++
++ usleep_range(1000, 2000);
++ }
++
++ return -ETIMEDOUT;
++}
++
+ static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
+ {
+ u16 state;
+@@ -154,6 +175,42 @@ int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
+ return mv88e6352_g1_wait_ppu_polling(chip);
+ }
+
++int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
++{
++ u16 val;
+ int err;
+
-+ /* Check the value of the PPUState bits 15:14 */
-+ err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &state);
++ err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
+ if (err)
+ return err;
+
-+ state &= GLOBAL_STATUS_PPU_STATE_MASK;
-+ *polling = state == GLOBAL_STATUS_PPU_STATE_POLLING;
-+
-+ return 0;
-+}
-+
-+int mv88e6352_g1_ppu_polling(struct mv88e6xxx_chip *chip, bool *polling)
-+{
-+ u16 state;
-+ int err;
-+
-+ /* Check the value of the PPUState (or InitState) bit 15 */
-+ err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &state);
++ val |= GLOBAL_CONTROL_PPU_ENABLE;
++
++ err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, val);
+ if (err)
+ return err;
+
-+ *polling = !!(state & GLOBAL_STATUS_PPU_STATE);
-+
-+ return 0;
++ return mv88e6185_g1_wait_ppu_polling(chip);
+}
+
- /* Offset 0x04: Switch Global Control Register */
-
- int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
++int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
++{
++ u16 val;
++ int err;
++
++ err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val);
++ if (err)
++ return err;
++
++ val &= ~GLOBAL_CONTROL_PPU_ENABLE;
++
++ err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, val);
++ if (err)
++ return err;
++
++ return mv88e6185_g1_wait_ppu_disabled(chip);
++}
++
+ /* Offset 0x1a: Monitor Control */
+ /* Offset 0x1a: Monitor & MGMT Control on some devices */
+
diff --git a/drivers/net/dsa/mv88e6xxx/global1.h b/drivers/net/dsa/mv88e6xxx/global1.h
-index 868a281..cdccf473 100644
+index 9fca215..1aec738 100644
--- a/drivers/net/dsa/mv88e6xxx/global1.h
+++ b/drivers/net/dsa/mv88e6xxx/global1.h
-@@ -20,6 +20,9 @@ int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
- int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
- int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask);
-
-+int mv88e6185_g1_ppu_polling(struct mv88e6xxx_chip *chip, bool *polling);
-+int mv88e6352_g1_ppu_polling(struct mv88e6xxx_chip *chip, bool *polling);
-+
+@@ -23,6 +23,9 @@ int mv88e6xxx_g1_wait(struct mv88e6xxx_chip *chip, int reg, u16 mask);
int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);
int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);
++int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);
++int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);
++
+ int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip);
+ int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
+ int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
diff --git a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h b/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
-index 9e51405..9ae228c 100644
+index f201d13..af54bae 100644
--- a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
+++ b/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
-@@ -175,12 +175,11 @@
-
- #define GLOBAL_STATUS 0x00
- #define GLOBAL_STATUS_PPU_STATE BIT(15) /* 6351 and 6171 */
--/* Two bits for 6165, 6185 etc */
--#define GLOBAL_STATUS_PPU_MASK (0x3 << 14)
--#define GLOBAL_STATUS_PPU_DISABLED_RST (0x0 << 14)
--#define GLOBAL_STATUS_PPU_INITIALIZING (0x1 << 14)
--#define GLOBAL_STATUS_PPU_DISABLED (0x2 << 14)
--#define GLOBAL_STATUS_PPU_POLLING (0x3 << 14)
-+#define GLOBAL_STATUS_PPU_STATE_MASK (0x3 << 14) /* 6165 6185 */
-+#define GLOBAL_STATUS_PPU_STATE_DISABLED_RST (0x0 << 14)
-+#define GLOBAL_STATUS_PPU_STATE_INITIALIZING (0x1 << 14)
-+#define GLOBAL_STATUS_PPU_STATE_DISABLED (0x2 << 14)
-+#define GLOBAL_STATUS_PPU_STATE_POLLING (0x3 << 14)
- #define GLOBAL_STATUS_IRQ_AVB 8
- #define GLOBAL_STATUS_IRQ_DEVICE 7
- #define GLOBAL_STATUS_IRQ_STATS 6
-@@ -765,6 +764,8 @@ struct mv88e6xxx_ops {
+@@ -490,12 +490,6 @@ enum mv88e6xxx_cap {
+ MV88E6XXX_CAP_G2_PVT_DATA, /* (0x0c) Cross Chip Port VLAN Data */
+ MV88E6XXX_CAP_G2_POT, /* (0x0f) Priority Override Table */
+
+- /* PHY Polling Unit.
+- * See GLOBAL_CONTROL_PPU_ENABLE and GLOBAL_STATUS_PPU_POLLING.
+- */
+- MV88E6XXX_CAP_PPU,
+- MV88E6XXX_CAP_PPU_ACTIVE,
+-
+ /* Per VLAN Spanning Tree Unit (STU).
+ * The Port State database, if present, is accessed through VTU
+ * operations and dedicated SID registers. See GLOBAL_VTU_SID.
+@@ -537,8 +531,6 @@ enum mv88e6xxx_cap {
+ #define MV88E6XXX_FLAG_G2_PVT_DATA BIT_ULL(MV88E6XXX_CAP_G2_PVT_DATA)
+ #define MV88E6XXX_FLAG_G2_POT BIT_ULL(MV88E6XXX_CAP_G2_POT)
+
+-#define MV88E6XXX_FLAG_PPU BIT_ULL(MV88E6XXX_CAP_PPU)
+-#define MV88E6XXX_FLAG_PPU_ACTIVE BIT_ULL(MV88E6XXX_CAP_PPU_ACTIVE)
+ #define MV88E6XXX_FLAG_STU BIT_ULL(MV88E6XXX_CAP_STU)
+ #define MV88E6XXX_FLAG_TEMP BIT_ULL(MV88E6XXX_CAP_TEMP)
+ #define MV88E6XXX_FLAG_TEMP_LIMIT BIT_ULL(MV88E6XXX_CAP_TEMP_LIMIT)
+@@ -567,7 +559,6 @@ enum mv88e6xxx_cap {
+ #define MV88E6XXX_FLAGS_FAMILY_6095 \
+ (MV88E6XXX_FLAG_GLOBAL2 | \
+ MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
+- MV88E6XXX_FLAG_PPU | \
+ MV88E6XXX_FLAG_VTU | \
+ MV88E6XXX_FLAGS_MULTI_CHIP)
+
+@@ -578,7 +569,6 @@ enum mv88e6xxx_cap {
+ MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
+ MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
+ MV88E6XXX_FLAG_G2_POT | \
+- MV88E6XXX_FLAG_PPU | \
+ MV88E6XXX_FLAG_STU | \
+ MV88E6XXX_FLAG_VTU | \
+ MV88E6XXX_FLAGS_IRL | \
+@@ -605,7 +595,6 @@ enum mv88e6xxx_cap {
+ MV88E6XXX_FLAG_G2_INT | \
+ MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
+ MV88E6XXX_FLAGS_MULTI_CHIP | \
+- MV88E6XXX_FLAG_PPU | \
+ MV88E6XXX_FLAG_VTU)
+
+ #define MV88E6XXX_FLAGS_FAMILY_6320 \
+@@ -614,7 +603,6 @@ enum mv88e6xxx_cap {
+ MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
+ MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
+ MV88E6XXX_FLAG_G2_POT | \
+- MV88E6XXX_FLAG_PPU_ACTIVE | \
+ MV88E6XXX_FLAG_TEMP | \
+ MV88E6XXX_FLAG_TEMP_LIMIT | \
+ MV88E6XXX_FLAG_VTU | \
+@@ -630,7 +618,6 @@ enum mv88e6xxx_cap {
+ MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
+ MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
+ MV88E6XXX_FLAG_G2_POT | \
+- MV88E6XXX_FLAG_PPU_ACTIVE | \
+ MV88E6XXX_FLAG_STU | \
+ MV88E6XXX_FLAG_TEMP | \
+ MV88E6XXX_FLAG_VTU | \
+@@ -647,7 +634,6 @@ enum mv88e6xxx_cap {
+ MV88E6XXX_FLAG_G2_MGMT_EN_2X | \
+ MV88E6XXX_FLAG_G2_MGMT_EN_0X | \
+ MV88E6XXX_FLAG_G2_POT | \
+- MV88E6XXX_FLAG_PPU_ACTIVE | \
+ MV88E6XXX_FLAG_STU | \
+ MV88E6XXX_FLAG_TEMP | \
+ MV88E6XXX_FLAG_TEMP_LIMIT | \
+@@ -662,7 +648,6 @@ struct mv88e6xxx_ops;
+ #define MV88E6XXX_FLAGS_FAMILY_6390 \
+ (MV88E6XXX_FLAG_EEE | \
+ MV88E6XXX_FLAG_GLOBAL2 | \
+- MV88E6XXX_FLAG_PPU_ACTIVE | \
+ MV88E6XXX_FLAG_STU | \
+ MV88E6XXX_FLAG_TEMP | \
+ MV88E6XXX_FLAG_TEMP_LIMIT | \
+@@ -792,6 +777,10 @@ struct mv88e6xxx_ops {
int (*phy_write)(struct mv88e6xxx_chip *chip, int addr, int reg,
u16 val);
+ /* PHY Polling Unit (PPU) operations */
-+ int (*ppu_polling)(struct mv88e6xxx_chip *chip, bool *polling);
++ int (*ppu_enable)(struct mv88e6xxx_chip *chip);
++ int (*ppu_disable)(struct mv88e6xxx_chip *chip);
++
/* Switch Software Reset */
int (*reset)(struct mv88e6xxx_chip *chip);