Reviews by randolph@andestech.com · lkml

All review-attestation trailers (Reviewed-by / Acked-by / Tested-by / Reported-by / Suggested-by / Co-developed-by / Reported-and-tested-by) by this address on the lkml archive.

11 attestations . (1 Co-developed-by, 10 Reviewed-by)

• STALE189d REVIEWED: 14 (13M) [PATCH v2] PCI: dwc: Use multiple ATU regions for large bridge windows
  2026-01-09 · Co-developed-by
• STALE867d REVIEWED: 6 (6M) [tip: irq/msi] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
  2024-02-23 · Reviewed-by
• STALE867d REVIEWED: 7 (6M) [tip: irq/msi] irqchip/riscv-intc: Allow large non-standard interrupt number
  2024-02-23 · Reviewed-by
• STALE867d LANDED: 7 (6M) [PATCH v9 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number
  2024-02-22 · Reviewed-by
• STALE867d LANDED: 6 (6M) [PATCH v9 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
  2024-02-22 · Reviewed-by
• STALE889d REVIEWED: 7 (6M) [PATCH v8 02/10] irqchip/riscv-intc: Allow large non-standard interrupt number
  2024-01-29 · Reviewed-by
• STALE889d REVIEWED: 6 (6M) [PATCH v8 03/10] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
  2024-01-29 · Reviewed-by
• STALE920d REVIEWED: 1 (1M) [PATCH v7 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number
  2024-01-10 · Reviewed-by
• STALE920d REVIEWED: 1 (1M) [PATCH v7 03/16] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
  2024-01-10 · Reviewed-by
• STALE947d REVIEWED: 1 (1M) [PATCH v6 03/16] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
  2023-12-25 · Reviewed-by
• STALE947d REVIEWED: 1 (1M) [PATCH v6 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number
  2023-12-25 · Reviewed-by