--- v6
+++ v9
@@ -1,263 +1,271 @@
-TCE tables might get too big in case of 4K IOMMU pages and DDW enabled
-on huge guests (hundreds of GB of RAM) so the kernel might be unable to
-allocate contiguous chunk of physical memory to store the TCE table.
-
-To address this, POWER8 CPU (actually, IODA2) supports multi-level TCE tables,
-up to 5 levels which splits the table into a tree of smaller subtables.
-
-This adds multi-level TCE tables support to pnv_pci_ioda2_create_table()
-and pnv_pci_ioda2_free_table() callbacks.
+This extends iommu_table_group_ops by a set of callbacks to support
+dynamic DMA windows management.
+
+create_table() creates a TCE table with specific parameters.
+it receives iommu_table_group to know nodeid in order to allocate
+TCE table memory closer to the PHB. The exact format of allocated
+multi-level table might be also specific to the PHB model (not
+the case now though).
+This callback calculated the DMA window offset on a PCI bus from @num
+and stores it in a just created table.
+
+set_window() sets the window at specified TVT index + @num on PHB.
+
+unset_window() unsets the window from specified TVT.
+
+This adds a free() callback to iommu_table_ops to free the memory
+(potentially a tree of tables) allocated for the TCE table.
+
+create_table() and free() are supposed to be called once per
+VFIO container and set_window()/unset_window() are supposed to be
+called for every group in a container.
+
+This adds IOMMU capabilities to iommu_table_group such as default
+32bit window parameters and others.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
- arch/powerpc/include/asm/iommu.h | 2 +
- arch/powerpc/platforms/powernv/pci-ioda.c | 127 ++++++++++++++++++++++++------
- arch/powerpc/platforms/powernv/pci.c | 19 +++++
- 3 files changed, 122 insertions(+), 26 deletions(-)
+ arch/powerpc/include/asm/iommu.h | 19 ++++++++
+ arch/powerpc/platforms/powernv/pci-ioda.c | 75 ++++++++++++++++++++++++++---
+ arch/powerpc/platforms/powernv/pci-p5ioc2.c | 12 +++--
+ 3 files changed, 96 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/include/asm/iommu.h b/arch/powerpc/include/asm/iommu.h
-index fd118ea..4007432 100644
+index 0f50ee2..7694546 100644
--- a/arch/powerpc/include/asm/iommu.h
+++ b/arch/powerpc/include/asm/iommu.h
-@@ -88,6 +88,8 @@ struct iommu_pool {
- struct iommu_table {
- unsigned long it_busno; /* Bus number this table belongs to */
- unsigned long it_size; /* Size of iommu table in entries */
-+ unsigned long it_indirect_levels;
-+ unsigned long it_level_size;
- unsigned long it_offset; /* Offset into global table */
- unsigned long it_base; /* mapped address of tce table */
- unsigned long it_index; /* which iommu table this is */
+@@ -70,6 +70,7 @@ struct iommu_table_ops {
+ /* get() returns a physical address */
+ unsigned long (*get)(struct iommu_table *tbl, long index);
+ void (*flush)(struct iommu_table *tbl);
++ void (*free)(struct iommu_table *tbl);
+ };
+
+ /* These are used by VIO */
+@@ -148,6 +149,17 @@ extern struct iommu_table *iommu_init_table(struct iommu_table * tbl,
+ struct iommu_table_group;
+
+ struct iommu_table_group_ops {
++ long (*create_table)(struct iommu_table_group *table_group,
++ int num,
++ __u32 page_shift,
++ __u64 window_size,
++ __u32 levels,
++ struct iommu_table *tbl);
++ long (*set_window)(struct iommu_table_group *table_group,
++ int num,
++ struct iommu_table *tblnew);
++ long (*unset_window)(struct iommu_table_group *table_group,
++ int num);
+ /*
+ * Switches ownership from the kernel itself to an external
+ * user. While onwership is taken, the kernel cannot use IOMMU itself.
+@@ -160,6 +172,13 @@ struct iommu_table_group {
+ #ifdef CONFIG_IOMMU_API
+ struct iommu_group *group;
+ #endif
++ /* Some key properties of IOMMU */
++ __u32 tce32_start;
++ __u32 tce32_size;
++ __u64 pgsizes; /* Bitmap of supported page sizes */
++ __u32 max_dynamic_windows_supported;
++ __u32 max_levels;
++
+ struct iommu_table tables[IOMMU_TABLE_GROUP_MAX_TABLES];
+ struct iommu_table_group_ops *ops;
+ };
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
-index 8bb5d6d..bdf511d 100644
+index cc1d09c..4828837 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c
-@@ -47,6 +47,8 @@
- #include "powernv.h"
- #include "pci.h"
-
-+#define POWERNV_IOMMU_DEFAULT_LEVELS 1
-+
- static void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
- const char *fmt, ...)
+@@ -24,6 +24,7 @@
+ #include <linux/msi.h>
+ #include <linux/memblock.h>
+ #include <linux/iommu.h>
++#include <linux/sizes.h>
+
+ #include <asm/sections.h>
+ #include <asm/io.h>
+@@ -1846,6 +1847,7 @@ static struct iommu_table_ops pnv_ioda2_iommu_ops = {
+ #endif
+ .clear = pnv_ioda2_tce_free,
+ .get = pnv_tce_get,
++ .free = pnv_pci_free_table,
+ };
+
+ static void pnv_pci_ioda_setup_opal_tce_kill(struct pnv_phb *phb,
+@@ -1936,6 +1938,8 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
+ TCE_PCI_SWINV_PAIR);
+
+ tbl->it_ops = &pnv_ioda1_iommu_ops;
++ pe->table_group.tce32_start = tbl->it_offset << tbl->it_page_shift;
++ pe->table_group.tce32_size = tbl->it_size << tbl->it_page_shift;
+ iommu_init_table(tbl, phb->hose->node);
+
+ if (pe->flags & PNV_IODA_PE_DEV) {
+@@ -1961,7 +1965,7 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
+ }
+
+ static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
+- struct iommu_table *tbl)
++ int num, struct iommu_table *tbl)
{
-@@ -1331,16 +1333,79 @@ static void pnv_pci_ioda_setup_dma_pe(struct pnv_phb *phb,
- __free_pages(tce_mem, get_order(TCE32_TABLE_SIZE * segs));
- }
-
-+static void pnv_free_tce_table(unsigned long addr, unsigned size,
-+ unsigned level)
-+{
-+ addr &= ~(TCE_PCI_READ | TCE_PCI_WRITE);
-+
-+ if (level) {
-+ long i;
-+ u64 *tmp = (u64 *) addr;
-+
-+ for (i = 0; i < size; ++i) {
-+ unsigned long hpa = be64_to_cpu(tmp[i]);
-+
-+ if (!(hpa & (TCE_PCI_READ | TCE_PCI_WRITE)))
-+ continue;
-+
-+ pnv_free_tce_table((unsigned long) __va(hpa),
-+ size, level - 1);
-+ }
-+ }
-+
-+ free_pages(addr, get_order(size << 3));
-+}
-+
-+static __be64 *pnv_alloc_tce_table(int nid,
-+ unsigned shift, unsigned levels, unsigned long *left)
-+{
-+ struct page *tce_mem = NULL;
-+ __be64 *addr, *tmp;
-+ unsigned order = max_t(unsigned, shift, PAGE_SHIFT) - PAGE_SHIFT;
-+ unsigned long chunk = 1UL << shift, i;
-+
-+ tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
-+ if (!tce_mem) {
-+ pr_err("Failed to allocate a TCE memory\n");
-+ return NULL;
-+ }
-+
-+ if (!*left)
-+ return NULL;
-+
-+ addr = page_address(tce_mem);
-+ memset(addr, 0, chunk);
-+
-+ --levels;
-+ if (!levels) {
-+ /* This is last level, actual TCEs */
-+ *left -= min(*left, chunk);
-+ return addr;
-+ }
-+
-+ for (i = 0; i < (chunk >> 3); ++i) {
-+ /* We allocated required TCEs, mark the rest "page fault" */
-+ if (!*left) {
-+ addr[i] = cpu_to_be64(0);
-+ continue;
-+ }
-+
-+ tmp = pnv_alloc_tce_table(nid, shift, levels, left);
-+ addr[i] = cpu_to_be64(__pa(tmp) |
-+ TCE_PCI_READ | TCE_PCI_WRITE);
-+ }
-+
-+ return addr;
-+}
-+
- static long pnv_pci_ioda2_create_table(struct pnv_ioda_pe *pe,
-- __u32 page_shift, __u64 window_size,
-+ __u32 page_shift, __u64 window_size, __u32 levels,
- struct iommu_table *tbl)
- {
- int nid = pe->phb->hose->node;
-- struct page *tce_mem = NULL;
- void *addr;
-- unsigned long tce_table_size;
-- int64_t rc;
-- unsigned order;
-+ unsigned long tce_table_size, left;
-+ unsigned shift;
-
- if (!(table_group->pgsizes & (1ULL << page_shift)))
- return -EINVAL;
-@@ -1348,20 +1413,27 @@ static long pnv_pci_ioda2_create_table(struct pnv_ioda_pe *pe,
- if ((window_size > memory_hotplug_max()) || !is_power_of_2(window_size))
- return -EINVAL;
-
-+ if (!levels || (levels > POWERNV_IOMMU_MAX_LEVELS))
-+ return -EINVAL;
-+
- tce_table_size = (window_size >> page_shift) * 8;
- tce_table_size = max(0x1000UL, tce_table_size);
-
- /* Allocate TCE table */
-- order = get_order(tce_table_size);
-+#define ROUND_UP(x, n) (((x) + (n) - 1u) & ~((n) - 1u))
-+ shift = ROUND_UP(ilog2(window_size) - page_shift, levels) / levels;
-+ shift += 3;
-+ shift = max_t(unsigned, shift, IOMMU_PAGE_SHIFT_4K);
-+ pr_info("Creating TCE table %08llx, %d levels, TCE table size = %lx\n",
-+ window_size, levels, 1UL << shift);
-
-- tce_mem = alloc_pages_node(nid, GFP_KERNEL, order);
-- if (!tce_mem) {
-- pr_err("Failed to allocate a TCE memory, order=%d\n", order);
-- rc = -ENOMEM;
-- goto fail;
-- }
-- addr = page_address(tce_mem);
-- memset(addr, 0, tce_table_size);
-+ tbl->it_level_size = 1ULL << (shift - 3);
-+ left = tce_table_size;
-+ addr = pnv_alloc_tce_table(nid, shift, levels, &left);
-+ if (!addr)
-+ return -ENOMEM;
-+
-+ tbl->it_indirect_levels = levels - 1;
-
- /* Setup linux iommu table */
- pnv_pci_setup_iommu_table(tbl, addr, tce_table_size, 0,
-@@ -1370,20 +1442,18 @@ static long pnv_pci_ioda2_create_table(struct pnv_ioda_pe *pe,
- tbl->it_ops = &pnv_ioda2_iommu_ops;
-
- return 0;
--fail:
-- if (tce_mem)
-- __free_pages(tce_mem, get_order(tce_table_size));
--
-- return rc;
- }
-
- static void pnv_pci_free_table(struct iommu_table *tbl)
- {
-+ const unsigned size = tbl->it_indirect_levels ?
-+ tbl->it_level_size : tbl->it_size;
-+
- if (!tbl->it_size)
- return;
-
-- free_pages(tbl->it_base, get_order(tbl->it_size << 3));
-- memset(tbl, 0, sizeof(struct iommu_table));
-+ pnv_free_tce_table(tbl->it_base, size, tbl->it_indirect_levels);
-+ iommu_reset_table(tbl, "ioda2");
- }
-
- static long pnv_pci_ioda2_set_window(struct pnv_ioda_pe *pe,
-@@ -1392,12 +1462,15 @@ static long pnv_pci_ioda2_set_window(struct pnv_ioda_pe *pe,
- struct pnv_phb *phb = pe->phb;
- const __be64 *swinvp;
- int64_t rc;
-+ const unsigned size = tbl->it_indirect_levels ?
-+ tbl->it_level_size : tbl->it_size;
+ struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
+ table_group);
+@@ -1972,9 +1976,10 @@ static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
const __u64 start_addr = tbl->it_offset << tbl->it_page_shift;
const __u64 win_size = tbl->it_size << tbl->it_page_shift;
-- pe_info(pe, "Setting up window at %llx..%llx pagesize=0x%x tablesize=0x%lx\n",
-+ pe_info(pe, "Setting up window at %llx..%llx pagesize=0x%x tablesize=0x%lx levels=%d levelsize=%x\n",
+- pe_info(pe, "Setting up window at %llx..%llx "
++ pe_info(pe, "Setting up window#%d at %llx..%llx "
+ "pgsize=0x%x tablesize=0x%lx "
+ "levels=%d levelsize=%x\n",
++ num,
start_addr, start_addr + win_size - 1,
-- 1UL << tbl->it_page_shift, tbl->it_size << 3);
-+ 1UL << tbl->it_page_shift, tbl->it_size,
-+ tbl->it_indirect_levels + 1, tbl->it_level_size);
-
- pe->table_group.tables[0] = *tbl;
- tbl = &pe->table_group.tables[0];
-@@ -1408,8 +1481,9 @@ static long pnv_pci_ioda2_set_window(struct pnv_ioda_pe *pe,
- * shifted by 1 bit for 32-bits DMA space.
+ 1UL << tbl->it_page_shift, tbl->it_size << 3,
+ tbl->it_indirect_levels + 1, tbl->it_level_size << 3);
+@@ -1987,7 +1992,7 @@ static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
*/
- rc = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
-- pe->pe_number << 1, 1, __pa(tbl->it_base),
-- tbl->it_size << 3, 1ULL << tbl->it_page_shift);
-+ pe->pe_number << 1, tbl->it_indirect_levels + 1,
-+ __pa(tbl->it_base),
-+ size << 3, 1ULL << tbl->it_page_shift);
- if (rc) {
- pe_err(pe, "Failed to configure TCE table, err %ld\n", rc);
- goto fail;
-@@ -1523,7 +1597,8 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
- end);
-
- rc = pnv_pci_ioda2_create_table(pe, IOMMU_PAGE_SHIFT_4K,
-- phb->ioda.m32_pci_base, tbl);
-+ phb->ioda.m32_pci_base,
-+ POWERNV_IOMMU_DEFAULT_LEVELS, tbl);
+ rc = opal_pci_map_pe_dma_window(phb->opal_id,
+ pe->pe_number,
+- pe->pe_number << 1,
++ (pe->pe_number << 1) + num,
+ tbl->it_indirect_levels + 1,
+ __pa(tbl->it_base),
+ size << 3,
+@@ -2000,7 +2005,7 @@ static long pnv_pci_ioda2_set_window(struct iommu_table_group *table_group,
+ pnv_pci_ioda2_tvt_invalidate(pe);
+
+ /* Store fully initialized *tbl (may be external) in PE */
+- pe->table_group.tables[0] = *tbl;
++ pe->table_group.tables[num] = *tbl;
+
+ return 0;
+ fail:
+@@ -2061,6 +2066,53 @@ static void pnv_pci_ioda2_setup_bypass_pe(struct pnv_phb *phb,
+ }
+
+ #ifdef CONFIG_IOMMU_API
++static long pnv_pci_ioda2_create_table(struct iommu_table_group *table_group,
++ int num, __u32 page_shift, __u64 window_size, __u32 levels,
++ struct iommu_table *tbl)
++{
++ struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
++ table_group);
++ int nid = pe->phb->hose->node;
++ __u64 bus_offset = num ? pe->tce_bypass_base : 0;
++ long ret;
++
++ ret = pnv_pci_create_table(table_group, nid, bus_offset, page_shift,
++ window_size, levels, tbl);
++ if (ret)
++ return ret;
++
++ tbl->it_ops = &pnv_ioda2_iommu_ops;
++ if (pe->tce_inval_reg)
++ tbl->it_type |= (TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE);
++
++ return 0;
++}
++
++static long pnv_pci_ioda2_unset_window(struct iommu_table_group *table_group,
++ int num)
++{
++ struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
++ table_group);
++ struct pnv_phb *phb = pe->phb;
++ struct iommu_table *tbl = &pe->table_group.tables[num];
++ long ret;
++
++ pe_info(pe, "Removing DMA window #%d\n", num);
++
++ ret = opal_pci_map_pe_dma_window(phb->opal_id, pe->pe_number,
++ (pe->pe_number << 1) + num,
++ 0/* levels */, 0/* table address */,
++ 0/* table size */, 0/* page size */);
++ if (ret)
++ pe_warn(pe, "Unmapping failed, ret = %ld\n", ret);
++ else
++ pnv_pci_ioda2_tvt_invalidate(pe);
++
++ memset(tbl, 0, sizeof(*tbl));
++
++ return ret;
++}
++
+ static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
+ {
+ struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
+@@ -2080,6 +2132,9 @@ static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
+ }
+
+ static struct iommu_table_group_ops pnv_pci_ioda2_ops = {
++ .create_table = pnv_pci_ioda2_create_table,
++ .set_window = pnv_pci_ioda2_set_window,
++ .unset_window = pnv_pci_ioda2_unset_window,
+ .take_ownership = pnv_ioda2_take_ownership,
+ .release_ownership = pnv_ioda2_release_ownership,
+ };
+@@ -2102,8 +2157,16 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
+ pe_info(pe, "Setting up 32-bit TCE table at 0..%08x\n",
+ phb->ioda.m32_pci_base);
+
++ pe->table_group.tce32_start = 0;
++ pe->table_group.tce32_size = phb->ioda.m32_pci_base;
++ pe->table_group.max_dynamic_windows_supported =
++ IOMMU_TABLE_GROUP_MAX_TABLES;
++ pe->table_group.max_levels = POWERNV_IOMMU_MAX_LEVELS;
++ pe->table_group.pgsizes = SZ_4K | SZ_64K | SZ_16M;
++
+ rc = pnv_pci_create_table(&pe->table_group, pe->phb->hose->node,
+- 0, IOMMU_PAGE_SHIFT_4K, phb->ioda.m32_pci_base,
++ pe->table_group.tce32_start, IOMMU_PAGE_SHIFT_4K,
++ pe->table_group.tce32_size,
+ POWERNV_IOMMU_DEFAULT_LEVELS, tbl);
if (rc) {
pe_err(pe, "Failed to create 32-bit TCE table, err %ld", rc);
- return;
-diff --git a/arch/powerpc/platforms/powernv/pci.c b/arch/powerpc/platforms/powernv/pci.c
-index c5e1f05..9b4a0cf 100644
---- a/arch/powerpc/platforms/powernv/pci.c
-+++ b/arch/powerpc/platforms/powernv/pci.c
-@@ -592,6 +592,25 @@ struct pci_ops pnv_pci_ops = {
- static __be64 *pnv_tce(struct iommu_table *tbl, long index)
- {
- __be64 *tmp = ((__be64 *)tbl->it_base);
-+ int level = tbl->it_indirect_levels;
-+ const long shift = ilog2(tbl->it_level_size);
-+ unsigned long mask = (tbl->it_level_size - 1) << (level * shift);
-+
-+ if (index >= tbl->it_size)
-+ return NULL;
-+
-+ while (level) {
-+ int n = (index & mask) >> (level * shift);
-+ unsigned long tce = be64_to_cpu(tmp[n]);
-+
-+ if (!(tce & (TCE_PCI_READ | TCE_PCI_WRITE)))
-+ return NULL;
-+
-+ tmp = __va(tce & ~(TCE_PCI_READ | TCE_PCI_WRITE));
-+ index &= ~mask;
-+ mask >>= shift;
-+ --level;
-+ }
-
- return tmp + index;
- }
+@@ -2119,7 +2182,7 @@ static void pnv_pci_ioda2_setup_dma_pe(struct pnv_phb *phb,
+ pe->table_group.ops = &pnv_pci_ioda2_ops;
+ #endif
+
+- rc = pnv_pci_ioda2_set_window(&pe->table_group, tbl);
++ rc = pnv_pci_ioda2_set_window(&pe->table_group, 0, tbl);
+ if (rc) {
+ pe_err(pe, "Failed to configure 32-bit TCE table,"
+ " err %ld\n", rc);
+diff --git a/arch/powerpc/platforms/powernv/pci-p5ioc2.c b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
+index 7a6fd92..d9de4c7 100644
+--- a/arch/powerpc/platforms/powernv/pci-p5ioc2.c
++++ b/arch/powerpc/platforms/powernv/pci-p5ioc2.c
+@@ -116,6 +116,8 @@ static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np, u64 hub_id,
+ u64 phb_id;
+ int64_t rc;
+ static int primary = 1;
++ struct iommu_table_group *table_group;
++ struct iommu_table *tbl;
+
+ pr_info(" Initializing p5ioc2 PHB %s\n", np->full_name);
+
+@@ -181,14 +183,16 @@ static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np, u64 hub_id,
+ pnv_pci_init_p5ioc2_msis(phb);
+
+ /* Setup iommu */
+- phb->p5ioc2.table_group.tables[0].it_table_group =
+- &phb->p5ioc2.table_group;
++ table_group = &phb->p5ioc2.table_group;
++ tbl = &phb->p5ioc2.table_group.tables[0];
++ tbl->it_table_group = table_group;
+
+ /* Setup TCEs */
+ phb->dma_dev_setup = pnv_pci_p5ioc2_dma_dev_setup;
+- pnv_pci_setup_iommu_table(&phb->p5ioc2.table_group.tables[0],
+- tce_mem, tce_size, 0,
++ pnv_pci_setup_iommu_table(tbl, tce_mem, tce_size, 0,
+ IOMMU_PAGE_SHIFT_4K);
++ table_group->tce32_start = tbl->it_offset << tbl->it_page_shift;
++ table_group->tce32_size = tbl->it_size << tbl->it_page_shift;
+ }
+
+ void __init pnv_pci_init_p5ioc2_hub(struct device_node *np)
--
2.0.0