--- vrfc
+++ v3
@@ -3,18 +3,32 @@
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
---
+Changelog[v3]
+ - Rename winctx->pid to winctx->pidr to reflect that its a value
+ from the PID register (SPRN_PID), not the linux process id.
+ - Make it easier to split header into kernel/user parts
+ - To keep user interface simple, use macros rather than enum for
+ the threshold-control modes.
+ - Add a pid field to struct vas_window - needed for user space
+ send windows.
+
+Changelog[v2]
+ - Add an overview of VAS in vas-internal.h
+ - Get window context parameters from device tree and drop
+ unnecessary macros.
+---
MAINTAINERS | 6 +
- arch/powerpc/include/asm/vas.h | 40 +++++
- drivers/misc/vas/vas-internal.h | 365 ++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 411 insertions(+)
+ arch/powerpc/include/asm/vas.h | 43 +++++
+ drivers/misc/vas/vas-internal.h | 392 ++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 441 insertions(+)
create mode 100644 arch/powerpc/include/asm/vas.h
create mode 100644 drivers/misc/vas/vas-internal.h
diff --git a/MAINTAINERS b/MAINTAINERS
-index 644ff65..3ef8d4d 100644
+index c265a5f..2a910c9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
-@@ -12410,6 +12410,12 @@ S: Maintained
+@@ -13213,6 +13213,12 @@ S: Maintained
F: Documentation/fb/uvesafb.txt
F: drivers/video/fbdev/uvesafb.*
@@ -29,10 +43,10 @@
L: linux-mtd@lists.infradead.org
diff --git a/arch/powerpc/include/asm/vas.h b/arch/powerpc/include/asm/vas.h
new file mode 100644
-index 0000000..1c10437
+index 0000000..6d35ce6
--- /dev/null
+++ b/arch/powerpc/include/asm/vas.h
-@@ -0,0 +1,40 @@
+@@ -0,0 +1,43 @@
+/*
+ * Copyright 2016 IBM Corp.
+ *
@@ -44,6 +58,20 @@
+
+#ifndef VAS_H
+#define VAS_H
++
++/*
++ * Threshold Control Mode: Have paste operation fail if the number of
++ * requests in receive FIFO exceeds a threshold.
++ *
++ * NOTE: No special error code yet if paste is rejected because of these
++ * limits. So users can't distinguish between this and other errors.
++ */
++#define VAS_THRESH_DISABLED 0
++#define VAS_THRESH_FIFO_GT_HALF_FULL 1
++#define VAS_THRESH_FIFO_GT_QTR_FULL 2
++#define VAS_THRESH_FIFO_GT_EIGHTH_FULL 3
++
++#ifdef __KERNEL__
+
+#define VAS_RX_FIFO_SIZE_MAX (8 << 20) /* 8MB */
+/*
@@ -58,27 +86,16 @@
+ VAS_COP_TYPE_MAX,
+};
+
-+/*
-+ * Threshold Control Mode: Have paste operation fail if the number of
-+ * requests in receive FIFO exceeds a threshold.
-+ *
-+ * NOTE: No special error code yet if paste is rejected because of these
-+ * limits. So users can't distinguish between this and other errors.
-+ */
-+enum vas_thresh_ctl {
-+ VAS_THRESH_DISABLED,
-+ VAS_THRESH_FIFO_GT_HALF_FULL,
-+ VAS_THRESH_FIFO_GT_QTR_FULL,
-+ VAS_THRESH_FIFO_GT_EIGHTH_FULL,
-+};
++
++#endif /* __KERNEL__ */
+
+#endif
diff --git a/drivers/misc/vas/vas-internal.h b/drivers/misc/vas/vas-internal.h
new file mode 100644
-index 0000000..f91fd66
+index 0000000..ce48f14
--- /dev/null
+++ b/drivers/misc/vas/vas-internal.h
-@@ -0,0 +1,365 @@
+@@ -0,0 +1,392 @@
+/*
+ * Copyright 2016 IBM Corp.
+ *
@@ -93,75 +110,6 @@
+#include <linux/atomic.h>
+#include <linux/idr.h>
+#include <asm/vas.h>
-+
-+/*
-+ * HVWC and UWC BAR.
-+ *
-+ * A Power node can have (upto?) 8 Power chips.
-+ *
-+ * There is one instance of VAS in each Power chip. Each instance of VAS
-+ * has 64K windows, which can be used to send/receive messages from
-+ * software threads and coprocessors.
-+ *
-+ * Each window is described by two types of window contexts:
-+ *
-+ * Hypervisor Window Context (HVWC) of size VAS_HVWC_SIZE bytes
-+ * OS/User Window Context (UWC) of size VAS_UWC_SIZE bytes.
-+ *
-+ * A window context can be viewed as a set of 64-bit registers. The settings
-+ * of these registers control/determine the behavior of the VAS hardware
-+ * when messages are sent/received through the window.
-+ *
-+ * Each Power chip i.e each instance of VAS, is assigned two distinct ranges
-+ * (one for each type of context) of Power-bus addresses (aka Base Address
-+ * Region or BAR) which can be used to access the window contexts in that
-+ * instance of VAS.
-+ *
-+ * From the Power9 MMIO Ranges Spreadsheet:
-+ *
-+ * The HVWC BAR is of size 0x40000000000 and for chip 0, the HVWC BAR begins
-+ * at 0x6019000000000ULL, for chip 1 at 0x0006059000000000 etc.
-+ *
-+ * i.e the HVWC for each of the 64K windows on chip 0 can be accessed at the
-+ * address 0x6019000000000ULL, and HVWC for the 64K windows on chip 1 can be
-+ * accessed at the address 0x0006059000000000 and so on.
-+ *
-+ * Similarly, the UWC BAR is also of size 0x40000000000 and for chip 0,
-+ * begins at 0x0006019100000000, for chip 1 at 0x0006059100000000 etc.
-+ *
-+ * Following macros describe the HVWC and UWC BARs for chip 0. The BARs for
-+ * the other chips are computed in get_hvwc_mmio_bar() / get_uwc_mmio_bar().
-+ */
-+#define VAS_HVWC_MMIO_BAR_BASE 0x0006019100000000ULL
-+#define VAS_HVWC_MMIO_BAR_SIZE 0x40000000000
-+
-+#define VAS_UWC_MMIO_BAR_BASE 0x0006019000000000ULL
-+#define VAS_UWC_MMIO_BAR_SIZE 0x40000000000
-+
-+/*
-+ * Hypervisor and OS/USer Window Context sizes
-+ */
-+#define VAS_HVWC_SIZE 512
-+#define VAS_UWC_SIZE PAGE_SIZE
-+
-+/*
-+ * TODO: Get nodes and chip info from device tree.
-+ */
-+#define VAS_MAX_NODES 1
-+#define VAS_MAX_CHIPS_PER_NODE 1
-+
-+/* Initial per-process credits. We may need to tweak these later */
-+#define VAS_WCREDS_MIN 16
-+#define VAS_WCREDS_MAX 64
-+#define VAS_WCREDS_DEFAULT 64
-+
-+/*
-+ * TODO:
-+ * - Hardcoded for Power9 but should get from device tree (must
-+ * sync with Skiboot!)
-+ * - Increase number of windows to 64K after initial development
-+ */
-+#define VAS_MAX_WINDOWS_PER_CHIP 64
+
+#ifdef CONFIG_PPC_4K_PAGES
+# error "TODO: Compute RMA/Paste-address for 4K pages."
@@ -172,15 +120,103 @@
+#endif
+
+/*
-+ * TODO: Copied from nx-842.h. Move to a common header
-+ */
-+/* Get/Set bit fields */
-+#define MASK_LSH(m) (__builtin_ffsl(m) - 1)
-+
-+/* Sigh. nx-842 and skiboot have the parameters in opposite order */
-+#define GET_FIELD(m, v) (((v) & (m)) >> MASK_LSH(m))
-+#define SET_FIELD(m, v, val) \
-+ (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_LSH(m)) & (m)))
++ * Overview of Virtual Accelerator Switchboard (VAS).
++ *
++ * VAS is a hardware "switchboard" that allows senders and receivers to
++ * exchange messages with _minimal_ kernel involvment. The receivers are
++ * typically NX coprocessor engines that perform compression or encryption
++ * in hardware, but receivers can also be other software threads.
++ *
++ * Senders are user/kernel threads that submit compression/encryption or
++ * other requests to the receivers. Senders must format their messages as
++ * Coprocessor Request Blocks (CRB)s and submit them using the instructions
++ * "copy" and "paste" which were introduced in Power9.
++ *
++ * A Power node can have (upto?) 8 Power chips. There is one instance of
++ * VAS in each Power9 chip. Each instance of VAS has 64K windows or ports,
++ * Senders and receivers must each connect to a separate window before they
++ * can exchange messages through the switchboard.
++ *
++ * Each window is described by two types of window contexts:
++ *
++ * Hypervisor Window Context (HVWC) of size VAS_HVWC_SIZE bytes
++ *
++ * OS/User Window Context (UWC) of size VAS_UWC_SIZE bytes.
++ *
++ * A window context can be viewed as a set of 64-bit registers. The settings
++ * in these registers configure/control/determine the behavior of the VAS
++ * hardware when messages are sent/received through the window. The registers
++ * in the HVWC are configured by the kernel while the registers in the UWC can
++ * be configured by the kernel or by the user space application that is using
++ * the window.
++ *
++ * The HVWCs for all windows on a specific instance of VAS are in a contiguous
++ * range of hardware addresses or Base address region (BAR) referred to as the
++ * HVWC BAR for the instance. Similarly the UWCs for all windows on an instance
++ * are referred to as the UWC BAR for the instance. The two BARs for each
++ * instance are defined Power9 MMIO Ranges spreadsheet and available to the
++ * kernel the device tree as follows:
++ *
++ * /proc/device-tree/xscom@.../vas@.../hvwc-bar-start
++ * /proc/device-tree/xscom@.../vas@.../hvwc-bar-size
++ * /proc/device-tree/xscom@.../vas@.../uwc-bar-start
++ * /proc/device-tree/xscom@.../vas@.../uwc-bar-size
++ *
++ * The kernel maps these two hardware address regions into the kernel address
++ * space (hvwc_map and uwc_map) and accesses the window contexts of a specific
++ * window using:
++ *
++ * hvwc = hvwc_map + winid * VAS_HVWC_SIZE.
++ * uwc = uwc_map + winid * VAS_UWC_SIZE.
++ *
++ * where winid is the window index (0..64K).
++ *
++ * Note that the window contexts are used to "configure" the windows. In
++ * addition to this configuration address, each _send_ window also has a
++ * unique hardware address, referred to as the "paste-address" to which the
++ * sender must "paste" the message (CRB) they wish to submit. This hardware
++ * paste address for window can be computed from the following nodes in the
++ * device tree:
++ *
++ * /proc/device-tree/xscom@.../vas@.../window-base
++ * /proc/device-tree/xscom@.../vas@.../window-shift
++ *
++ * Thus if 'base' and 'shift' give the values of the above nodes for a given
++ * instance of VAS, the paste address for a window can be computed using:
++ *
++ * paste_addr = base + ((winid << shift))
++ *
++ * The kernel maps this hardware address into the sender's address space after
++ * which they can use the 'paste' instruction to send a message (submit a
++ * request).
++ *
++ * NOTE: In the initial version, senders can only in-kernel drivers/threads.
++ * Support for user space threads will be added in follow-on patches.
++ *
++ * TODO: Do we need to map the UWC into user address space so they can return
++ * credits? Its NA for NX but may be needed for other receive windows.
++ *
++ */
++
++/* TODO: Increase to 64K after initial development */
++#define VAS_MAX_WINDOWS_PER_CHIP 64
++
++/*
++ * Hypervisor and OS/USer Window Context sizes
++ */
++#define VAS_HVWC_SIZE 512
++#define VAS_UWC_SIZE PAGE_SIZE
++
++/*
++ * Initial per-process credits.
++ * Max send window credits: 4K-1 (12-bits in VAS_TX_WCRED)
++ * Max receive window credits: 64K-1 (16 bits in VAS_LRX_WCRED)
++ *
++ * TODO: Needs tuning for per-process credits
++ */
++#define VAS_WCREDS_MIN 16
++#define VAS_WCREDS_MAX ((64 << 10) - 1)
++#define VAS_WCREDS_DEFAULT (1 << 10)
+
+/*
+ * VAS Window Context Register Offsets and bitmasks.
@@ -276,8 +312,8 @@
+#define VAS_WINCTL_PIN PPC_BIT(2)
+#define VAS_WINCTL_TX_WCRED_MODE PPC_BIT(3)
+#define VAS_WINCTL_RX_WCRED_MODE PPC_BIT(4)
-+#define VAS_WINCTL_TXWIN_ORD_MODE PPC_BIT(5)
-+#define VAS_WINCTL_RXWIN_ORD_MODE PPC_BIT(6)
++#define VAS_WINCTL_TX_WORD_MODE PPC_BIT(5)
++#define VAS_WINCTL_RX_WORD_MODE PPC_BIT(6)
+#define VAS_WINCTL_RSVD_TXBUF PPC_BIT(7)
+#define VAS_WINCTL_THRESH_CTL PPC_BITMASK(8, 9)
+#define VAS_WINCTL_FAULT_WIN PPC_BIT(10)
@@ -359,14 +395,20 @@
+};
+
+/*
-+ * One per instance of VAS (i.e one per chip).
-+ * Each instance will have a separate set of receive windows, one per
-+ * coprocessor type.
++ * One per instance of VAS. Each instance will have a separate set of
++ * receive windows, one per coprocessor type.
+ */
+struct vas_instance {
-+ int node;
-+ int chip;
++ int vas_id;
+ struct ida ida;
++
++ u64 hvwc_bar_start;
++ u64 hvwc_bar_len;
++ u64 uwc_bar_start;
++ u64 uwc_bar_len;
++ u64 win_base_addr;
++ u64 win_id_shift;
++
+ struct mutex mutex;
+ struct vas_window *rxwin[VAS_COP_TYPE_MAX];
+};
@@ -378,12 +420,13 @@
+ /* Fields common to Send and receive windows */
+ struct vas_instance *vinst;
+ int winid;
-+ bool txwin; /* True if send window */
++ bool tx_win; /* True if send window */
+ bool nx_win; /* True if NX window */
+ void *hvwc_map; /* HV window context */
+ void *uwc_map; /* OS/User window context */
+
+ /* Fields applicable only to send windows */
++ pid_t pid; /* linux process id of sender, if applicable */
+ void *paste_kaddr;
+ char *paste_addr_name;
+ struct vas_window *rxwin;
@@ -417,8 +460,8 @@
+ bool rej_no_credit;
+ bool tx_wcred_mode;
+ bool rx_wcred_mode;
-+ bool tx_win_ord_mode;
-+ bool rx_win_ord_mode;
++ bool tx_word_mode;
++ bool rx_word_mode;
+ bool data_stamp;
+ bool xtra_write;
+ bool notify_disable;
@@ -427,17 +470,18 @@
+ bool notify_os_intr_reg;
+
+ int lpid;
-+ int pid;
++ int pidr; /* value from SPRN_PID, not linux pid */
+ int lnotify_lpid;
+ int lnotify_pid;
+ int lnotify_tid;
+ int pswid;
+ int rx_win_id;
+ int fault_win_id;
++ int tc_mode;
++
+ uint64_t irq_port;
+
+ enum vas_dma_type dma_type;
-+ enum vas_thresh_ctl tc_mode;
+ enum vas_notify_scope min_scope;
+ enum vas_notify_scope max_scope;
+ enum vas_notify_after_count notify_after_count;
@@ -445,4 +489,4 @@
+
+#endif
--
-1.8.3.1
+2.7.4