--- v3
+++ v6
@@ -1,101 +1,199 @@
-_PAGE_PSIZE macro is never used outside the place it is defined
-and is used only on 8xx and e500.
+From: Michael Ellerman <mpe@ellerman.id.au>
-Remove indirection, remove it and use its content directly.
+All 64-bit Book3E have MMU_FTR_TYPE_FSL_E, since A2 was removed, so
+remove checks for it in 64-bit only code.
+Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
-Reviewed-by: Oscar Salvador <osalvador@suse.de>
---
- arch/powerpc/include/asm/nohash/32/pte-40x.h | 3 ---
- arch/powerpc/include/asm/nohash/32/pte-44x.h | 3 ---
- arch/powerpc/include/asm/nohash/32/pte-85xx.h | 3 ---
- arch/powerpc/include/asm/nohash/32/pte-8xx.h | 5 ++---
- arch/powerpc/include/asm/nohash/pte-e500.h | 4 +---
- 5 files changed, 3 insertions(+), 15 deletions(-)
+ arch/powerpc/kernel/setup_64.c | 6 +-
+ arch/powerpc/mm/nohash/tlb_64e.c | 97 ++++++++++++--------------------
+ 2 files changed, 38 insertions(+), 65 deletions(-)
-diff --git a/arch/powerpc/include/asm/nohash/32/pte-40x.h b/arch/powerpc/include/asm/nohash/32/pte-40x.h
-index d759cfd74754..52ed58516fa4 100644
---- a/arch/powerpc/include/asm/nohash/32/pte-40x.h
-+++ b/arch/powerpc/include/asm/nohash/32/pte-40x.h
-@@ -49,9 +49,6 @@
- #define _PAGE_EXEC 0x200 /* hardware: EX permission */
- #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
+diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
+index ae36a129789f..22f83fbbc762 100644
+--- a/arch/powerpc/kernel/setup_64.c
++++ b/arch/powerpc/kernel/setup_64.c
+@@ -696,11 +696,7 @@ __init u64 ppc64_bolted_size(void)
+ {
+ #ifdef CONFIG_PPC_BOOK3E_64
+ /* Freescale BookE bolts the entire linear mapping */
+- /* XXX: BookE ppc64_rma_limit setup seems to disagree? */
+- if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E))
+- return linear_map_top;
+- /* Other BookE, we assume the first GB is bolted */
+- return 1ul << 30;
++ return linear_map_top;
+ #else
+ /* BookS radix, does not take faults on linear mapping */
+ if (early_radix_enabled())
+diff --git a/arch/powerpc/mm/nohash/tlb_64e.c b/arch/powerpc/mm/nohash/tlb_64e.c
+index 9db85ee9ba5b..21c4b2442fcf 100644
+--- a/arch/powerpc/mm/nohash/tlb_64e.c
++++ b/arch/powerpc/mm/nohash/tlb_64e.c
+@@ -86,9 +86,8 @@ static void __init setup_page_sizes(void)
+ int psize;
--/* No page size encoding in the linux PTE */
--#define _PAGE_PSIZE 0
--
- /* cache related flags non existing on 40x */
- #define _PAGE_COHERENT 0
+ unsigned int mmucfg = mfspr(SPRN_MMUCFG);
+- int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);
-diff --git a/arch/powerpc/include/asm/nohash/32/pte-44x.h b/arch/powerpc/include/asm/nohash/32/pte-44x.h
-index 851813725237..da0469928273 100644
---- a/arch/powerpc/include/asm/nohash/32/pte-44x.h
-+++ b/arch/powerpc/include/asm/nohash/32/pte-44x.h
-@@ -75,9 +75,6 @@
- #define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
- #define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
+- if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
++ if ((mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
+ unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
+ unsigned int min_pg, max_pg;
--/* No page size encoding in the linux PTE */
--#define _PAGE_PSIZE 0
--
- /* TODO: Add large page lowmem mapping support */
- #define _PMD_PRESENT 0
- #define _PMD_PRESENT_MASK (PAGE_MASK)
-diff --git a/arch/powerpc/include/asm/nohash/32/pte-85xx.h b/arch/powerpc/include/asm/nohash/32/pte-85xx.h
-index 653a342d3b25..14d64b4f3f14 100644
---- a/arch/powerpc/include/asm/nohash/32/pte-85xx.h
-+++ b/arch/powerpc/include/asm/nohash/32/pte-85xx.h
-@@ -31,9 +31,6 @@
- #define _PAGE_WRITETHRU 0x00400 /* H: W bit */
- #define _PAGE_SPECIAL 0x00800 /* S: Special page */
+@@ -115,7 +114,7 @@ static void __init setup_page_sizes(void)
+ goto out;
+ }
--/* No page size encoding in the linux PTE */
--#define _PAGE_PSIZE 0
--
- #define _PMD_PRESENT 0
- #define _PMD_PRESENT_MASK (PAGE_MASK)
- #define _PMD_BAD (~PAGE_MASK)
-diff --git a/arch/powerpc/include/asm/nohash/32/pte-8xx.h b/arch/powerpc/include/asm/nohash/32/pte-8xx.h
-index 137dc3c84e45..625c31d6ce5c 100644
---- a/arch/powerpc/include/asm/nohash/32/pte-8xx.h
-+++ b/arch/powerpc/include/asm/nohash/32/pte-8xx.h
-@@ -74,12 +74,11 @@
- #define _PTE_NONE_MASK 0
+- if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
++ if ((mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
+ u32 tlb1cfg, tlb1ps;
- #ifdef CONFIG_PPC_16K_PAGES
--#define _PAGE_PSIZE _PAGE_SPS
-+#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_SPS)
- #else
--#define _PAGE_PSIZE 0
-+#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED)
+ tlb0cfg = mfspr(SPRN_TLB0CFG);
+@@ -213,26 +212,24 @@ static void early_init_this_mmu(void)
+ }
+ mtspr(SPRN_MAS4, mas4);
+
+- if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
+- unsigned int num_cams;
+- bool map = true;
++ unsigned int num_cams;
++ bool map = true;
+
+- /* use a quarter of the TLBCAM for bolted linear map */
+- num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
++ /* use a quarter of the TLBCAM for bolted linear map */
++ num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
+
+- /*
+- * Only do the mapping once per core, or else the
+- * transient mapping would cause problems.
+- */
++ /*
++ * Only do the mapping once per core, or else the
++ * transient mapping would cause problems.
++ */
+ #ifdef CONFIG_SMP
+- if (hweight32(get_tensr()) > 1)
+- map = false;
++ if (hweight32(get_tensr()) > 1)
++ map = false;
#endif
--#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
- #define _PAGE_BASE (_PAGE_BASE_NC)
+- if (map)
+- linear_map_top = map_mem_in_cams(linear_map_top,
+- num_cams, false, true);
+- }
++ if (map)
++ linear_map_top = map_mem_in_cams(linear_map_top,
++ num_cams, false, true);
- #include <asm/pgtable-masks.h>
-diff --git a/arch/powerpc/include/asm/nohash/pte-e500.h b/arch/powerpc/include/asm/nohash/pte-e500.h
-index f516f0b5b7a8..975facc7e38e 100644
---- a/arch/powerpc/include/asm/nohash/pte-e500.h
-+++ b/arch/powerpc/include/asm/nohash/pte-e500.h
-@@ -65,8 +65,6 @@
+ /* A sync won't hurt us after mucking around with
+ * the MMU configuration
+@@ -242,16 +239,10 @@ static void early_init_this_mmu(void)
- #define _PAGE_SPECIAL _PAGE_SW0
+ static void __init early_init_mmu_global(void)
+ {
+- /* XXX This should be decided at runtime based on supported
+- * page sizes in the TLB, but for now let's assume 16M is
+- * always there and a good fit (which it probably is)
+- *
++ /*
+ * Freescale booke only supports 4K pages in TLB0, so use that.
+ */
+- if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
+- mmu_vmemmap_psize = MMU_PAGE_4K;
+- else
+- mmu_vmemmap_psize = MMU_PAGE_16M;
++ mmu_vmemmap_psize = MMU_PAGE_4K;
--/* Base page size */
--#define _PAGE_PSIZE _PAGE_PSIZE_4K
- #define PTE_RPN_SHIFT (24)
+ /* XXX This code only checks for TLB 0 capabilities and doesn't
+ * check what page size combos are supported by the HW. It
+@@ -264,13 +255,10 @@ static void __init early_init_mmu_global(void)
+ /* Look for HW tablewalk support */
+ setup_mmu_htw();
- #define PTE_WIMGE_SHIFT (19)
-@@ -89,7 +87,7 @@
- * pages. We always set _PAGE_COHERENT when SMP is enabled or
- * the processor might need it for DMA coherency.
- */
--#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)
-+#define _PAGE_BASE_NC (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE_4K)
- #if defined(CONFIG_SMP)
- #define _PAGE_BASE (_PAGE_BASE_NC | _PAGE_COHERENT)
- #else
+- if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
+- if (book3e_htw_mode == PPC_HTW_NONE) {
+- extlb_level_exc = EX_TLB_SIZE;
+- patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
+- patch_exception(0x1e0,
+- exc_instruction_tlb_miss_bolted_book3e);
+- }
++ if (book3e_htw_mode == PPC_HTW_NONE) {
++ extlb_level_exc = EX_TLB_SIZE;
++ patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
++ patch_exception(0x1e0, exc_instruction_tlb_miss_bolted_book3e);
+ }
+
+ /* Set the global containing the top of the linear mapping
+@@ -283,16 +271,14 @@ static void __init early_init_mmu_global(void)
+
+ static void __init early_mmu_set_memory_limit(void)
+ {
+- if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
+- /*
+- * Limit memory so we dont have linear faults.
+- * Unlike memblock_set_current_limit, which limits
+- * memory available during early boot, this permanently
+- * reduces the memory available to Linux. We need to
+- * do this because highmem is not supported on 64-bit.
+- */
+- memblock_enforce_memory_limit(linear_map_top);
+- }
++ /*
++ * Limit memory so we dont have linear faults.
++ * Unlike memblock_set_current_limit, which limits
++ * memory available during early boot, this permanently
++ * reduces the memory available to Linux. We need to
++ * do this because highmem is not supported on 64-bit.
++ */
++ memblock_enforce_memory_limit(linear_map_top);
+
+ memblock_set_current_limit(linear_map_top);
+ }
+@@ -313,12 +299,8 @@ void early_init_mmu_secondary(void)
+ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
+ phys_addr_t first_memblock_size)
+ {
+- /* On non-FSL Embedded 64-bit, we adjust the RMA size to match
+- * the bolted TLB entry. We know for now that only 1G
+- * entries are supported though that may eventually
+- * change.
+- *
+- * on FSL Embedded 64-bit, usually all RAM is bolted, but with
++ /*
++ * On FSL Embedded 64-bit, usually all RAM is bolted, but with
+ * unusual memory sizes it's possible for some RAM to not be mapped
+ * (such RAM is not used at all by Linux, since we don't support
+ * highmem on 64-bit). We limit ppc64_rma_size to what would be
+@@ -330,19 +312,14 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
+ * We crop it to the size of the first MEMBLOCK to
+ * avoid going over total available memory just in case...
+ */
+- if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
+- unsigned long linear_sz;
+- unsigned int num_cams;
+-
+- /* use a quarter of the TLBCAM for bolted linear map */
+- num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
++ unsigned long linear_sz;
++ unsigned int num_cams;
+
+- linear_sz = map_mem_in_cams(first_memblock_size, num_cams,
+- true, true);
++ /* use a quarter of the TLBCAM for bolted linear map */
++ num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
+
+- ppc64_rma_size = min_t(u64, linear_sz, 0x40000000);
+- } else
+- ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
++ linear_sz = map_mem_in_cams(first_memblock_size, num_cams, true, true);
++ ppc64_rma_size = min_t(u64, linear_sz, 0x40000000);
+
+ /* Finally limit subsequent allocations */
+ memblock_set_current_limit(first_memblock_base + ppc64_rma_size);
--
2.44.0