--- v5
+++ v8
@@ -1,25 +1,29 @@
From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
-Rename the variable to better reflect the values. No functional change
-in this patch.
+This patch convert different functions to take virtual page number
+instead of virtual address. Virtual page number is virtual address
+shifted right by VPN_SHIFT (12) bits. This enable us to have an
+address range of upto 76 bits.
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
- arch/powerpc/include/asm/kvm_book3s.h | 2 +-
- arch/powerpc/include/asm/machdep.h | 6 +--
- arch/powerpc/include/asm/mmu-hash64.h | 23 ++++----
- arch/powerpc/include/asm/tlbflush.h | 4 +-
- arch/powerpc/kvm/book3s_32_mmu_host.c | 8 +--
- arch/powerpc/kvm/book3s_64_mmu_host.c | 17 +++---
- arch/powerpc/kvm/trace.h | 14 ++---
- arch/powerpc/mm/hash_native_64.c | 88 ++++++++++++++++---------------
- arch/powerpc/mm/hash_utils_64.c | 30 +++++------
- arch/powerpc/mm/hugetlbpage-hash64.c | 15 +++---
- arch/powerpc/mm/tlb_hash64.c | 11 ++--
- arch/powerpc/platforms/cell/beat_htab.c | 45 ++++++++--------
- arch/powerpc/platforms/ps3/htab.c | 22 ++++----
- arch/powerpc/platforms/pseries/lpar.c | 60 +++++++++++----------
- 14 files changed, 177 insertions(+), 168 deletions(-)
+ arch/powerpc/include/asm/kvm_book3s.h | 2 +-
+ arch/powerpc/include/asm/machdep.h | 6 +-
+ arch/powerpc/include/asm/mmu-hash64.h | 78 +++++++++++++++----
+ arch/powerpc/include/asm/pte-hash64-64k.h | 18 +++--
+ arch/powerpc/include/asm/tlbflush.h | 4 +-
+ arch/powerpc/kvm/book3s_32_mmu_host.c | 8 +-
+ arch/powerpc/kvm/book3s_64_mmu_host.c | 17 ++--
+ arch/powerpc/kvm/trace.h | 14 ++--
+ arch/powerpc/mm/hash_low_64.S | 97 ++++++++++++++---------
+ arch/powerpc/mm/hash_native_64.c | 121 +++++++++++++++++------------
+ arch/powerpc/mm/hash_utils_64.c | 30 +++----
+ arch/powerpc/mm/hugetlbpage-hash64.c | 15 ++--
+ arch/powerpc/mm/tlb_hash64.c | 11 +--
+ arch/powerpc/platforms/cell/beat_htab.c | 45 +++++------
+ arch/powerpc/platforms/ps3/htab.c | 22 +++---
+ arch/powerpc/platforms/pseries/lpar.c | 76 ++++++++----------
+ 16 files changed, 324 insertions(+), 240 deletions(-)
diff --git a/arch/powerpc/include/asm/kvm_book3s.h b/arch/powerpc/include/asm/kvm_book3s.h
index f0e0c6a..7aefdb3 100644
@@ -62,10 +66,62 @@
unsigned long rflags,
unsigned long vflags,
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
-index 60f8596..e5af632 100644
+index 1c65a59..6aeb498 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
-@@ -227,11 +227,11 @@ static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
+@@ -154,9 +154,25 @@ struct mmu_psize_def
+ #define MMU_SEGSIZE_256M 0
+ #define MMU_SEGSIZE_1T 1
+
++/*
++ * encode page number shift.
++ * in order to fit the 78 bit va in a 64 bit variable we shift the va by
++ * 12 bits. This enable us to address upto 76 bit va.
++ * For hpt hash from a va we can ignore the page size bits of va and for
++ * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
++ * we work in all cases including 4k page size.
++ */
++#define VPN_SHIFT 12
+
+ #ifndef __ASSEMBLY__
+
++static inline int segment_shift(int ssize)
++{
++ if (ssize == MMU_SEGSIZE_256M)
++ return SID_SHIFT;
++ return SID_SHIFT_1T;
++}
++
+ /*
+ * The current system page and segment sizes
+ */
+@@ -180,18 +196,39 @@ extern unsigned long tce_alloc_start, tce_alloc_end;
+ extern int mmu_ci_restrictions;
+
+ /*
++ * This computes the AVPN and B fields of the first dword of a HPTE,
++ * for use when we want to match an existing PTE. The bottom 7 bits
++ * of the returned value are zero.
++ */
++static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
++ int ssize)
++{
++ unsigned long v;
++ /*
++ * The AVA field omits the low-order 23 bits of the 78 bits VA.
++ * These bits are not needed in the PTE, because the
++ * low-order b of these bits are part of the byte offset
++ * into the virtual page and, if b < 23, the high-order
++ * 23-b of these bits are always used in selecting the
++ * PTEGs to be searched
++ */
++ v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
++ v <<= HPTE_V_AVPN_SHIFT;
++ v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
++ return v;
++}
++
++/*
* This function sets the AVPN and L fields of the HPTE appropriately
* for the page size
*/
@@ -75,23 +131,37 @@
+ int psize, int ssize)
{
unsigned long v;
-- v = hpte_encode_avpn(va, psize, ssize);
+- v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
+- v <<= HPTE_V_AVPN_SHIFT;
+ v = hpte_encode_avpn(vpn, psize, ssize);
if (psize != MMU_PAGE_4K)
v |= HPTE_V_LARGE;
+- v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
return v;
-@@ -260,8 +260,8 @@ static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
+ }
+
+@@ -216,30 +253,37 @@ static inline unsigned long hpte_encode_r(unsigned long pa, int psize)
+ }
+
/*
- * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
+- * Build a VA given VSID, EA and segment size
++ * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
*/
--static inline unsigned long hpt_vpn(unsigned long ea, unsigned long vsid,
+-static inline unsigned long hpt_va(unsigned long ea, unsigned long vsid,
- int ssize)
+static inline unsigned long hpt_vpn(unsigned long ea,
+ unsigned long vsid, int ssize)
{
- unsigned long mask;
- int s_shift = segment_shift(ssize);
-@@ -273,9 +273,8 @@ static inline unsigned long hpt_vpn(unsigned long ea, unsigned long vsid,
+- if (ssize == MMU_SEGSIZE_256M)
+- return (vsid << 28) | (ea & 0xfffffffUL);
+- return (vsid << 40) | (ea & 0xffffffffffUL);
++ unsigned long mask;
++ int s_shift = segment_shift(ssize);
++
++ mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
++ return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
+ }
+
/*
* This hashes a virtual address
*/
@@ -101,26 +171,54 @@
+static inline unsigned long hpt_hash(unsigned long vpn,
+ unsigned int shift, int ssize)
{
- int mask;
++ int mask;
unsigned long hash, vsid;
-@@ -284,13 +283,13 @@ static inline unsigned long hpt_hash(unsigned long va, unsigned int shift,
-
+
++ /* VPN_SHIFT can be atmost 12 */
if (ssize == MMU_SEGSIZE_256M) {
- mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
-- hash = ((va >> (SID_SHIFT - VPN_SHIFT)) & 0x0000007fffffffff) ^
-- (((va & mask) >> (shift - VPN_SHIFT)) & 0xffff);
-+ hash = ((vpn >> (SID_SHIFT - VPN_SHIFT)) & 0x0000007fffffffff) ^
-+ (((vpn & mask) >> (shift - VPN_SHIFT)) & 0xffff);
+- hash = (va >> 28) ^ ((va & 0x0fffffffUL) >> shift);
++ mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
++ hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
++ ((vpn & mask) >> (shift - VPN_SHIFT));
} else {
- mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
-- vsid = va >> (SID_SHIFT_1T - VPN_SHIFT);
+- vsid = va >> 40;
+- hash = vsid ^ (vsid << 25) ^ ((va & 0xffffffffffUL) >> shift);
++ mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
+ vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
- hash = (vsid & 0xffffff) ^ ((vsid << 25) & 0x7fffffffff) ^
-- (((va & mask) >> (shift - VPN_SHIFT)) & 0xfffffff);
-+ (((vpn & mask) >> (shift - VPN_SHIFT)) & 0xfffffff);
++ hash = vsid ^ (vsid << 25) ^
++ ((vpn & mask) >> (shift - VPN_SHIFT)) ;
}
return hash & 0x7fffffffffUL;
}
+diff --git a/arch/powerpc/include/asm/pte-hash64-64k.h b/arch/powerpc/include/asm/pte-hash64-64k.h
+index 59247e8..eedf427 100644
+--- a/arch/powerpc/include/asm/pte-hash64-64k.h
++++ b/arch/powerpc/include/asm/pte-hash64-64k.h
+@@ -58,14 +58,16 @@
+ /* Trick: we set __end to va + 64k, which happens works for
+ * a 16M page as well as we want only one iteration
+ */
+-#define pte_iterate_hashed_subpages(rpte, psize, va, index, shift) \
+- do { \
+- unsigned long __end = va + PAGE_SIZE; \
+- unsigned __split = (psize == MMU_PAGE_4K || \
+- psize == MMU_PAGE_64K_AP); \
+- shift = mmu_psize_defs[psize].shift; \
+- for (index = 0; va < __end; index++, va += (1L << shift)) { \
+- if (!__split || __rpte_sub_valid(rpte, index)) do { \
++#define pte_iterate_hashed_subpages(rpte, psize, vpn, index, shift) \
++ do { \
++ unsigned long __end = vpn + (1UL << (PAGE_SHIFT - VPN_SHIFT)); \
++ unsigned __split = (psize == MMU_PAGE_4K || \
++ psize == MMU_PAGE_64K_AP); \
++ shift = mmu_psize_defs[psize].shift; \
++ for (index = 0; vpn < __end; index++, \
++ vpn += (1L << (shift - VPN_SHIFT))) { \
++ if (!__split || __rpte_sub_valid(rpte, index)) \
++ do {
+
+ #define pte_iterate_hashed_end() } while(0); } } while(0)
+
diff --git a/arch/powerpc/include/asm/tlbflush.h b/arch/powerpc/include/asm/tlbflush.h
index 81143fc..fc02d1d 100644
--- a/arch/powerpc/include/asm/tlbflush.h
@@ -144,7 +242,7 @@
extern void flush_hash_range(unsigned long number, int local);
diff --git a/arch/powerpc/kvm/book3s_32_mmu_host.c b/arch/powerpc/kvm/book3s_32_mmu_host.c
-index bf5dfb3..f024d2c 100644
+index 837f13e..00aa612 100644
--- a/arch/powerpc/kvm/book3s_32_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_32_mmu_host.c
@@ -141,7 +141,7 @@ extern char etext[];
@@ -160,12 +258,12 @@
BUG_ON(!map);
vsid = map->host_vsid;
-- va = (vsid << (SID_SHIFT - VPN_SHIFT)) | ((eaddr & ~ESID_MASK) >> VPN_SHIFT)
+- va = (vsid << SID_SHIFT) | (eaddr & ~ESID_MASK);
+ vpn = (vsid << (SID_SHIFT - VPN_SHIFT)) | ((eaddr & ~ESID_MASK) >> VPN_SHIFT)
next_pteg:
if (rr == 16) {
-@@ -241,11 +241,11 @@ next_pteg:
+@@ -244,11 +244,11 @@ next_pteg:
dprintk_mmu("KVM: %c%c Map 0x%llx: [%lx] 0x%llx (0x%llx) -> %lx\n",
orig_pte->may_write ? 'w' : '-',
orig_pte->may_execute ? 'x' : '-',
@@ -180,7 +278,7 @@
pte->pfn = hpaddr >> PAGE_SHIFT;
diff --git a/arch/powerpc/kvm/book3s_64_mmu_host.c b/arch/powerpc/kvm/book3s_64_mmu_host.c
-index 9d184f1..bfb5640 100644
+index 0688b6b..4d72f9e 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_host.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_host.c
@@ -33,7 +33,7 @@
@@ -207,21 +305,21 @@
}
vsid = map->host_vsid;
-- va = hpt_vpn(orig_pte->eaddr, vsid, MMU_SEGSIZE_256M);
+- va = hpt_va(orig_pte->eaddr, vsid, MMU_SEGSIZE_256M);
+ vpn = hpt_vpn(orig_pte->eaddr, vsid, MMU_SEGSIZE_256M);
if (!orig_pte->may_write)
rflags |= HPTE_R_PP;
-@@ -127,7 +128,7 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
- if (!orig_pte->may_execute)
- rflags |= HPTE_R_N;
+@@ -129,7 +130,7 @@ int kvmppc_mmu_map_page(struct kvm_vcpu *vcpu, struct kvmppc_pte *orig_pte)
+ else
+ kvmppc_mmu_flush_icache(hpaddr >> PAGE_SHIFT);
- hash = hpt_hash(va, PTE_SIZE, MMU_SEGSIZE_256M);
+ hash = hpt_hash(vpn, PTE_SIZE, MMU_SEGSIZE_256M);
map_again:
hpteg = ((hash & htab_hash_mask) * HPTES_PER_GROUP);
-@@ -139,7 +140,8 @@ map_again:
+@@ -141,7 +142,8 @@ map_again:
goto out;
}
@@ -231,7 +329,7 @@
if (ret < 0) {
/* If we couldn't map a primary PTE, try a secondary */
-@@ -150,7 +152,8 @@ map_again:
+@@ -152,7 +154,8 @@ map_again:
} else {
struct hpte_cache *pte = kvmppc_mmu_hpte_cache_next(vcpu);
@@ -241,7 +339,7 @@
/* The ppc_md code may give us a secondary entry even though we
asked for a primary. Fix up. */
-@@ -160,7 +163,7 @@ map_again:
+@@ -162,7 +165,7 @@ map_again:
}
pte->slot = hpteg + (ret & 7);
@@ -310,11 +408,328 @@
__entry->vpage, __entry->raddr, __entry->flags)
);
+diff --git a/arch/powerpc/mm/hash_low_64.S b/arch/powerpc/mm/hash_low_64.S
+index 602aeb0..5658508 100644
+--- a/arch/powerpc/mm/hash_low_64.S
++++ b/arch/powerpc/mm/hash_low_64.S
+@@ -63,7 +63,7 @@ _GLOBAL(__hash_page_4K)
+ /* Save non-volatile registers.
+ * r31 will hold "old PTE"
+ * r30 is "new PTE"
+- * r29 is "va"
++ * r29 is vpn
+ * r28 is a hash value
+ * r27 is hashtab mask (maybe dynamic patched instead ?)
+ */
+@@ -111,10 +111,10 @@ BEGIN_FTR_SECTION
+ cmpdi r9,0 /* check segment size */
+ bne 3f
+ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
+- /* Calc va and put it in r29 */
+- rldicr r29,r5,28,63-28
+- rldicl r3,r3,0,36
+- or r29,r3,r29
++ /* Calc vpn and put it in r29 */
++ sldi r29,r5,SID_SHIFT - VPN_SHIFT
++ rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
++ or r29,r28,r29
+
+ /* Calculate hash value for primary slot and store it in r28 */
+ rldicl r5,r5,0,25 /* vsid & 0x0000007fffffffff */
+@@ -122,14 +122,19 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
+ xor r28,r5,r0
+ b 4f
+
+-3: /* Calc VA and hash in r29 and r28 for 1T segment */
+- sldi r29,r5,40 /* vsid << 40 */
+- clrldi r3,r3,24 /* ea & 0xffffffffff */
++3: /* Calc vpn and put it in r29 */
++ sldi r29,r5,SID_SHIFT_1T - VPN_SHIFT
++ rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT_1T - VPN_SHIFT)
++ or r29,r28,r29
++
++ /*
++ * calculate hash value for primary slot and
++ * store it in r28 for 1T segment
++ */
+ rldic r28,r5,25,25 /* (vsid << 25) & 0x7fffffffff */
+ clrldi r5,r5,40 /* vsid & 0xffffff */
+ rldicl r0,r3,64-12,36 /* (ea >> 12) & 0xfffffff */
+ xor r28,r28,r5
+- or r29,r3,r29 /* VA */
+ xor r28,r28,r0 /* hash */
+
+ /* Convert linux PTE bits into HW equivalents */
+@@ -185,7 +190,7 @@ htab_insert_pte:
+
+ /* Call ppc_md.hpte_insert */
+ ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
+- mr r4,r29 /* Retrieve va */
++ mr r4,r29 /* Retrieve vpn */
+ li r7,0 /* !bolted, !secondary */
+ li r8,MMU_PAGE_4K /* page size */
+ ld r9,STK_PARAM(R9)(r1) /* segment size */
+@@ -208,7 +213,7 @@ _GLOBAL(htab_call_hpte_insert1)
+
+ /* Call ppc_md.hpte_insert */
+ ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
+- mr r4,r29 /* Retrieve va */
++ mr r4,r29 /* Retrieve vpn */
+ li r7,HPTE_V_SECONDARY /* !bolted, secondary */
+ li r8,MMU_PAGE_4K /* page size */
+ ld r9,STK_PARAM(R9)(r1) /* segment size */
+@@ -278,7 +283,7 @@ htab_modify_pte:
+ add r3,r0,r3 /* add slot idx */
+
+ /* Call ppc_md.hpte_updatepp */
+- mr r5,r29 /* va */
++ mr r5,r29 /* vpn */
+ li r6,MMU_PAGE_4K /* page size */
+ ld r7,STK_PARAM(R9)(r1) /* segment size */
+ ld r8,STK_PARAM(R8)(r1) /* get "local" param */
+@@ -339,7 +344,7 @@ _GLOBAL(__hash_page_4K)
+ /* Save non-volatile registers.
+ * r31 will hold "old PTE"
+ * r30 is "new PTE"
+- * r29 is "va"
++ * r29 is vpn
+ * r28 is a hash value
+ * r27 is hashtab mask (maybe dynamic patched instead ?)
+ * r26 is the hidx mask
+@@ -394,10 +399,14 @@ BEGIN_FTR_SECTION
+ cmpdi r9,0 /* check segment size */
+ bne 3f
+ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
+- /* Calc va and put it in r29 */
+- rldicr r29,r5,28,63-28 /* r29 = (vsid << 28) */
+- rldicl r3,r3,0,36 /* r3 = (ea & 0x0fffffff) */
+- or r29,r3,r29 /* r29 = va */
++ /* Calc vpn and put it in r29 */
++ sldi r29,r5,SID_SHIFT - VPN_SHIFT
++ /*
++ * clrldi r3,r3,64 - SID_SHIFT --> ea & 0xfffffff
++ * srdi r28,r3,VPN_SHIFT
++ */
++ rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
++ or r29,r28,r29
+
+ /* Calculate hash value for primary slot and store it in r28 */
+ rldicl r5,r5,0,25 /* vsid & 0x0000007fffffffff */
+@@ -405,14 +414,23 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
+ xor r28,r5,r0
+ b 4f
+
+-3: /* Calc VA and hash in r29 and r28 for 1T segment */
+- sldi r29,r5,40 /* vsid << 40 */
+- clrldi r3,r3,24 /* ea & 0xffffffffff */
++3: /* Calc vpn and put it in r29 */
++ sldi r29,r5,SID_SHIFT_1T - VPN_SHIFT
++ /*
++ * clrldi r3,r3,64 - SID_SHIFT_1T --> ea & 0xffffffffff
++ * srdi r28,r3,VPN_SHIFT
++ */
++ rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT_1T - VPN_SHIFT)
++ or r29,r28,r29
++
++ /*
++ * Calculate hash value for primary slot and
++ * store it in r28 for 1T segment
++ */
+ rldic r28,r5,25,25 /* (vsid << 25) & 0x7fffffffff */
+ clrldi r5,r5,40 /* vsid & 0xffffff */
+ rldicl r0,r3,64-12,36 /* (ea >> 12) & 0xfffffff */
+ xor r28,r28,r5
+- or r29,r3,r29 /* VA */
+ xor r28,r28,r0 /* hash */
+
+ /* Convert linux PTE bits into HW equivalents */
+@@ -488,7 +506,7 @@ htab_special_pfn:
+
+ /* Call ppc_md.hpte_insert */
+ ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
+- mr r4,r29 /* Retrieve va */
++ mr r4,r29 /* Retrieve vpn */
+ li r7,0 /* !bolted, !secondary */
+ li r8,MMU_PAGE_4K /* page size */
+ ld r9,STK_PARAM(R9)(r1) /* segment size */
+@@ -515,7 +533,7 @@ _GLOBAL(htab_call_hpte_insert1)
+
+ /* Call ppc_md.hpte_insert */
+ ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
+- mr r4,r29 /* Retrieve va */
++ mr r4,r29 /* Retrieve vpn */
+ li r7,HPTE_V_SECONDARY /* !bolted, secondary */
+ li r8,MMU_PAGE_4K /* page size */
+ ld r9,STK_PARAM(R9)(r1) /* segment size */
+@@ -547,7 +565,7 @@ _GLOBAL(htab_call_hpte_remove)
+ * useless now that the segment has been switched to 4k pages.
+ */
+ htab_inval_old_hpte:
+- mr r3,r29 /* virtual addr */
++ mr r3,r29 /* vpn */
+ mr r4,r31 /* PTE.pte */
+ li r5,0 /* PTE.hidx */
+ li r6,MMU_PAGE_64K /* psize */
+@@ -620,7 +638,7 @@ htab_modify_pte:
+ add r3,r0,r3 /* add slot idx */
+
+ /* Call ppc_md.hpte_updatepp */
+- mr r5,r29 /* va */
++ mr r5,r29 /* vpn */
+ li r6,MMU_PAGE_4K /* page size */
+ ld r7,STK_PARAM(R9)(r1) /* segment size */
+ ld r8,STK_PARAM(R8)(r1) /* get "local" param */
+@@ -676,7 +694,7 @@ _GLOBAL(__hash_page_64K)
+ /* Save non-volatile registers.
+ * r31 will hold "old PTE"
+ * r30 is "new PTE"
+- * r29 is "va"
++ * r29 is vpn
+ * r28 is a hash value
+ * r27 is hashtab mask (maybe dynamic patched instead ?)
+ */
+@@ -729,10 +747,10 @@ BEGIN_FTR_SECTION
+ cmpdi r9,0 /* check segment size */
+ bne 3f
+ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
+- /* Calc va and put it in r29 */
+- rldicr r29,r5,28,63-28
+- rldicl r3,r3,0,36
+- or r29,r3,r29
++ /* Calc vpn and put it in r29 */
++ sldi r29,r5,SID_SHIFT - VPN_SHIFT
++ rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT - VPN_SHIFT)
++ or r29,r28,r29
+
+ /* Calculate hash value for primary slot and store it in r28 */
+ rldicl r5,r5,0,25 /* vsid & 0x0000007fffffffff */
+@@ -740,14 +758,19 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
+ xor r28,r5,r0
+ b 4f
+
+-3: /* Calc VA and hash in r29 and r28 for 1T segment */
+- sldi r29,r5,40 /* vsid << 40 */
+- clrldi r3,r3,24 /* ea & 0xffffffffff */
++3: /* Calc vpn and put it in r29 */
++ sldi r29,r5,SID_SHIFT_1T - VPN_SHIFT
++ rldicl r28,r3,64 - VPN_SHIFT,64 - (SID_SHIFT_1T - VPN_SHIFT)
++ or r29,r28,r29
++
++ /*
++ * calculate hash value for primary slot and
++ * store it in r28 for 1T segment
++ */
+ rldic r28,r5,25,25 /* (vsid << 25) & 0x7fffffffff */
+ clrldi r5,r5,40 /* vsid & 0xffffff */
+ rldicl r0,r3,64-16,40 /* (ea >> 16) & 0xffffff */
+ xor r28,r28,r5
+- or r29,r3,r29 /* VA */
+ xor r28,r28,r0 /* hash */
+
+ /* Convert linux PTE bits into HW equivalents */
+@@ -806,7 +829,7 @@ ht64_insert_pte:
+
+ /* Call ppc_md.hpte_insert */
+ ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
+- mr r4,r29 /* Retrieve va */
++ mr r4,r29 /* Retrieve vpn */
+ li r7,0 /* !bolted, !secondary */
+ li r8,MMU_PAGE_64K
+ ld r9,STK_PARAM(R9)(r1) /* segment size */
+@@ -829,7 +852,7 @@ _GLOBAL(ht64_call_hpte_insert1)
+
+ /* Call ppc_md.hpte_insert */
+ ld r6,STK_PARAM(R4)(r1) /* Retrieve new pp bits */
+- mr r4,r29 /* Retrieve va */
++ mr r4,r29 /* Retrieve vpn */
+ li r7,HPTE_V_SECONDARY /* !bolted, secondary */
+ li r8,MMU_PAGE_64K
+ ld r9,STK_PARAM(R9)(r1) /* segment size */
+@@ -899,7 +922,7 @@ ht64_modify_pte:
+ add r3,r0,r3 /* add slot idx */
+
+ /* Call ppc_md.hpte_updatepp */
+- mr r5,r29 /* va */
++ mr r5,r29 /* vpn */
+ li r6,MMU_PAGE_64K
+ ld r7,STK_PARAM(R9)(r1) /* segment size */
+ ld r8,STK_PARAM(R8)(r1) /* get "local" param */
diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c
-index 8e12798..c01679f 100644
+index 660b8bb..36b212b 100644
--- a/arch/powerpc/mm/hash_native_64.c
+++ b/arch/powerpc/mm/hash_native_64.c
-@@ -115,7 +115,7 @@ static inline void __tlbiel(unsigned long vpn, int psize, int ssize)
+@@ -39,22 +39,35 @@
+
+ DEFINE_RAW_SPINLOCK(native_tlbie_lock);
+
+-static inline void __tlbie(unsigned long va, int psize, int ssize)
++static inline void __tlbie(unsigned long vpn, int psize, int ssize)
+ {
++ unsigned long va;
+ unsigned int penc;
+
+- /* clear top 16 bits, non SLS segment */
++ /*
++ * We need 14 to 65 bits of va for a tlibe of 4K page
++ * With vpn we ignore the lower VPN_SHIFT bits already.
++ * And top two bits are already ignored because we can
++ * only accomadate 76 bits in a 64 bit vpn with a VPN_SHIFT
++ * of 12.
++ */
++ va = vpn << VPN_SHIFT;
++ /*
++ * clear top 16 bits of 64bit va, non SLS segment
++ * Older versions of the architecture (2.02 and earler) require the
++ * masking of the top 16 bits.
++ */
+ va &= ~(0xffffULL << 48);
+
+ switch (psize) {
+ case MMU_PAGE_4K:
+- va &= ~0xffful;
+ va |= ssize << 8;
+ asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
+ : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
+ : "memory");
+ break;
+ default:
++ /* We need 14 to 14 + i bits of va */
+ penc = mmu_psize_defs[psize].penc;
+ va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
+ va |= penc << 12;
+@@ -67,21 +80,28 @@ static inline void __tlbie(unsigned long va, int psize, int ssize)
+ }
+ }
+
+-static inline void __tlbiel(unsigned long va, int psize, int ssize)
++static inline void __tlbiel(unsigned long vpn, int psize, int ssize)
+ {
++ unsigned long va;
+ unsigned int penc;
+
+- /* clear top 16 bits, non SLS segment */
++ /* VPN_SHIFT can be atmost 12 */
++ va = vpn << VPN_SHIFT;
++ /*
++ * clear top 16 bits of 64 bit va, non SLS segment
++ * Older versions of the architecture (2.02 and earler) require the
++ * masking of the top 16 bits.
++ */
+ va &= ~(0xffffULL << 48);
+
+ switch (psize) {
+ case MMU_PAGE_4K:
+- va &= ~0xffful;
+ va |= ssize << 8;
+ asm volatile(".long 0x7c000224 | (%0 << 11) | (0 << 21)"
+ : : "r"(va) : "memory");
+ break;
+ default:
++ /* We need 14 to 14 + i bits of va */
+ penc = mmu_psize_defs[psize].penc;
+ va &= ~((1ul << mmu_psize_defs[psize].shift) - 1);
+ va |= penc << 12;
+@@ -94,7 +114,7 @@ static inline void __tlbiel(unsigned long va, int psize, int ssize)
}
@@ -323,7 +738,7 @@
{
unsigned int use_local = local && mmu_has_feature(MMU_FTR_TLBIEL);
int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
-@@ -126,10 +126,10 @@ static inline void tlbie(unsigned long va, int psize, int ssize, int local)
+@@ -105,10 +125,10 @@ static inline void tlbie(unsigned long va, int psize, int ssize, int local)
raw_spin_lock(&native_tlbie_lock);
asm volatile("ptesync": : :"memory");
if (use_local) {
@@ -336,7 +751,7 @@
asm volatile("eieio; tlbsync; ptesync": : :"memory");
}
if (lock_tlbie && !use_local)
-@@ -155,7 +155,7 @@ static inline void native_unlock_hpte(struct hash_pte *hptep)
+@@ -134,7 +154,7 @@ static inline void native_unlock_hpte(struct hash_pte *hptep)
clear_bit_unlock(HPTE_LOCK_BIT, word);
}
@@ -345,7 +760,7 @@
unsigned long pa, unsigned long rflags,
unsigned long vflags, int psize, int ssize)
{
-@@ -164,9 +164,9 @@ static long native_hpte_insert(unsigned long hpte_group, unsigned long va,
+@@ -143,9 +163,9 @@ static long native_hpte_insert(unsigned long hpte_group, unsigned long va,
int i;
if (!(vflags & HPTE_V_BOLTED)) {
@@ -357,7 +772,7 @@
}
for (i = 0; i < HPTES_PER_GROUP; i++) {
-@@ -184,7 +184,7 @@ static long native_hpte_insert(unsigned long hpte_group, unsigned long va,
+@@ -163,7 +183,7 @@ static long native_hpte_insert(unsigned long hpte_group, unsigned long va,
if (i == HPTES_PER_GROUP)
return -1;
@@ -366,7 +781,7 @@
hpte_r = hpte_encode_r(pa, psize) | rflags;
if (!(vflags & HPTE_V_BOLTED)) {
-@@ -246,17 +246,17 @@ static long native_hpte_remove(unsigned long hpte_group)
+@@ -225,17 +245,17 @@ static long native_hpte_remove(unsigned long hpte_group)
}
static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
@@ -381,14 +796,14 @@
- want_v = hpte_encode_v(va, psize, ssize);
+ want_v = hpte_encode_v(vpn, psize, ssize);
-- DBG_LOW(" update(va=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
+- DBG_LOW(" update(va=%016lx, avpnv=%016lx, hash=%016lx, newpp=%x)",
- va, want_v & HPTE_V_AVPN, slot, newpp);
+ DBG_LOW(" update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
+ vpn, want_v & HPTE_V_AVPN, slot, newpp);
native_lock_hpte(hptep);
-@@ -275,12 +275,12 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
+@@ -254,12 +274,12 @@ static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
native_unlock_hpte(hptep);
/* Ensure it is out of the tlb too. */
@@ -403,7 +818,7 @@
{
struct hash_pte *hptep;
unsigned long hash;
-@@ -288,8 +288,8 @@ static long native_hpte_find(unsigned long va, int psize, int ssize)
+@@ -267,8 +287,8 @@ static long native_hpte_find(unsigned long va, int psize, int ssize)
long slot;
unsigned long want_v, hpte_v;
@@ -414,7 +829,7 @@
/* Bolted mappings are only ever in the primary group */
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
-@@ -316,14 +316,15 @@ static long native_hpte_find(unsigned long va, int psize, int ssize)
+@@ -295,14 +315,15 @@ static long native_hpte_find(unsigned long va, int psize, int ssize)
static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
int psize, int ssize)
{
@@ -425,7 +840,7 @@
struct hash_pte *hptep;
vsid = get_kernel_vsid(ea, ssize);
-- va = hpt_vpn(ea, vsid, ssize);
+- va = hpt_va(ea, vsid, ssize);
+ vpn = hpt_vpn(ea, vsid, ssize);
- slot = native_hpte_find(va, psize, ssize);
@@ -433,7 +848,7 @@
if (slot == -1)
panic("could not find page to bolt\n");
hptep = htab_address + slot;
-@@ -333,10 +334,10 @@ static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
+@@ -312,10 +333,10 @@ static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
(newpp & (HPTE_R_PP | HPTE_R_N));
/* Ensure it is out of the tlb too. */
@@ -446,11 +861,11 @@
int psize, int ssize, int local)
{
struct hash_pte *hptep = htab_address + slot;
-@@ -346,9 +347,9 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long va,
+@@ -325,9 +346,9 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long va,
local_irq_save(flags);
-- DBG_LOW(" invalidate(va=%016lx, hash: %lx)\n", va, slot);
+- DBG_LOW(" invalidate(va=%016lx, hash: %x)\n", va, slot);
+ DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot);
- want_v = hpte_encode_v(va, psize, ssize);
@@ -458,7 +873,7 @@
native_lock_hpte(hptep);
hpte_v = hptep->v;
-@@ -360,7 +361,7 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long va,
+@@ -339,7 +360,7 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long va,
hptep->v = 0;
/* Invalidate the TLB */
@@ -467,7 +882,7 @@
local_irq_restore(flags);
}
-@@ -370,7 +371,7 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long va,
+@@ -349,7 +370,7 @@ static void native_hpte_invalidate(unsigned long slot, unsigned long va,
#define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT)
static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
@@ -476,20 +891,20 @@
{
unsigned long avpn, pteg, vpi;
unsigned long hpte_r = hpte->r;
-@@ -420,7 +421,7 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
+@@ -399,7 +420,7 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
vpi = (vsid ^ pteg) & htab_hash_mask;
seg_off |= vpi << shift;
}
-- *va = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT;
+- *va = vsid << SID_SHIFT | seg_off;
+ *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT;
case MMU_SEGSIZE_1T:
/* We only have 40 - 23 bits of seg_off in avpn */
seg_off = (avpn & 0x1ffff) << 23;
-@@ -429,9 +430,9 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
+@@ -408,9 +429,9 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
seg_off |= vpi << shift;
}
-- *va = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT;
+- *va = vsid << SID_SHIFT_1T | seg_off;
+ *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT;
default:
- *va = size = 0;
@@ -497,16 +912,19 @@
}
*psize = size;
}
-@@ -446,7 +447,7 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
+@@ -425,9 +446,10 @@ static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
*/
static void native_hpte_clear(void)
{
-- unsigned long va = 0;
+ unsigned long vpn = 0;
unsigned long slot, slots, flags;
struct hash_pte *hptep = htab_address;
- unsigned long hpte_v;
-@@ -477,9 +478,9 @@ static void native_hpte_clear(void)
+- unsigned long hpte_v, va;
++ unsigned long hpte_v;
+ unsigned long pteg_count;
+ int psize, ssize;
+
+@@ -455,9 +477,9 @@ static void native_hpte_clear(void)
* already hold the native_tlbie_lock.
*/
if (hpte_v & HPTE_V_VALID) {
@@ -518,7 +936,7 @@
}
}
-@@ -494,7 +495,8 @@ static void native_hpte_clear(void)
+@@ -472,7 +494,8 @@ static void native_hpte_clear(void)
*/
static void native_flush_hash_range(unsigned long number, int local)
{
@@ -528,7 +946,7 @@
struct hash_pte *hptep;
unsigned long hpte_v;
unsigned long want_v;
-@@ -508,18 +510,18 @@ static void native_flush_hash_range(unsigned long number, int local)
+@@ -486,18 +509,18 @@ static void native_flush_hash_range(unsigned long number, int local)
local_irq_save(flags);
for (i = 0; i < number; i++) {
@@ -551,7 +969,7 @@
native_lock_hpte(hptep);
hpte_v = hptep->v;
if (!HPTE_V_COMPARE(hpte_v, want_v) ||
-@@ -534,12 +536,12 @@ static void native_flush_hash_range(unsigned long number, int local)
+@@ -512,12 +535,12 @@ static void native_flush_hash_range(unsigned long number, int local)
mmu_psize_defs[psize].tlbiel && local) {
asm volatile("ptesync":::"memory");
for (i = 0; i < number; i++) {
@@ -568,7 +986,7 @@
} pte_iterate_hashed_end();
}
asm volatile("ptesync":::"memory");
-@@ -551,12 +553,12 @@ static void native_flush_hash_range(unsigned long number, int local)
+@@ -529,12 +552,12 @@ static void native_flush_hash_range(unsigned long number, int local)
asm volatile("ptesync":::"memory");
for (i = 0; i < number; i++) {
@@ -586,14 +1004,14 @@
}
asm volatile("eieio; tlbsync; ptesync":::"memory");
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
-index 975c7d1..74c5479 100644
+index 377e5cb..74c5479 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -192,18 +192,18 @@ int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
vaddr += step, paddr += step) {
unsigned long hash, hpteg;
unsigned long vsid = get_kernel_vsid(vaddr, ssize);
-- unsigned long va = hpt_vpn(vaddr, vsid, ssize);
+- unsigned long va = hpt_va(vaddr, vsid, ssize);
+ unsigned long vpn = hpt_vpn(vaddr, vsid, ssize);
unsigned long tprot = prot;
@@ -651,7 +1069,7 @@
{
unsigned long hash, hpteg;
unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
-- unsigned long va = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
+- unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
+ unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
unsigned long mode = htab_convert_pte_flags(PAGE_KERNEL);
int ret;
@@ -669,7 +1087,7 @@
{
unsigned long hash, hidx, slot;
unsigned long vsid = get_kernel_vsid(vaddr, mmu_kernel_ssize);
-- unsigned long va = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
+- unsigned long va = hpt_va(vaddr, vsid, mmu_kernel_ssize);
+ unsigned long vpn = hpt_vpn(vaddr, vsid, mmu_kernel_ssize);
- hash = hpt_hash(va, PAGE_SHIFT, mmu_kernel_ssize);
@@ -687,7 +1105,7 @@
void kernel_map_pages(struct page *page, int numpages, int enable)
diff --git a/arch/powerpc/mm/hugetlbpage-hash64.c b/arch/powerpc/mm/hugetlbpage-hash64.c
-index 1331403..cecad34 100644
+index cc5c273..cecad34 100644
--- a/arch/powerpc/mm/hugetlbpage-hash64.c
+++ b/arch/powerpc/mm/hugetlbpage-hash64.c
@@ -18,14 +18,15 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
@@ -703,7 +1121,7 @@
BUG_ON(shift != mmu_psize_defs[mmu_psize].shift);
/* Search the Linux page table for a match with va */
-- va = hpt_vpn(ea, vsid, ssize);
+- va = hpt_va(ea, vsid, ssize);
+ vpn = hpt_vpn(ea, vsid, ssize);
/* At this point, we have a pte (old_pte) which can be used to build
@@ -749,7 +1167,7 @@
mmu_psize, ssize);
if (slot == -1) {
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
-index 321c585..ae758b3 100644
+index 31f1820..ae758b3 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -42,8 +42,9 @@ DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
@@ -767,7 +1185,7 @@
vsid = get_kernel_vsid(addr, mmu_kernel_ssize);
ssize = mmu_kernel_ssize;
}
-- vaddr = hpt_vpn(addr, vsid, ssize);
+- vaddr = hpt_va(addr, vsid, ssize);
+ vpn = hpt_vpn(addr, vsid, ssize);
rpte = __real_pte(__pte(pte), ptep);
@@ -800,7 +1218,7 @@
else
flush_hash_range(i, local);
diff --git a/arch/powerpc/platforms/cell/beat_htab.c b/arch/powerpc/platforms/cell/beat_htab.c
-index c8c7bf6..0f6f839 100644
+index b83077e..0f6f839 100644
--- a/arch/powerpc/platforms/cell/beat_htab.c
+++ b/arch/powerpc/platforms/cell/beat_htab.c
@@ -88,7 +88,7 @@ static inline unsigned int beat_read_mask(unsigned hpte_group)
@@ -867,7 +1285,7 @@
u64 dummy0, dummy1;
vsid = get_kernel_vsid(ea, MMU_SEGSIZE_256M);
-- va = hpt_vpn(ea, vsid, MMU_SEGSIZE_256M);
+- va = hpt_va(ea, vsid, MMU_SEGSIZE_256M);
+ vpn = hpt_vpn(ea, vsid, MMU_SEGSIZE_256M);
raw_spin_lock(&beat_htab_lock);
@@ -1039,7 +1457,7 @@
}
diff --git a/arch/powerpc/platforms/pseries/lpar.c b/arch/powerpc/platforms/pseries/lpar.c
-index 2127529..8308b25 100644
+index 5f3ef87..8308b25 100644
--- a/arch/powerpc/platforms/pseries/lpar.c
+++ b/arch/powerpc/platforms/pseries/lpar.c
@@ -108,9 +108,9 @@ void vpa_init(int cpu)
@@ -1071,7 +1489,30 @@
hpte_r = hpte_encode_r(pa, psize) | rflags;
if (!(vflags & HPTE_V_BOLTED))
-@@ -234,14 +234,14 @@ static void pSeries_lpar_hptab_clear(void)
+@@ -227,22 +227,6 @@ static void pSeries_lpar_hptab_clear(void)
+ }
+
+ /*
+- * This computes the AVPN and B fields of the first dword of a HPTE,
+- * for use when we want to match an existing PTE. The bottom 7 bits
+- * of the returned value are zero.
+- */
+-static inline unsigned long hpte_encode_avpn(unsigned long va, int psize,
+- int ssize)
+-{
+- unsigned long v;
+-
+- v = (va >> 23) & ~(mmu_psize_defs[psize].avpnm);
+- v <<= HPTE_V_AVPN_SHIFT;
+- v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
+- return v;
+-}
+-
+-/*
+ * NOTE: for updatepp ops we are fortunate that the linux "newpp" bits and
+ * the low 3 bits of flags happen to line up. So no transform is needed.
+ * We can probably optimize here and assume the high bits of newpp are
+@@ -250,14 +234,14 @@ static inline unsigned long hpte_encode_avpn(unsigned long va, int psize,
*/
static long pSeries_lpar_hpte_updatepp(unsigned long slot,
unsigned long newpp,
@@ -1088,7 +1529,7 @@
pr_devel(" update: avpnv=%016lx, hash=%016lx, f=%lx, psize: %d ...",
want_v, slot, flags, psize);
-@@ -279,15 +279,15 @@ static unsigned long pSeries_lpar_hpte_getword0(unsigned long slot)
+@@ -295,15 +279,15 @@ static unsigned long pSeries_lpar_hpte_getword0(unsigned long slot)
return dword0;
}
@@ -1107,7 +1548,7 @@
/* Bolted entries are always in the primary group */
slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
-@@ -307,12 +307,13 @@ static void pSeries_lpar_hpte_updateboltedpp(unsigned long newpp,
+@@ -323,12 +307,13 @@ static void pSeries_lpar_hpte_updateboltedpp(unsigned long newpp,
unsigned long ea,
int psize, int ssize)
{
@@ -1116,7 +1557,7 @@
+ unsigned long lpar_rc, slot, vsid, flags;
vsid = get_kernel_vsid(ea, ssize);
-- va = hpt_vpn(ea, vsid, ssize);
+- va = hpt_va(ea, vsid, ssize);
+ vpn = hpt_vpn(ea, vsid, ssize);
- slot = pSeries_lpar_hpte_find(va, psize, ssize);
@@ -1124,7 +1565,7 @@
BUG_ON(slot == -1);
flags = newpp & 7;
-@@ -321,17 +322,17 @@ static void pSeries_lpar_hpte_updateboltedpp(unsigned long newpp,
+@@ -337,17 +322,17 @@ static void pSeries_lpar_hpte_updateboltedpp(unsigned long newpp,
BUG_ON(lpar_rc != H_SUCCESS);
}
@@ -1146,7 +1587,7 @@
lpar_rc = plpar_pte_remove(H_AVPN, slot, want_v, &dummy1, &dummy2);
if (lpar_rc == H_NOT_FOUND)
return;
-@@ -342,15 +343,16 @@ static void pSeries_lpar_hpte_invalidate(unsigned long slot, unsigned long va,
+@@ -358,15 +343,16 @@ static void pSeries_lpar_hpte_invalidate(unsigned long slot, unsigned long va,
static void pSeries_lpar_hpte_removebolted(unsigned long ea,
int psize, int ssize)
{
@@ -1155,7 +1596,7 @@
+ unsigned long slot, vsid;
vsid = get_kernel_vsid(ea, ssize);
-- va = hpt_vpn(ea, vsid, ssize);
+- va = hpt_va(ea, vsid, ssize);
+ vpn = hpt_vpn(ea, vsid, ssize);
- slot = pSeries_lpar_hpte_find(va, psize, ssize);
@@ -1167,7 +1608,7 @@
}
/* Flag bits for H_BULK_REMOVE */
-@@ -366,12 +368,12 @@ static void pSeries_lpar_hpte_removebolted(unsigned long ea,
+@@ -382,12 +368,12 @@ static void pSeries_lpar_hpte_removebolted(unsigned long ea,
*/
static void pSeries_lpar_flush_hash_range(unsigned long number, int local)
{
@@ -1181,7 +1622,7 @@
unsigned long hash, index, shift, hidx, slot;
real_pte_t pte;
int psize, ssize;
-@@ -383,21 +385,21 @@ static void pSeries_lpar_flush_hash_range(unsigned long number, int local)
+@@ -399,21 +385,21 @@ static void pSeries_lpar_flush_hash_range(unsigned long number, int local)
ssize = batch->ssize;
pix = 0;
for (i = 0; i < number; i++) {