--- v4
+++ v8
@@ -3,20 +3,23 @@
Increase max addressable range to 64TB. This is not tested on
real hardware yet.
+Reviewed-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
---
- arch/powerpc/include/asm/mmu-hash64.h | 14 +++++++++-----
+ arch/powerpc/include/asm/mmu-hash64.h | 42 ++++++++++++++++++++------
arch/powerpc/include/asm/pgtable-ppc64-4k.h | 2 +-
arch/powerpc/include/asm/pgtable-ppc64-64k.h | 2 +-
- arch/powerpc/include/asm/processor.h | 4 ++--
- arch/powerpc/include/asm/sparsemem.h | 4 ++--
- 5 files changed, 15 insertions(+), 11 deletions(-)
+ arch/powerpc/include/asm/processor.h | 4 +--
+ arch/powerpc/include/asm/sparsemem.h | 4 +--
+ arch/powerpc/kernel/exceptions-64s.S | 4 ++-
+ arch/powerpc/mm/slb_low.S | 12 ++++++++
+ 7 files changed, 54 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
-index d24d484..daa3e4b 100644
+index cbd7edb..de9cfed 100644
--- a/arch/powerpc/include/asm/mmu-hash64.h
+++ b/arch/powerpc/include/asm/mmu-hash64.h
-@@ -376,17 +376,21 @@ extern void slb_set_size(u16 size);
+@@ -370,17 +370,21 @@ extern void slb_set_size(u16 size);
* (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
*/
@@ -43,6 +46,43 @@
#define USER_VSID_RANGE (1UL << (USER_ESID_BITS + SID_SHIFT))
+@@ -503,12 +507,32 @@ typedef struct {
+ })
+ #endif /* 1 */
+
+-/* This is only valid for addresses >= PAGE_OFFSET */
++/*
++ * This is only valid for addresses >= PAGE_OFFSET
++ * The proto-VSID space is divided into two class
++ * User: 0 to 2^(CONTEXT_BITS + USER_ESID_BITS) -1
++ * kernel: 2^(CONTEXT_BITS + USER_ESID_BITS) to 2^(VSID_BITS) - 1
++ *
++ * With KERNEL_START at 0xc000000000000000, the proto vsid for
++ * the kernel ends up with 0xc00000000 (36 bits). With 64TB
++ * support we need to have kernel proto-VSID in the
++ * [2^37 to 2^38 - 1] range due to the increased USER_ESID_BITS.
++ */
+ static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
+ {
+- if (ssize == MMU_SEGSIZE_256M)
+- return vsid_scramble(ea >> SID_SHIFT, 256M);
+- return vsid_scramble(ea >> SID_SHIFT_1T, 1T);
++ unsigned long proto_vsid;
++ /*
++ * We need to make sure proto_vsid for the kernel is
++ * >= 2^(CONTEXT_BITS + USER_ESID_BITS[_1T])
++ */
++ if (ssize == MMU_SEGSIZE_256M) {
++ proto_vsid = ea >> SID_SHIFT;
++ proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS));
++ return vsid_scramble(proto_vsid, 256M);
++ }
++ proto_vsid = ea >> SID_SHIFT_1T;
++ proto_vsid |= (1UL << (CONTEXT_BITS + USER_ESID_BITS_1T));
++ return vsid_scramble(proto_vsid, 1T);
+ }
+
+ /* Returns the segment size indicator for a user address */
diff --git a/arch/powerpc/include/asm/pgtable-ppc64-4k.h b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
index 6eefdcf..b3eccf2 100644
--- a/arch/powerpc/include/asm/pgtable-ppc64-4k.h
@@ -70,7 +110,7 @@
#ifndef __ASSEMBLY__
#define PTE_TABLE_SIZE (sizeof(real_pte_t) << PTE_INDEX_SIZE)
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
-index 413a5ea..ac3861b 100644
+index 53b6dfa..00bda2f 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -97,8 +97,8 @@ extern struct task_struct *last_task_used_spe;
@@ -99,5 +139,50 @@
#endif /* CONFIG_SPARSEMEM */
+diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
+index e894515..d980818 100644
+--- a/arch/powerpc/kernel/exceptions-64s.S
++++ b/arch/powerpc/kernel/exceptions-64s.S
+@@ -959,7 +959,9 @@ _GLOBAL(do_stab_bolted)
+ rldimi r10,r11,7,52 /* r10 = first ste of the group */
+
+ /* Calculate VSID */
+- /* This is a kernel address, so protovsid = ESID */
++ /* This is a kernel address, so protovsid = ESID | 1 << 37 */
++ li r9,0x1
++ rldimi r11,r9,(CONTEXT_BITS + USER_ESID_BITS),0
+ ASM_VSID_SCRAMBLE(r11, r9, 256M)
+ rldic r9,r11,12,16 /* r9 = vsid << 12 */
+
+diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
+index f6a2625..1a16ca2 100644
+--- a/arch/powerpc/mm/slb_low.S
++++ b/arch/powerpc/mm/slb_low.S
+@@ -56,6 +56,12 @@ _GLOBAL(slb_allocate_realmode)
+ */
+ _GLOBAL(slb_miss_kernel_load_linear)
+ li r11,0
++ li r9,0x1
++ /*
++ * for 1T we shift 12 bits more. slb_finish_load_1T will do
++ * the necessary adjustment
++ */
++ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS),0
+ BEGIN_FTR_SECTION
+ b slb_finish_load
+ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
+@@ -85,6 +91,12 @@ _GLOBAL(slb_miss_kernel_load_vmemmap)
+ _GLOBAL(slb_miss_kernel_load_io)
+ li r11,0
+ 6:
++ li r9,0x1
++ /*
++ * for 1T we shift 12 bits more. slb_finish_load_1T will do
++ * the necessary adjustment
++ */
++ rldimi r10,r9,(CONTEXT_BITS + USER_ESID_BITS),0
+ BEGIN_FTR_SECTION
+ b slb_finish_load
+ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_1T_SEGMENT)
--
1.7.10