diff v4→v3 (patch 10) | series

Inter-revision diff: patch 10

Comparing v4 (message) to v3 (message)
--- v4
+++ v3
@@ -1,103 +1,45 @@
 From: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>
 
-Increase max addressable range to 64TB. This is not tested on
-real hardware yet.
+With larger vsid we need to track more bits of ESID in slb cache
+for slb invalidate.
 
 Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
 ---
- arch/powerpc/include/asm/mmu-hash64.h        |   14 +++++++++-----
- arch/powerpc/include/asm/pgtable-ppc64-4k.h  |    2 +-
- arch/powerpc/include/asm/pgtable-ppc64-64k.h |    2 +-
- arch/powerpc/include/asm/processor.h         |    4 ++--
- arch/powerpc/include/asm/sparsemem.h         |    4 ++--
- 5 files changed, 15 insertions(+), 11 deletions(-)
+ arch/powerpc/include/asm/paca.h |    2 +-
+ arch/powerpc/mm/slb_low.S       |    8 ++++----
+ 2 files changed, 5 insertions(+), 5 deletions(-)
 
-diff --git a/arch/powerpc/include/asm/mmu-hash64.h b/arch/powerpc/include/asm/mmu-hash64.h
-index d24d484..daa3e4b 100644
---- a/arch/powerpc/include/asm/mmu-hash64.h
-+++ b/arch/powerpc/include/asm/mmu-hash64.h
-@@ -376,17 +376,21 @@ extern void slb_set_size(u16 size);
-  * (head.S) and ASM_VSID_SCRAMBLE (below) are changed accordingly.
-  */
+diff --git a/arch/powerpc/include/asm/paca.h b/arch/powerpc/include/asm/paca.h
+index daf813f..3e7abba 100644
+--- a/arch/powerpc/include/asm/paca.h
++++ b/arch/powerpc/include/asm/paca.h
+@@ -100,7 +100,7 @@ struct paca_struct {
+ 	/* SLB related definitions */
+ 	u16 vmalloc_sllp;
+ 	u16 slb_cache_ptr;
+-	u16 slb_cache[SLB_CACHE_ENTRIES];
++	u32 slb_cache[SLB_CACHE_ENTRIES];
+ #endif /* CONFIG_PPC_STD_MMU_64 */
  
--#define VSID_MULTIPLIER_256M	ASM_CONST(200730139)	/* 28-bit prime */
--#define VSID_BITS_256M		36
-+/*
-+ * This should be computed such that protovosid * vsid_mulitplier
-+ * doesn't overflow 64 bits. It should also be co-prime to vsid_modulus
-+ */
-+#define VSID_MULTIPLIER_256M	ASM_CONST(12538073)	/* 24-bit prime */
-+#define VSID_BITS_256M		38
- #define VSID_MODULUS_256M	((1UL<<VSID_BITS_256M)-1)
+ #ifdef CONFIG_PPC_BOOK3E
+diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
+index c1fc81c..d522679 100644
+--- a/arch/powerpc/mm/slb_low.S
++++ b/arch/powerpc/mm/slb_low.S
+@@ -269,10 +269,10 @@ _GLOBAL(slb_compare_rr_to_size)
+ 	bge	1f
  
- #define VSID_MULTIPLIER_1T	ASM_CONST(12538073)	/* 24-bit prime */
--#define VSID_BITS_1T		24
-+#define VSID_BITS_1T		26
- #define VSID_MODULUS_1T		((1UL<<VSID_BITS_1T)-1)
- 
- #define CONTEXT_BITS		19
--#define USER_ESID_BITS		16
--#define USER_ESID_BITS_1T	4
-+#define USER_ESID_BITS		18
-+#define USER_ESID_BITS_1T	6
- 
- #define USER_VSID_RANGE	(1UL << (USER_ESID_BITS + SID_SHIFT))
- 
-diff --git a/arch/powerpc/include/asm/pgtable-ppc64-4k.h b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
-index 6eefdcf..b3eccf2 100644
---- a/arch/powerpc/include/asm/pgtable-ppc64-4k.h
-+++ b/arch/powerpc/include/asm/pgtable-ppc64-4k.h
-@@ -7,7 +7,7 @@
-  */
- #define PTE_INDEX_SIZE  9
- #define PMD_INDEX_SIZE  7
--#define PUD_INDEX_SIZE  7
-+#define PUD_INDEX_SIZE  9
- #define PGD_INDEX_SIZE  9
- 
- #ifndef __ASSEMBLY__
-diff --git a/arch/powerpc/include/asm/pgtable-ppc64-64k.h b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
-index 90533dd..be4e287 100644
---- a/arch/powerpc/include/asm/pgtable-ppc64-64k.h
-+++ b/arch/powerpc/include/asm/pgtable-ppc64-64k.h
-@@ -7,7 +7,7 @@
- #define PTE_INDEX_SIZE  12
- #define PMD_INDEX_SIZE  12
- #define PUD_INDEX_SIZE	0
--#define PGD_INDEX_SIZE  4
-+#define PGD_INDEX_SIZE  6
- 
- #ifndef __ASSEMBLY__
- #define PTE_TABLE_SIZE	(sizeof(real_pte_t) << PTE_INDEX_SIZE)
-diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
-index 413a5ea..ac3861b 100644
---- a/arch/powerpc/include/asm/processor.h
-+++ b/arch/powerpc/include/asm/processor.h
-@@ -97,8 +97,8 @@ extern struct task_struct *last_task_used_spe;
- #endif
- 
- #ifdef CONFIG_PPC64
--/* 64-bit user address space is 44-bits (16TB user VM) */
--#define TASK_SIZE_USER64 (0x0000100000000000UL)
-+/* 64-bit user address space is 46-bits (64TB user VM) */
-+#define TASK_SIZE_USER64 (0x0000400000000000UL)
- 
- /* 
-  * 32-bit user address space is 4GB - 1 page 
-diff --git a/arch/powerpc/include/asm/sparsemem.h b/arch/powerpc/include/asm/sparsemem.h
-index 0c5fa31..f6fc0ee 100644
---- a/arch/powerpc/include/asm/sparsemem.h
-+++ b/arch/powerpc/include/asm/sparsemem.h
-@@ -10,8 +10,8 @@
-  */
- #define SECTION_SIZE_BITS       24
- 
--#define MAX_PHYSADDR_BITS       44
--#define MAX_PHYSMEM_BITS        44
-+#define MAX_PHYSADDR_BITS       46
-+#define MAX_PHYSMEM_BITS        46
- 
- #endif /* CONFIG_SPARSEMEM */
- 
+ 	/* still room in the slb cache */
+-	sldi	r11,r3,1		/* r11 = offset * sizeof(u16) */
+-	rldicl	r10,r10,36,28		/* get low 16 bits of the ESID */
+-	add	r11,r11,r13		/* r11 = (u16 *)paca + offset */
+-	sth	r10,PACASLBCACHE(r11)	/* paca->slb_cache[offset] = esid */
++	sldi	r11,r3,2		/* r11 = offset * sizeof(u32) */
++	rldicl	r10,r10,36,28		/* get the 36 bits of the ESID */
++	add	r11,r11,r13		/* r11 = (u32 *)paca + offset */
++	stw	r10,PACASLBCACHE(r11)	/* paca->slb_cache[offset] = esid */
+ 	addi	r3,r3,1			/* offset++ */
+ 	b	2f
+ 1:					/* offset >= SLB_CACHE_ENTRIES */
 -- 
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