[PATCH] powerpc: warn on emulation of dcbz instruction

Subsystems: linux for powerpc (32-bit and 64-bit), the rest

STALE1807d

6 messages, 3 authors, 2021-09-17 · open the first message on its own page

[PATCH] powerpc: warn on emulation of dcbz instruction

From: Christophe Leroy <hidden>
Date: 2021-09-15 14:32:02

dcbz instruction shouldn't be used on non-cached memory. Using
it on non-cached memory can result in alignment exception and
implies a heavy handling.

Instead of silentely emulating the instruction and resulting in high
performance degradation, warn whenever an alignment exception is
taken due to dcbz, so that the user is made aware that dcbz
instruction has been used unexpectedly.

Reported-by: Stan Johnson <redacted>
Cc: Finn Thain <fthain@linux-m68k.org>
Signed-off-by: Christophe Leroy <redacted>
---
 arch/powerpc/kernel/align.c | 1 +
 1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
index bbb4181621dd..adc3a4a9c6e4 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c
@@ -349,6 +349,7 @@ int fix_alignment(struct pt_regs *regs)
 		if (op.type != CACHEOP + DCBZ)
 			return -EINVAL;
 		PPC_WARN_ALIGNMENT(dcbz, regs);
+		WARN_ON_ONCE(1);
 		r = emulate_dcbz(op.ea, regs);
 	} else {
 		if (type == LARX || type == STCX)
-- 
2.31.1

Re: [PATCH] powerpc: warn on emulation of dcbz instruction

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: 2021-09-16 07:20:54

On Wed, 2021-09-15 at 16:31 +0200, Christophe Leroy wrote:
quoted hunk
dcbz instruction shouldn't be used on non-cached memory. Using
it on non-cached memory can result in alignment exception and
implies a heavy handling.

Instead of silentely emulating the instruction and resulting in high
performance degradation, warn whenever an alignment exception is
taken due to dcbz, so that the user is made aware that dcbz
instruction has been used unexpectedly.

Reported-by: Stan Johnson <redacted>
Cc: Finn Thain <fthain@linux-m68k.org>
Signed-off-by: Christophe Leroy <redacted>
---
 arch/powerpc/kernel/align.c | 1 +
 1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/align.c
b/arch/powerpc/kernel/align.c
index bbb4181621dd..adc3a4a9c6e4 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c
@@ -349,6 +349,7 @@ int fix_alignment(struct pt_regs *regs)
 		if (op.type != CACHEOP + DCBZ)
 			return -EINVAL;
 		PPC_WARN_ALIGNMENT(dcbz, regs);
+		WARN_ON_ONCE(1);
This is heavy handed ... It will be treated as an oops by various
things uselessly spit out a kernel backtrace. Isn't PPC_WARN_ALIGNMENT
enough ?

Ben.

Re: [PATCH] powerpc: warn on emulation of dcbz instruction

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: 2021-09-16 07:22:04

On Thu, 2021-09-16 at 17:15 +1000, Benjamin Herrenschmidt wrote:
On Wed, 2021-09-15 at 16:31 +0200, Christophe Leroy wrote:
quoted
dcbz instruction shouldn't be used on non-cached memory. Using
it on non-cached memory can result in alignment exception and
implies a heavy handling.

Instead of silentely emulating the instruction and resulting in
high
performance degradation, warn whenever an alignment exception is
taken due to dcbz, so that the user is made aware that dcbz
instruction has been used unexpectedly.

Reported-by: Stan Johnson <redacted>
Cc: Finn Thain <fthain@linux-m68k.org>
Signed-off-by: Christophe Leroy <redacted>
---
 arch/powerpc/kernel/align.c | 1 +
 1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/align.c
b/arch/powerpc/kernel/align.c
index bbb4181621dd..adc3a4a9c6e4 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c
@@ -349,6 +349,7 @@ int fix_alignment(struct pt_regs *regs)
 		if (op.type != CACHEOP + DCBZ)
 			return -EINVAL;
 		PPC_WARN_ALIGNMENT(dcbz, regs);
+		WARN_ON_ONCE(1);
This is heavy handed ... It will be treated as an oops by various
things uselessly spit out a kernel backtrace. Isn't
PPC_WARN_ALIGNMENT
enough ?
Ah I saw your other one about fbdev...  Ok what about you do that in a
if (!user_mode(regs)) ?

Indeed the kernel should not do that.

Cheers,
Ben.

Re: [PATCH] powerpc: warn on emulation of dcbz instruction

From: Christophe Leroy <hidden>
Date: 2021-09-16 07:24:11


Le 16/09/2021 à 09:16, Benjamin Herrenschmidt a écrit :
On Thu, 2021-09-16 at 17:15 +1000, Benjamin Herrenschmidt wrote:
quoted
On Wed, 2021-09-15 at 16:31 +0200, Christophe Leroy wrote:
quoted
dcbz instruction shouldn't be used on non-cached memory. Using
it on non-cached memory can result in alignment exception and
implies a heavy handling.

Instead of silentely emulating the instruction and resulting in
high
performance degradation, warn whenever an alignment exception is
taken due to dcbz, so that the user is made aware that dcbz
instruction has been used unexpectedly.

Reported-by: Stan Johnson <redacted>
Cc: Finn Thain <fthain@linux-m68k.org>
Signed-off-by: Christophe Leroy <redacted>
---
  arch/powerpc/kernel/align.c | 1 +
  1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/align.c
b/arch/powerpc/kernel/align.c
index bbb4181621dd..adc3a4a9c6e4 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c
@@ -349,6 +349,7 @@ int fix_alignment(struct pt_regs *regs)
  		if (op.type != CACHEOP + DCBZ)
  			return -EINVAL;
  		PPC_WARN_ALIGNMENT(dcbz, regs);
+		WARN_ON_ONCE(1);
This is heavy handed ... It will be treated as an oops by various
things uselessly spit out a kernel backtrace. Isn't
PPC_WARN_ALIGNMENT
enough ?

PPC_WARN_ALIGNMENT() only warns if explicitely activated, I want to 
catch uses on 'dcbz' on non-cached memory all the time as they are most 
often the result of using memset() instead of memset_io().
Ah I saw your other one about fbdev...  Ok what about you do that in a
if (!user_mode(regs)) ?
Yes I can do WARN_ON_ONCE(!user_mode(regs)); instead.
Indeed the kernel should not do that.

Does userspace accesses non-cached memory directly ?

Christophe

RE: [PATCH] powerpc: warn on emulation of dcbz instruction

From: David Laight <hidden>
Date: 2021-09-16 14:36:26

From: Christophe Leroy
Sent: 16 September 2021 08:24

Le 16/09/2021 à 09:16, Benjamin Herrenschmidt a écrit :
quoted
On Thu, 2021-09-16 at 17:15 +1000, Benjamin Herrenschmidt wrote:
quoted
On Wed, 2021-09-15 at 16:31 +0200, Christophe Leroy wrote:
quoted
dcbz instruction shouldn't be used on non-cached memory. Using
it on non-cached memory can result in alignment exception and
implies a heavy handling.

Instead of silentely emulating the instruction and resulting in
high
performance degradation, warn whenever an alignment exception is
taken due to dcbz, so that the user is made aware that dcbz
instruction has been used unexpectedly.

Reported-by: Stan Johnson <redacted>
Cc: Finn Thain <fthain@linux-m68k.org>
Signed-off-by: Christophe Leroy <redacted>
---
  arch/powerpc/kernel/align.c | 1 +
  1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/kernel/align.c
b/arch/powerpc/kernel/align.c
index bbb4181621dd..adc3a4a9c6e4 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c
@@ -349,6 +349,7 @@ int fix_alignment(struct pt_regs *regs)
  		if (op.type != CACHEOP + DCBZ)
  			return -EINVAL;
  		PPC_WARN_ALIGNMENT(dcbz, regs);
+		WARN_ON_ONCE(1);
This is heavy handed ... It will be treated as an oops by various
things uselessly spit out a kernel backtrace. Isn't
PPC_WARN_ALIGNMENT
enough ?

PPC_WARN_ALIGNMENT() only warns if explicitely activated, I want to
catch uses on 'dcbz' on non-cached memory all the time as they are most
often the result of using memset() instead of memset_io().
quoted
Ah I saw your other one about fbdev...  Ok what about you do that in a
if (!user_mode(regs)) ?
Yes I can do WARN_ON_ONCE(!user_mode(regs)); instead.
quoted
Indeed the kernel should not do that.
Does userspace accesses non-cached memory directly ?
It probably can if a driver mmaps PCI space directly into user space.
That certainly works on x86-64.

	David

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Registration No: 1397386 (Wales)

Re: [PATCH] powerpc: warn on emulation of dcbz instruction

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: 2021-09-17 12:39:36

On Thu, 2021-09-16 at 14:36 +0000, David Laight wrote:
quoted
Does userspace accesses non-cached memory directly ?

It probably can if a driver mmaps PCI space directly into user space.

That certainly works on x86-64.
The posterchild for that is Xorg

Cheers,
Ben.

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