From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 10:58:30
This series applies to powerpc topic/ppc-kvm branch (KVM Cify
series in particular), plus "KVM: PPC: Book3S HV Nested: Reflect L2 PMU
in-use to L0 when L2 SPRs are live" posted to kvm-ppc.
This reduces radix guest full entry/exit latency on POWER9 and POWER10
by almost 2x (hash is similar but it's still significantly slower than
the P7/8 real mode handler). Nested HV guests should see speedups with
some smaller improvements in the L1, plus the L0 switching sees many
of the same speedups as a direct guest.
It does this in several main ways:
- Rearrange code to optimise SPR accesses. Mainly, avoid scoreboard
stalls.
- Test SPR values to avoid mtSPRs where possible. mtSPRs are expensive.
- Reduce mftb. mftb is expensive.
- Demand fault certain facilities to avoid saving and/or restoring them
(at the cost of fault when they are used, but this is mitigated over
a number of entries, like the facilities when context switching
processes). PM, TM, and EBB so far.
- Defer some sequences that are made just in case a guest is interrupted
in the middle of a critical section to the case where the guest is
scheduled on a different CPU, rather than every time (at the cost of
an extra IPI in this case). Namely the tlbsync sequence for radix with
GTSE, which is very expensive.
Some of the numbers quoted in changelogs may have changed a bit with
patches being updated, reordered, etc. They give a bit of a guide, but
I might remove them from the final submission because they're too much
to maintain.
Thanks,
Nick
Nicholas Piggin (43):
powerpc/64s: Remove WORT SPR from POWER9/10
KMV: PPC: Book3S HV P9: Use set_dec to set decrementer to host
KVM: PPC: Book3S HV P9: Use host timer accounting to avoid decrementer
read
KVM: PPC: Book3S HV P9: Use large decrementer for HDEC
KVM: PPC: Book3S HV P9: Reduce mftb per guest entry/exit
powerpc/time: add API for KVM to re-arm the host timer/decrementer
KVM: PPC: Book3S HV: POWER10 enable HAIL when running radix guests
powerpc/64s: Keep AMOR SPR a constant ~0 at runtime
KVM: PPC: Book3S HV: Don't always save PMU for guest capable of
nesting
powerpc/64s: Always set PMU control registers to frozen/disabled when
not in use
KVM: PPC: Book3S HV P9: Implement PMU save/restore in C
KVM: PPC: Book3S HV P9: Factor out yield_count increment
KVM: PPC: Book3S HV P9: Factor PMU save/load into context switch
functions
KVM: PPC: Book3S HV P9: Demand fault PMU SPRs when marked not inuse
KVM: PPC: Book3S HV: CTRL SPR does not require read-modify-write
KVM: PPC: Book3S HV P9: Move SPRG restore to restore_p9_host_os_sprs
KVM: PPC: Book3S HV P9: Reduce mtmsrd instructions required to save
host SPRs
KVM: PPC: Book3S HV P9: Improve mtmsrd scheduling by delaying MSR[EE]
disable
KVM: PPC: Book3S HV P9: Add kvmppc_stop_thread to match
kvmppc_start_thread
KVM: PPC: Book3S HV: Change dec_expires to be relative to guest
timebase
KVM: PPC: Book3S HV P9: Move TB updates
KVM: PPC: Book3S HV P9: Optimise timebase reads
KVM: PPC: Book3S HV P9: Avoid SPR scoreboard stalls
KVM: PPC: Book3S HV P9: Only execute mtSPR if the value changed
KVM: PPC: Book3S HV P9: Juggle SPR switching around
KVM: PPC: Book3S HV P9: Move vcpu register save/restore into functions
KVM: PPC: Book3S HV P9: Move host OS save/restore functions to
built-in
KVM: PPC: Book3S HV P9: Move nested guest entry into its own function
KVM: PPC: Book3S HV P9: Move remaining SPR and MSR access into low
level entry
KVM: PPC: Book3S HV P9: Implement TM fastpath for guest entry/exit
KVM: PPC: Book3S HV P9: Switch PMU to guest as late as possible
KVM: PPC: Book3S HV P9: Restrict DSISR canary workaround to processors
that require it
KVM: PPC: Book3S HV P9: More SPR speed improvements
KVM: PPC: Book3S HV P9: Demand fault EBB facility registers
KVM: PPC: Book3S HV P9: Demand fault TM facility registers
KVM: PPC: Book3S HV P9: Use Linux SPR save/restore to manage some host
SPRs
KVM: PPC: Book3S HV P9: Comment and fix MMU context switching code
KVM: PPC: Book3S HV P9: Test dawr_enabled() before saving host DAWR
SPRs
KVM: PPC: Book3S HV P9: Don't restore PSSCR if not needed
KVM: PPC: Book3S HV P9: Avoid tlbsync sequence on radix guest exit
KVM: PPC: Book3S HV Nested: Avoid extra mftb() in nested entry
KVM: PPC: Book3S HV P9: Improve mfmsr performance on entry
KVM: PPC: Book3S HV P9: Optimise hash guest SLB saving
arch/powerpc/include/asm/asm-prototypes.h | 5 -
arch/powerpc/include/asm/kvm_asm.h | 1 +
arch/powerpc/include/asm/kvm_book3s.h | 6 +
arch/powerpc/include/asm/kvm_book3s_64.h | 4 +-
arch/powerpc/include/asm/kvm_host.h | 5 +-
arch/powerpc/include/asm/switch_to.h | 2 +
arch/powerpc/include/asm/time.h | 19 +-
arch/powerpc/kernel/cpu_setup_power.c | 12 +-
arch/powerpc/kernel/dt_cpu_ftrs.c | 8 +-
arch/powerpc/kernel/process.c | 30 +
arch/powerpc/kernel/time.c | 54 +-
arch/powerpc/kvm/book3s_64_mmu_radix.c | 4 +
arch/powerpc/kvm/book3s_hv.c | 628 +++++++++----------
arch/powerpc/kvm/book3s_hv.h | 36 ++
arch/powerpc/kvm/book3s_hv_interrupts.S | 13 +-
arch/powerpc/kvm/book3s_hv_nested.c | 21 +-
arch/powerpc/kvm/book3s_hv_p9_entry.c | 725 +++++++++++++++++++---
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 74 +--
arch/powerpc/mm/book3s64/radix_pgtable.c | 15 -
arch/powerpc/perf/core-book3s.c | 7 +
arch/powerpc/platforms/powernv/idle.c | 10 +-
21 files changed, 1143 insertions(+), 536 deletions(-)
create mode 100644 arch/powerpc/kvm/book3s_hv.h
--
2.23.0
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 10:58:54
This register is not architected and not implemented in POWER9 or 10,
it just reads back zeroes for compatibility.
-78 cycles (9255) cycles POWER9 virt-mode NULL hcall
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 3 ---
arch/powerpc/platforms/powernv/idle.c | 2 --
2 files changed, 5 deletions(-)
@@ -667,7 +667,6 @@ static unsigned long power9_idle_stop(unsigned long psscr)sprs.purr=mfspr(SPRN_PURR);sprs.spurr=mfspr(SPRN_SPURR);sprs.dscr=mfspr(SPRN_DSCR);-sprs.wort=mfspr(SPRN_WORT);sprs.ciabr=mfspr(SPRN_CIABR);sprs.mmcra=mfspr(SPRN_MMCRA);
@@ -785,7 +784,6 @@ static unsigned long power9_idle_stop(unsigned long psscr)mtspr(SPRN_PURR,sprs.purr);mtspr(SPRN_SPURR,sprs.spurr);mtspr(SPRN_DSCR,sprs.dscr);-mtspr(SPRN_WORT,sprs.wort);mtspr(SPRN_CIABR,sprs.ciabr);mtspr(SPRN_MMCRA,sprs.mmcra);
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 10:59:19
The host Linux timer code arms the decrementer with the value
'decrementers_next_tb - current_tb' using set_dec(), which stores
val - 1 on Book3S-64, which is not quite the same as what KVM does
to re-arm the host decrementer when exiting the guest.
This shouldn't be a significant change, but it makes the logic match
and avoids this small extra change being brought into the next patch.
Suggested-by: Alexey Kardashevskiy <redacted>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
@@ -3914,7 +3914,7 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,vc->entry_exit_map=0x101;vc->in_guest=0;-mtspr(SPRN_DEC,local_paca->kvm_hstate.dec_expires-mftb());+set_dec(local_paca->kvm_hstate.dec_expires-mftb());/* We may have raced with new irq work */if(test_irq_work_pending())set_dec(1);
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 10:59:44
There is no need to save away the host DEC value, as it is derived
from the host timer subsystem which maintains the next timer time,
so it can be restored from there.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/time.h | 5 +++++
arch/powerpc/kernel/time.c | 1 +
arch/powerpc/kvm/book3s_hv.c | 14 +++++++-------
3 files changed, 13 insertions(+), 7 deletions(-)
@@ -3914,7 +3913,8 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,vc->entry_exit_map=0x101;vc->in_guest=0;-set_dec(local_paca->kvm_hstate.dec_expires-mftb());+next_timer=timer_get_next_tb();+set_dec(next_timer-mftb());/* We may have raced with new irq work */if(test_irq_work_pending())set_dec(1);
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:00:15
On processors that don't suppress the HDEC exceptions when LPCR[HDICE]=0,
this could help reduce needless guest exits due to leftover exceptions on
entering the guest.
Reviewed-by: Alexey Kardashevskiy <redacted>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/time.h | 2 ++
arch/powerpc/kernel/time.c | 1 +
arch/powerpc/kvm/book3s_hv_p9_entry.c | 3 ++-
3 files changed, 5 insertions(+), 1 deletion(-)
@@ -489,7 +489,8 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcvc->tb_offset_applied=0;}-mtspr(SPRN_HDEC,0x7fffffff);+/* HDEC must be at least as large as DEC, so decrementer_max fits */+mtspr(SPRN_HDEC,decrementer_max);save_clear_guest_mmu(kvm,vcpu);switch_mmu_to_host(kvm,host_pidr);
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:00:48
mftb is serialising (dispatch next-to-complete) so it is heavy weight
for a mfspr. Avoid reading it multiple times in the entry or exit paths.
A small number of cycles delay to timers is tolerable.
-118 cycles (9137) POWER9 virt-mode NULL hcall
Reviewed-by: Fabiano Rosas <redacted>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 4 ++--
arch/powerpc/kvm/book3s_hv_p9_entry.c | 5 +++--
2 files changed, 5 insertions(+), 4 deletions(-)
@@ -3914,7 +3914,7 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,vc->in_guest=0;next_timer=timer_get_next_tb();-set_dec(next_timer-mftb());+set_dec(next_timer-tb);/* We may have raced with new irq work */if(test_irq_work_pending())set_dec(1);
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:01:13
Rather than have KVM look up the host timer and fiddle with the
irq-work internal details, have the powerpc/time.c code provide a
function for KVM to re-arm the Linux timer code when exiting a
guest.
This is implementation has an improvement over existing code of
marking a decrementer interrupt as soft-pending if a timer has
expired, rather than setting DEC to a -ve value, which tended to
cause host timers to take two interrupts (first hdec to exit the
guest, then the immediate dec).
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/time.h | 16 +++-------
arch/powerpc/kernel/time.c | 52 +++++++++++++++++++++++++++------
arch/powerpc/kvm/book3s_hv.c | 7 ++---
3 files changed, 49 insertions(+), 26 deletions(-)
@@ -553,13 +563,44 @@ void arch_irq_work_raise(void)preempt_enable();}+staticvoidset_dec_or_work(u64val)+{+set_dec(val);+/* We may have raced with new irq work */+if(unlikely(test_irq_work_pending()))+set_dec(1);+}+#else /* CONFIG_IRQ_WORK */#define test_irq_work_pending() 0#define clear_irq_work_pending()+staticvoidset_dec_or_work(u64val)+{+set_dec(val);+}#endif /* CONFIG_IRQ_WORK */+#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE+voidtimer_rearm_host_dec(u64now)+{+u64*next_tb=this_cpu_ptr(&decrementers_next_tb);++WARN_ON_ONCE(!arch_irqs_disabled());+WARN_ON_ONCE(mfmsr()&MSR_EE);++if(now>=*next_tb){+local_paca->irq_happened|=PACA_IRQ_DEC;+}else{+now=*next_tb-now;+if(now<=decrementer_max)+set_dec_or_work(now);+}+}+EXPORT_SYMBOL_GPL(timer_rearm_host_dec);+#endif+/**timer_interrupt-getscalledwhenthedecrementeroverflows,*withinterruptsdisabled.
@@ -620,10 +661,7 @@ DEFINE_INTERRUPT_HANDLER_ASYNC(timer_interrupt)}else{now=*next_tb-now;if(now<=decrementer_max)-set_dec(now);-/* We may have raced with new irq work */-if(test_irq_work_pending())-set_dec(1);+set_dec_or_work(now);__this_cpu_inc(irq_stat.timer_irqs_others);}
@@ -865,11 +903,7 @@ static int decrementer_set_next_event(unsigned long evt,structclock_event_device*dev){__this_cpu_write(decrementers_next_tb,get_tb()+evt);-set_dec(evt);--/* We may have raced with new irq work */-if(test_irq_work_pending())-set_dec(1);+set_dec_or_work(evt);return0;}
@@ -3913,11 +3913,8 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,vc->entry_exit_map=0x101;vc->in_guest=0;-next_timer=timer_get_next_tb();-set_dec(next_timer-tb);-/* We may have raced with new irq work */-if(test_irq_work_pending())-set_dec(1);+timer_rearm_host_dec(tb);+mtspr(SPRN_SPRG_VDSO_WRITE,local_paca->sprg_vdso);kvmhv_load_host_pmu();
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:01:37
HV interrupts may be taken with the MMU enabled when radix guests are
running. Enable LPCR[HAIL] on ISA v3.1 processors for radix guests.
Make this depend on the host LPCR[HAIL] being enabled. Currently that is
always enabled, but having this test means any issue that might require
LPCR[HAIL] to be disabled in the host will not have to be duplicated in
KVM.
-1380 cycles on P10 NULL hcall entry+exit
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 29 +++++++++++++++++++++++++----
1 file changed, 25 insertions(+), 4 deletions(-)
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:02:01
This register controls supervisor SPR modifications, and as such is only
relevant for KVM. KVM always sets AMOR to ~0 on guest entry, and never
restores it coming back out to the host, so it can be kept constant and
avoid the mtSPR in KVM guest entry.
-21 cycles (9116) cycles POWER9 virt-mode NULL hcall
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/cpu_setup_power.c | 8 ++++++++
arch/powerpc/kernel/dt_cpu_ftrs.c | 2 ++
arch/powerpc/kvm/book3s_hv_p9_entry.c | 2 --
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 2 --
arch/powerpc/mm/book3s64/radix_pgtable.c | 15 ---------------
arch/powerpc/platforms/powernv/idle.c | 8 +++-----
6 files changed, 13 insertions(+), 24 deletions(-)
@@ -306,8 +306,8 @@ struct p7_sprs {/* per thread SPRs that get lost in shallow states */u64amr;u64iamr;-u64amor;u64uamor;+/* amor is restored to constant ~0 */};staticunsignedlongpower7_idle_insn(unsignedlongtype)
@@ -378,7 +378,6 @@ static unsigned long power7_idle_insn(unsigned long type)if(cpu_has_feature(CPU_FTR_ARCH_207S)){sprs.amr=mfspr(SPRN_AMR);sprs.iamr=mfspr(SPRN_IAMR);-sprs.amor=mfspr(SPRN_AMOR);sprs.uamor=mfspr(SPRN_UAMOR);}
@@ -397,7 +396,7 @@ static unsigned long power7_idle_insn(unsigned long type)*/mtspr(SPRN_AMR,sprs.amr);mtspr(SPRN_IAMR,sprs.iamr);-mtspr(SPRN_AMOR,sprs.amor);+mtspr(SPRN_AMOR,~0);mtspr(SPRN_UAMOR,sprs.uamor);}}
@@ -687,7 +686,6 @@ static unsigned long power9_idle_stop(unsigned long psscr)sprs.amr=mfspr(SPRN_AMR);sprs.iamr=mfspr(SPRN_IAMR);-sprs.amor=mfspr(SPRN_AMOR);sprs.uamor=mfspr(SPRN_UAMOR);srr1=isa300_idle_stop_mayloss(psscr);/* go idle */
@@ -708,7 +706,7 @@ static unsigned long power9_idle_stop(unsigned long psscr)*/mtspr(SPRN_AMR,sprs.amr);mtspr(SPRN_IAMR,sprs.iamr);-mtspr(SPRN_AMOR,sprs.amor);+mtspr(SPRN_AMOR,~0);mtspr(SPRN_UAMOR,sprs.uamor);/*
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:02:26
Revert the workaround added by commit 63279eeb7f93a ("KVM: PPC: Book3S
HV: Always save guest pmu for guest capable of nesting").
Nested capable guests running with the earlier commit ("KVM: PPC: Book3S
HV Nested: Indicate guest PMU in-use in VPA") will now indicate the PMU
in-use status of their guests, which means the parent does not need to
unconditionally save the PMU for nested capable guests.
This will cause the PMU to break for nested guests when running older
nested hypervisor guests under a kernel with this change. It's unclear
there's an easy way to avoid that, so this could wait for a release or
so for the fix to filter into stable kernels.
-134 cycles (8982) POWER9 virt-mode NULL hcall
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 2 --
1 file changed, 2 deletions(-)
@@ -3901,8 +3901,6 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,vcpu->arch.vpa.dirty=1;save_pmu=lp->pmcregs_in_use;}-/* Must save pmu if this guest is capable of running nested guests */-save_pmu|=nesting_enabled(vcpu->kvm);kvmhv_save_guest_pmu(vcpu,save_pmu);#ifdef CONFIG_PPC_PSERIES
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:02:55
KVM PMU management code looks for particular frozen/disabled bits in
the PMU registers so it knows whether it must clear them when coming
out of a guest or not. Setting this up helps KVM make these optimisations
without getting confused. Longer term the better approach might be to
move guest/host PMU switching to the perf subsystem.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/cpu_setup_power.c | 4 ++--
arch/powerpc/kernel/dt_cpu_ftrs.c | 6 +++---
arch/powerpc/kvm/book3s_hv.c | 5 +++++
arch/powerpc/perf/core-book3s.c | 7 +++++++
4 files changed, 17 insertions(+), 5 deletions(-)
@@ -2593,6 +2593,11 @@ static int kvmppc_core_vcpu_create_hv(struct kvm_vcpu *vcpu)#endif#endifvcpu->arch.mmcr[0]=MMCR0_FC;+if(cpu_has_feature(CPU_FTR_ARCH_31)){+vcpu->arch.mmcr[0]|=MMCR0_PMCCEXT;+vcpu->arch.mmcra=MMCRA_BHRB_DISABLE;+}+vcpu->arch.ctrl=CTRL_RUNLATCH;/* default to host PVR, since we can't spoof it */kvmppc_set_pvr_hv(vcpu,mfspr(SPRN_PVR));
@@ -3635,6 +3635,188 @@ static noinline void kvmppc_run_core(struct kvmppc_vcore *vc)trace_kvmppc_run_core(vc,1);}+/*+*Privileged(non-hypervisor)hostregisterstosave.+*/+structp9_host_os_sprs{+unsignedlongdscr;+unsignedlongtidr;+unsignedlongiamr;+unsignedlongamr;+unsignedlongfscr;++unsignedintpmc1;+unsignedintpmc2;+unsignedintpmc3;+unsignedintpmc4;+unsignedintpmc5;+unsignedintpmc6;+unsignedlongmmcr0;+unsignedlongmmcr1;+unsignedlongmmcr2;+unsignedlongmmcr3;+unsignedlongmmcra;+unsignedlongsiar;+unsignedlongsier1;+unsignedlongsier2;+unsignedlongsier3;+unsignedlongsdar;+};++staticvoidfreeze_pmu(unsignedlongmmcr0,unsignedlongmmcra)+{+if(!(mmcr0&MMCR0_FC))+gotodo_freeze;+if(mmcra&MMCRA_SAMPLE_ENABLE)+gotodo_freeze;+if(cpu_has_feature(CPU_FTR_ARCH_31)){+if(!(mmcr0&MMCR0_PMCCEXT))+gotodo_freeze;+if(!(mmcra&MMCRA_BHRB_DISABLE))+gotodo_freeze;+}+return;++do_freeze:+mmcr0=MMCR0_FC;+mmcra=0;+if(cpu_has_feature(CPU_FTR_ARCH_31)){+mmcr0|=MMCR0_PMCCEXT;+mmcra=MMCRA_BHRB_DISABLE;+}++mtspr(SPRN_MMCR0,mmcr0);+mtspr(SPRN_MMCRA,mmcra);+isync();+}++staticvoidsave_p9_host_pmu(structp9_host_os_sprs*host_os_sprs)+{+if(ppc_get_pmu_inuse()){+/*+*ItmightbebettertoputPMUhandling(atleastforthe+*host)intheperfsubsystembecauseitknowsmoreaboutwhat+*isbeingused.+*/++/* POWER9, POWER10 do not implement HPMC or SPMC */++host_os_sprs->mmcr0=mfspr(SPRN_MMCR0);+host_os_sprs->mmcra=mfspr(SPRN_MMCRA);++freeze_pmu(host_os_sprs->mmcr0,host_os_sprs->mmcra);++host_os_sprs->pmc1=mfspr(SPRN_PMC1);+host_os_sprs->pmc2=mfspr(SPRN_PMC2);+host_os_sprs->pmc3=mfspr(SPRN_PMC3);+host_os_sprs->pmc4=mfspr(SPRN_PMC4);+host_os_sprs->pmc5=mfspr(SPRN_PMC5);+host_os_sprs->pmc6=mfspr(SPRN_PMC6);+host_os_sprs->mmcr1=mfspr(SPRN_MMCR1);+host_os_sprs->mmcr2=mfspr(SPRN_MMCR2);+host_os_sprs->sdar=mfspr(SPRN_SDAR);+host_os_sprs->siar=mfspr(SPRN_SIAR);+host_os_sprs->sier1=mfspr(SPRN_SIER);++if(cpu_has_feature(CPU_FTR_ARCH_31)){+host_os_sprs->mmcr3=mfspr(SPRN_MMCR3);+host_os_sprs->sier2=mfspr(SPRN_SIER2);+host_os_sprs->sier3=mfspr(SPRN_SIER3);+}+}+}++staticvoidload_p9_guest_pmu(structkvm_vcpu*vcpu)+{+mtspr(SPRN_PMC1,vcpu->arch.pmc[0]);+mtspr(SPRN_PMC2,vcpu->arch.pmc[1]);+mtspr(SPRN_PMC3,vcpu->arch.pmc[2]);+mtspr(SPRN_PMC4,vcpu->arch.pmc[3]);+mtspr(SPRN_PMC5,vcpu->arch.pmc[4]);+mtspr(SPRN_PMC6,vcpu->arch.pmc[5]);+mtspr(SPRN_MMCR1,vcpu->arch.mmcr[1]);+mtspr(SPRN_MMCR2,vcpu->arch.mmcr[2]);+mtspr(SPRN_SDAR,vcpu->arch.sdar);+mtspr(SPRN_SIAR,vcpu->arch.siar);+mtspr(SPRN_SIER,vcpu->arch.sier[0]);++if(cpu_has_feature(CPU_FTR_ARCH_31)){+mtspr(SPRN_MMCR3,vcpu->arch.mmcr[4]);+mtspr(SPRN_SIER2,vcpu->arch.sier[1]);+mtspr(SPRN_SIER3,vcpu->arch.sier[2]);+}++/* Set MMCRA then MMCR0 last */+mtspr(SPRN_MMCRA,vcpu->arch.mmcra);+mtspr(SPRN_MMCR0,vcpu->arch.mmcr[0]);+/* No isync necessary because we're starting counters */+}++staticvoidsave_p9_guest_pmu(structkvm_vcpu*vcpu)+{+structlppaca*lp;+intsave_pmu=1;++lp=vcpu->arch.vpa.pinned_addr;+if(lp)+save_pmu=lp->pmcregs_in_use;++if(save_pmu){+vcpu->arch.mmcr[0]=mfspr(SPRN_MMCR0);+vcpu->arch.mmcra=mfspr(SPRN_MMCRA);++freeze_pmu(vcpu->arch.mmcr[0],vcpu->arch.mmcra);++vcpu->arch.pmc[0]=mfspr(SPRN_PMC1);+vcpu->arch.pmc[1]=mfspr(SPRN_PMC2);+vcpu->arch.pmc[2]=mfspr(SPRN_PMC3);+vcpu->arch.pmc[3]=mfspr(SPRN_PMC4);+vcpu->arch.pmc[4]=mfspr(SPRN_PMC5);+vcpu->arch.pmc[5]=mfspr(SPRN_PMC6);+vcpu->arch.mmcr[1]=mfspr(SPRN_MMCR1);+vcpu->arch.mmcr[2]=mfspr(SPRN_MMCR2);+vcpu->arch.sdar=mfspr(SPRN_SDAR);+vcpu->arch.siar=mfspr(SPRN_SIAR);+vcpu->arch.sier[0]=mfspr(SPRN_SIER);++if(cpu_has_feature(CPU_FTR_ARCH_31)){+vcpu->arch.mmcr[3]=mfspr(SPRN_MMCR3);+vcpu->arch.sier[1]=mfspr(SPRN_SIER2);+vcpu->arch.sier[2]=mfspr(SPRN_SIER3);+}+}else{+freeze_pmu(mfspr(SPRN_MMCR0),mfspr(SPRN_MMCRA));+}+}++staticvoidload_p9_host_pmu(structp9_host_os_sprs*host_os_sprs)+{+if(ppc_get_pmu_inuse()){+mtspr(SPRN_PMC1,host_os_sprs->pmc1);+mtspr(SPRN_PMC2,host_os_sprs->pmc2);+mtspr(SPRN_PMC3,host_os_sprs->pmc3);+mtspr(SPRN_PMC4,host_os_sprs->pmc4);+mtspr(SPRN_PMC5,host_os_sprs->pmc5);+mtspr(SPRN_PMC6,host_os_sprs->pmc6);+mtspr(SPRN_MMCR1,host_os_sprs->mmcr1);+mtspr(SPRN_MMCR2,host_os_sprs->mmcr2);+mtspr(SPRN_SDAR,host_os_sprs->sdar);+mtspr(SPRN_SIAR,host_os_sprs->siar);+mtspr(SPRN_SIER,host_os_sprs->sier1);++if(cpu_has_feature(CPU_FTR_ARCH_31)){+mtspr(SPRN_MMCR3,host_os_sprs->mmcr3);+mtspr(SPRN_SIER2,host_os_sprs->sier2);+mtspr(SPRN_SIER3,host_os_sprs->sier3);+}++/* Set MMCRA then MMCR0 last */+mtspr(SPRN_MMCRA,host_os_sprs->mmcra);+mtspr(SPRN_MMCR0,host_os_sprs->mmcr0);+isync();+}+}+staticvoidload_spr_state(structkvm_vcpu*vcpu){mtspr(SPRN_DSCR,vcpu->arch.dscr);
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:04:16
Rather than guest/host save/retsore functions, implement context switch
functions that take care of details like the VPA update for nested.
The reason to split these kind of helpers into explicit save/load
functions is mainly to schedule SPR access nicely, but PMU is a special
case where the load requires mtSPR (to stop counters) and other
difficulties, so there's less possibility to schedule those nicely. The
SPR accesses also have side-effects if the PMU is running, and in later
changes we keep the host PMU running as long as possible so this code
can be better profiled, which also complicates scheduling.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 51 ++++++++++++++++--------------------
1 file changed, 23 insertions(+), 28 deletions(-)
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:04:39
The pmcregs_in_use field in the guest VPA can not be trusted to reflect
what the guest is doing with PMU SPRs, so the PMU must always be managed
(stopped) when exiting the guest, and SPR values set when entering the
guest to ensure it can't cause a covert channel or otherwise cause other
guests or the host to misbehave.
So prevent guest access to the PMU with HFSCR[PM] if pmcregs_in_use is
clear, and avoid the PMU SPR access on every partition switch. Guests
that set pmcregs_in_use incorrectly or when first setting it and using
the PMU will take a hypervisor facility unavailable interrupt that will
bring in the PMU SPRs.
-774 cycles (7759) cycles POWER9 virt-mode NULL hcall
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kvm/book3s_hv.c | 122 ++++++++++++++++++++++------
arch/powerpc/kvm/book3s_hv_nested.c | 12 ++-
3 files changed, 105 insertions(+), 30 deletions(-)
@@ -819,6 +819,7 @@ struct kvm_vcpu_arch {/* For support of nested guests */structkvm_nested_guest*nested;u32nested_vcpu_id;+u64nested_hfscr;gpa_tnested_io_gpr;#endif
@@ -1734,6 +1754,19 @@ static int kvmppc_handle_nested_exit(struct kvm_vcpu *vcpu)srcu_read_unlock(&vcpu->kvm->srcu,srcu_idx);break;+caseBOOK3S_INTERRUPT_H_FAC_UNAVAIL:{+unsignedlongcause=vcpu->arch.hfscr>>56;++r=EMULATE_FAIL;+if(cause==FSCR_PM_LG&&(vcpu->arch.nested_hfscr&HFSCR_PM))+r=kvmppc_pmu_unavailable(vcpu);++if(r==EMULATE_FAIL)+r=RESUME_HOST;++break;+}+#ifdef CONFIG_PPC_TRANSACTIONAL_MEMcaseBOOK3S_INTERRUPT_HV_SOFTPATCH:/*
@@ -3693,6 +3726,17 @@ static void freeze_pmu(unsigned long mmcr0, unsigned long mmcra)staticvoidswitch_pmu_to_guest(structkvm_vcpu*vcpu,structp9_host_os_sprs*host_os_sprs){+structlppaca*lp;+intload_pmu=1;++lp=vcpu->arch.vpa.pinned_addr;+if(lp)+load_pmu=lp->pmcregs_in_use;++if(load_pmu)+vcpu->arch.hfscr|=HFSCR_PM;++/* Save host */if(ppc_get_pmu_inuse()){/**ItmightbebettertoputPMUhandling(atleastforthe
@@ -3737,29 +3781,31 @@ static void switch_pmu_to_guest(struct kvm_vcpu *vcpu,}#endif-/* load guest */-mtspr(SPRN_PMC1,vcpu->arch.pmc[0]);-mtspr(SPRN_PMC2,vcpu->arch.pmc[1]);-mtspr(SPRN_PMC3,vcpu->arch.pmc[2]);-mtspr(SPRN_PMC4,vcpu->arch.pmc[3]);-mtspr(SPRN_PMC5,vcpu->arch.pmc[4]);-mtspr(SPRN_PMC6,vcpu->arch.pmc[5]);-mtspr(SPRN_MMCR1,vcpu->arch.mmcr[1]);-mtspr(SPRN_MMCR2,vcpu->arch.mmcr[2]);-mtspr(SPRN_SDAR,vcpu->arch.sdar);-mtspr(SPRN_SIAR,vcpu->arch.siar);-mtspr(SPRN_SIER,vcpu->arch.sier[0]);+/* Load guest */+if(vcpu->arch.hfscr&HFSCR_PM){+mtspr(SPRN_PMC1,vcpu->arch.pmc[0]);+mtspr(SPRN_PMC2,vcpu->arch.pmc[1]);+mtspr(SPRN_PMC3,vcpu->arch.pmc[2]);+mtspr(SPRN_PMC4,vcpu->arch.pmc[3]);+mtspr(SPRN_PMC5,vcpu->arch.pmc[4]);+mtspr(SPRN_PMC6,vcpu->arch.pmc[5]);+mtspr(SPRN_MMCR1,vcpu->arch.mmcr[1]);+mtspr(SPRN_MMCR2,vcpu->arch.mmcr[2]);+mtspr(SPRN_SDAR,vcpu->arch.sdar);+mtspr(SPRN_SIAR,vcpu->arch.siar);+mtspr(SPRN_SIER,vcpu->arch.sier[0]);-if(cpu_has_feature(CPU_FTR_ARCH_31)){-mtspr(SPRN_MMCR3,vcpu->arch.mmcr[4]);-mtspr(SPRN_SIER2,vcpu->arch.sier[1]);-mtspr(SPRN_SIER3,vcpu->arch.sier[2]);-}+if(cpu_has_feature(CPU_FTR_ARCH_31)){+mtspr(SPRN_MMCR3,vcpu->arch.mmcr[4]);+mtspr(SPRN_SIER2,vcpu->arch.sier[1]);+mtspr(SPRN_SIER3,vcpu->arch.sier[2]);+}-/* Set MMCRA then MMCR0 last */-mtspr(SPRN_MMCRA,vcpu->arch.mmcra);-mtspr(SPRN_MMCR0,vcpu->arch.mmcr[0]);-/* No isync necessary because we're starting counters */+/* Set MMCRA then MMCR0 last */+mtspr(SPRN_MMCRA,vcpu->arch.mmcra);+mtspr(SPRN_MMCR0,vcpu->arch.mmcr[0]);+/* No isync necessary because we're starting counters */+}}staticvoidswitch_pmu_to_host(structkvm_vcpu*vcpu,
@@ -3795,9 +3841,31 @@ static void switch_pmu_to_host(struct kvm_vcpu *vcpu,vcpu->arch.sier[1]=mfspr(SPRN_SIER2);vcpu->arch.sier[2]=mfspr(SPRN_SIER3);}-}else{++}elseif(vcpu->arch.hfscr&HFSCR_PM){+/*+*TheguestaccessedPMCSPRswithoutspecifyingtheyshould+*bepreserved.Stopthemfromcountingiftheguesthad+*startedanything.+*/freeze_pmu(mfspr(SPRN_MMCR0),mfspr(SPRN_MMCRA));-}++/*+*Demand-faultPMUregisteraccessintheguest.+*+*Thisisusedtograbtheguest'sVPApmcregs_in_usevalue+*andreflectitintothehost'sVPAinthecaseofanested+*hypervisor.+*+*Italsoavoidshavingtozero-outSPRsaftereachguest+*exittoavoidside-channelswhen.+*+*Thisisclearedherewhenweexittheguest,solaterHFSCR+*interrupthandlingcanadditbacktoruntheguestwith+*PMenablednexttime.+*/+vcpu->arch.hfscr&=~HFSCR_PM;+}/* otherwise the PMU should still be frozen from guest entry */#ifdef CONFIG_PPC_PSERIESif(kvmhv_on_pseries())
@@ -161,9 +165,10 @@ static void sanitise_hv_regs(struct kvm_vcpu *vcpu, struct hv_guest_state *hr)/**Don'tletL1enablefeaturesforL2whichwe'vedisabledforL1,-*butpreservetheinterruptcausefield.+*butpreservetheinterruptcausefieldandfacilitiesthatmight+*bedisabledfordemandfaultingintheL1.*/-hr->hfscr&=(HFSCR_INTR_CAUSE|vcpu->arch.hfscr);+hr->hfscr&=(HFSCR_INTR_CAUSE|HFSCR_PM|vcpu->arch.hfscr);/* Don't let data address watchpoint match in hypervisor state */hr->dawrx0&=~DAWRX_HYP;
@@ -342,6 +347,7 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)/* set L1 state to L2 state */vcpu->arch.nested=l2;vcpu->arch.nested_vcpu_id=l2_hv.vcpu_token;+vcpu->arch.nested_hfscr=l2_hv.hfscr;vcpu->arch.regs=l2_regs;/* Guest must always run with ME enabled, HV disabled. */
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:05:02
Processors that support KVM HV do not require read-modify-write of
the CTRL SPR to set/clear their thread's runlatch. Just write 1 or 0
to it.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 2 +-
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 15 ++++++---------
2 files changed, 7 insertions(+), 10 deletions(-)
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:05:27
Move the SPR update into its relevant helper function. This will
help with SPR scheduling improvements in later changes.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:05:57
This reduces the number of mtmsrd required to enable facility bits when
saving/restoring registers, by having the KVM code set all bits up front
rather than using individual facility functions that set their particular
MSR bits.
-42 cycles (7803) POWER9 virt-mode NULL hcall
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/process.c | 24 +++++++++++
arch/powerpc/kvm/book3s_hv.c | 57 ++++++++++++++++++---------
arch/powerpc/kvm/book3s_hv_p9_entry.c | 1 +
3 files changed, 64 insertions(+), 18 deletions(-)
@@ -4010,8 +4011,23 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,if(next_timer<time_limit)time_limit=next_timer;+vcpu->arch.ceded=0;+save_p9_host_os_sprs(&host_os_sprs);+/* MSR bits may have been cleared by context switch */+msr=0;+if(IS_ENABLED(CONFIG_PPC_FPU))+msr|=MSR_FP;+if(cpu_has_feature(CPU_FTR_ALTIVEC))+msr|=MSR_VEC;+if(cpu_has_feature(CPU_FTR_VSX))+msr|=MSR_VSX;+if(cpu_has_feature(CPU_FTR_TM)||+cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))+msr|=MSR_TM;+msr=msr_check_and_set(msr);+kvmppc_subcore_enter_guest();vc->entry_exit_map=1;
@@ -4663,6 +4677,8 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit,gotodone;}+voidsave_user_regs_kvm(void);+staticintkvmppc_vcpu_run_hv(structkvm_vcpu*vcpu){structkvm_run*run=vcpu->run;
@@ -4672,19 +4688,24 @@ static int kvmppc_vcpu_run_hv(struct kvm_vcpu *vcpu)unsignedlonguser_tar=0;unsignedintuser_vrsave;structkvm*kvm;+unsignedlongmsr;if(!vcpu->arch.sane){run->exit_reason=KVM_EXIT_INTERNAL_ERROR;return-EINVAL;}+/* No need to go into the guest when all we'll do is come back out */+if(signal_pending(current)){+run->exit_reason=KVM_EXIT_INTR;+return-EINTR;+}++#ifdef CONFIG_PPC_TRANSACTIONAL_MEM/**Don'tallowentrywithasuspendedtransaction,because*theguestentry/exitcodewillloseit.-*IftheguesthasTMenabled,saveawaytheirTM-relatedSPRs-*(theywillgetrestoredbytheTMunavailableinterrupt).*/-#ifdef CONFIG_PPC_TRANSACTIONAL_MEMif(cpu_has_feature(CPU_FTR_TM)&¤t->thread.regs&&(current->thread.regs->msr&MSR_TM)){if(MSR_TM_ACTIVE(current->thread.regs->msr)){
@@ -4692,12 +4713,6 @@ static int kvmppc_vcpu_run_hv(struct kvm_vcpu *vcpu)run->fail_entry.hardware_entry_failure_reason=0;return-EINVAL;}-/* Enable TM so we can read the TM SPRs */-mtmsr(mfmsr()|MSR_TM);-current->thread.tm_tfhar=mfspr(SPRN_TFHAR);-current->thread.tm_tfiar=mfspr(SPRN_TFIAR);-current->thread.tm_texasr=mfspr(SPRN_TEXASR);-current->thread.regs->msr&=~MSR_TM;}#endif
@@ -4712,18 +4727,24 @@ static int kvmppc_vcpu_run_hv(struct kvm_vcpu *vcpu)kvmppc_core_prepare_to_enter(vcpu);-/* No need to go into the guest when all we'll do is come back out */-if(signal_pending(current)){-run->exit_reason=KVM_EXIT_INTR;-return-EINTR;-}-kvm=vcpu->kvm;atomic_inc(&kvm->arch.vcpus_running);/* Order vcpus_running vs. mmu_ready, see kvmppc_alloc_reset_hpt */smp_mb();-flush_all_to_thread(current);+msr=0;+if(IS_ENABLED(CONFIG_PPC_FPU))+msr|=MSR_FP;+if(cpu_has_feature(CPU_FTR_ALTIVEC))+msr|=MSR_VEC;+if(cpu_has_feature(CPU_FTR_VSX))+msr|=MSR_VSX;+if(cpu_has_feature(CPU_FTR_TM)||+cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))+msr|=MSR_TM;+msr=msr_check_and_set(msr);++save_user_regs_kvm();/* Save userspace EBB and other register values */if(cpu_has_feature(CPU_FTR_ARCH_207S)){
@@ -224,6 +224,7 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcvc->tb_offset_applied=vc->tb_offset;}+/* Could avoid mfmsr by passing around, but probably no big deal */msr=mfmsr();host_hfscr=mfspr(SPRN_HFSCR);
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:06:21
Moving the mtmsrd after the host SPRs are saved and before the guest
SPRs start to be loaded can prevent an SPR scoreboard stall (because
the mtmsrd is L=1 type which does not cause context synchronisation.
This is also now more convenient to combined with the mtmsrd L=0
instruction to enable facilities just below, but that is not done yet.
-12 cycles (7791) POWER9 virt-mode NULL hcall
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 23 ++++++++++++++++++-----
1 file changed, 18 insertions(+), 5 deletions(-)
@@ -4015,6 +4015,18 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,save_p9_host_os_sprs(&host_os_sprs);+/*+*ThiscouldbecombinedwithMSR[RI]clearing,butthatexpands+*theunrecoverablewindow.Itwouldbebettertocoverunrecoverable+*withKVMbadinterrupthandlingratherthanuseMSR[RI]atall.+*+*MuchmoredifficultandlessworthwhiletocombinewithIR/DR+*disable.+*/+hard_irq_disable();+if(lazy_irq_pending())+return0;+/* MSR bits may have been cleared by context switch */msr=0;if(IS_ENABLED(CONFIG_PPC_FPU))
@@ -4512,6 +4524,7 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit,structkvmppc_vcore*vc;structkvm*kvm=vcpu->kvm;structkvm_nested_guest*nested=vcpu->arch.nested;+unsignedlongflags;trace_kvmppc_run_vcpu_enter(vcpu);
@@ -4555,11 +4568,11 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit,if(kvm_is_radix(kvm))kvmppc_prepare_radix_vcpu(vcpu,pcpu);-local_irq_disable();-hard_irq_disable();+/* flags save not required, but irq_pmu has no disable/enable API */+powerpc_local_irq_pmu_save(flags);if(signal_pending(current))gotosigpend;-if(lazy_irq_pending()||need_resched()||!kvm->arch.mmu_ready)+if(need_resched()||!kvm->arch.mmu_ready)gotoout;if(!nested){
@@ -4614,7 +4627,7 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit,guest_exit_irqoff();-local_irq_enable();+powerpc_local_irq_pmu_restore(flags);cpumask_clear_cpu(pcpu,&kvm->arch.cpu_in_guest);
@@ -4672,7 +4685,7 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit,run->exit_reason=KVM_EXIT_INTR;vcpu->arch.ret=-EINTR;out:-local_irq_enable();+powerpc_local_irq_pmu_restore(flags);preempt_enable();gotodone;}
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:06:44
Small cleanup makes it a bit easier to match up entry and exit
operations.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 11 +++++++++--
1 file changed, 9 insertions(+), 2 deletions(-)
@@ -2948,6 +2948,13 @@ static void kvmppc_start_thread(struct kvm_vcpu *vcpu, struct kvmppc_vcore *vc)kvmppc_ipi_thread(cpu);}+/* Old path does this in asm */+staticvoidkvmppc_stop_thread(structkvm_vcpu*vcpu)+{+vcpu->cpu=-1;+vcpu->arch.thread_cpu=-1;+}+staticvoidkvmppc_wait_for_nap(intn_threads){intcpu=smp_processor_id();
@@ -403,6 +403,12 @@ static inline ulong kvmppc_get_fault_dar(struct kvm_vcpu *vcpu)returnvcpu->arch.fault_dar;}+/* Expiry time of vcpu DEC relative to host TB */+staticinlineu64kvmppc_dec_expires_host_tb(structkvm_vcpu*vcpu)+{+returnvcpu->arch.dec_expires-vcpu->arch.vcore->tb_offset;+}+staticinlineboolis_kvmppc_resume_guest(intr){return(r==RESUME_GUEST||r==RESUME_GUEST_NV);
@@ -3258,7 +3256,7 @@ static void post_guest_process(struct kvmppc_vcore *vc, bool is_master)*/spin_unlock(&vc->lock);/* cancel pending dec exception if dec is positive */-if(now<vcpu->arch.dec_expires&&+if(now<kvmppc_dec_expires_host_tb(vcpu)&&kvmppc_core_pending_dec(vcpu))kvmppc_core_dequeue_dec(vcpu);
@@ -4118,6 +4119,12 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,vcpu->arch.psscr=mfspr(SPRN_PSSCR_PR);mtspr(SPRN_PSSCR_PR,host_psscr);+dec=mfspr(SPRN_DEC);+if(!(lpcr&LPCR_LD))/* Sign extend if not using large decrementer */+dec=(s32)dec;+tb=mftb();+vcpu->arch.dec_expires=dec+(tb+vc->tb_offset);+/* H_CEDE has to be handled now, not later */if(trap==BOOK3S_INTERRUPT_SYSCALL&&!vcpu->arch.nested&&kvmppc_get_gpr(vcpu,3)==H_CEDE){
@@ -4156,12 +4164,6 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,vcpu->arch.slb_max=0;}-dec=mfspr(SPRN_DEC);-if(!(lpcr&LPCR_LD))/* Sign extend if not using large decrementer */-dec=(s32)dec;-tb=mftb();-vcpu->arch.dec_expires=dec+tb;-store_spr_state(vcpu);restore_p9_host_os_sprs(vcpu,&host_os_sprs);
@@ -4646,7 +4648,7 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit,*byL2andtheL1decrementerisprovidedinhdec_expires*/if(kvmppc_core_pending_dec(vcpu)&&-((get_tb()<vcpu->arch.dec_expires)||+((get_tb()<kvmppc_dec_expires_host_tb(vcpu))||(trap==BOOK3S_INTERRUPT_SYSCALL&&kvmppc_get_gpr(vcpu,3)==H_ENTER_NESTED)))kvmppc_core_dequeue_dec(vcpu);
@@ -343,6 +343,7 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)/* convert TB values/offsets to host (L0) values */hdec_exp=l2_hv.hdec_expiry-vc->tb_offset;vc->tb_offset+=l2_hv.tb_offset;+vcpu->arch.dec_expires+=l2_hv.tb_offset;/* set L1 state to L2 state */vcpu->arch.nested=l2;
@@ -384,6 +385,8 @@ long kvmhv_enter_nested_guest(struct kvm_vcpu *vcpu)if(l2_regs.msr&MSR_TS_MASK)vcpu->arch.shregs.msr|=MSR_TS_S;vc->tb_offset=saved_l1_hv.tb_offset;+/* XXX: is this always the same delta as saved_l1_hv.tb_offset? */+vcpu->arch.dec_expires-=l2_hv.tb_offset;restore_hv_regs(vcpu,&saved_l1_hv);vcpu->arch.purr+=delta_purr;vcpu->arch.spurr+=delta_spurr;
@@ -188,7 +188,7 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcstructkvm*kvm=vcpu->kvm;structkvm_nested_guest*nested=vcpu->arch.nested;structkvmppc_vcore*vc=vcpu->arch.vcore;-s64hdec;+s64hdec,dec;u64tb,purr,spurr;u64*exsave;boolri_set;
@@ -317,6 +317,8 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpc*/mtspr(SPRN_HDEC,hdec);+mtspr(SPRN_DEC,vcpu->arch.dec_expires-tb);+mtspr(SPRN_DAR,vcpu->arch.shregs.dar);mtspr(SPRN_DSISR,vcpu->arch.shregs.dsisr);mtspr(SPRN_SRR0,vcpu->arch.shregs.srr0);
@@ -446,6 +448,12 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcvcpu->arch.shregs.sprg2=mfspr(SPRN_SPRG2);vcpu->arch.shregs.sprg3=mfspr(SPRN_SPRG3);+dec=mfspr(SPRN_DEC);+if(!(lpcr&LPCR_LD))/* Sign extend if not using large decrementer */+dec=(s32)dec;+tb=mftb();+vcpu->arch.dec_expires=dec+tb;+/* Preserve PSSCR[FAKE_SUSPEND] until we've called kvmppc_save_tm_hv */mtspr(SPRN_PSSCR,host_psscr|(local_paca->kvm_hstate.fake_suspend<<PSSCR_FAKE_SUSPEND_LG));
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:07:31
Move the TB updates between saving and loading guest and host SPRs,
to improve scheduling by keeping issue-NTC operations together as
much as possible.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv_p9_entry.c | 36 +++++++++++++--------------
1 file changed, 18 insertions(+), 18 deletions(-)
@@ -215,15 +215,6 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcvcpu->arch.ceded=0;-if(vc->tb_offset){-u64new_tb=tb+vc->tb_offset;-mtspr(SPRN_TBU40,new_tb);-tb=mftb();-if((tb&0xffffff)<(new_tb&0xffffff))-mtspr(SPRN_TBU40,new_tb+0x1000000);-vc->tb_offset_applied=vc->tb_offset;-}-/* Could avoid mfmsr by passing around, but probably no big deal */msr=mfmsr();
@@ -238,6 +229,15 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpchost_dawrx1=mfspr(SPRN_DAWRX1);}+if(vc->tb_offset){+u64new_tb=tb+vc->tb_offset;+mtspr(SPRN_TBU40,new_tb);+tb=mftb();+if((tb&0xffffff)<(new_tb&0xffffff))+mtspr(SPRN_TBU40,new_tb+0x1000000);+vc->tb_offset_applied=vc->tb_offset;+}+if(vc->pcr)mtspr(SPRN_PCR,vc->pcr|PCR_MASK);mtspr(SPRN_DPDES,vc->dpdes);
@@ -454,6 +454,15 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpctb=mftb();vcpu->arch.dec_expires=dec+tb;+if(vc->tb_offset_applied){+u64new_tb=tb-vc->tb_offset_applied;+mtspr(SPRN_TBU40,new_tb);+tb=mftb();+if((tb&0xffffff)<(new_tb&0xffffff))+mtspr(SPRN_TBU40,new_tb+0x1000000);+vc->tb_offset_applied=0;+}+/* Preserve PSSCR[FAKE_SUSPEND] until we've called kvmppc_save_tm_hv */mtspr(SPRN_PSSCR,host_psscr|(local_paca->kvm_hstate.fake_suspend<<PSSCR_FAKE_SUSPEND_LG));
@@ -488,15 +497,6 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcif(vc->pcr)mtspr(SPRN_PCR,PCR_MASK);-if(vc->tb_offset_applied){-u64new_tb=mftb()-vc->tb_offset_applied;-mtspr(SPRN_TBU40,new_tb);-tb=mftb();-if((tb&0xffffff)<(new_tb&0xffffff))-mtspr(SPRN_TBU40,new_tb+0x1000000);-vc->tb_offset_applied=0;-}-/* HDEC must be at least as large as DEC, so decrementer_max fits */mtspr(SPRN_HDEC,decrementer_max);
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:08:02
Reduce the number of mfTB executed by passing the current timebase
around entry and exit code rather than read it multiple times.
-213 cycles (7578) POWER9 virt-mode NULL hcall
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/kvm_book3s_64.h | 2 +-
arch/powerpc/kvm/book3s_hv.c | 88 +++++++++++++-----------
arch/powerpc/kvm/book3s_hv_p9_entry.c | 33 +++++----
3 files changed, 65 insertions(+), 58 deletions(-)
@@ -4122,8 +4121,8 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,dec=mfspr(SPRN_DEC);if(!(lpcr&LPCR_LD))/* Sign extend if not using large decrementer */dec=(s32)dec;-tb=mftb();-vcpu->arch.dec_expires=dec+(tb+vc->tb_offset);+*tb=mftb();+vcpu->arch.dec_expires=dec+(*tb+vc->tb_offset);/* H_CEDE has to be handled now, not later */if(trap==BOOK3S_INTERRUPT_SYSCALL&&!vcpu->arch.nested&&
@@ -4428,7 +4427,7 @@ static int kvmppc_run_vcpu(struct kvm_vcpu *vcpu)if((vc->vcore_state==VCORE_PIGGYBACK||vc->vcore_state==VCORE_RUNNING)&&!VCORE_IS_EXITING(vc)){-kvmppc_create_dtl_entry(vcpu,vc);+kvmppc_create_dtl_entry(vcpu,vc,mftb());kvmppc_start_thread(vcpu,vc);trace_kvm_guest_enter(vcpu);}elseif(vc->vcore_state==VCORE_SLEEPING){
@@ -4463,7 +4462,7 @@ static int kvmppc_run_vcpu(struct kvm_vcpu *vcpu)for_each_runnable_thread(i,v,vc){kvmppc_core_prepare_to_enter(v);if(signal_pending(v->arch.run_task)){-kvmppc_remove_runnable(vc,v);+kvmppc_remove_runnable(vc,v,mftb());v->stat.signal_exits++;v->run->exit_reason=KVM_EXIT_INTR;v->arch.ret=-EINTR;
@@ -4504,7 +4503,7 @@ static int kvmppc_run_vcpu(struct kvm_vcpu *vcpu)kvmppc_vcore_end_preempt(vc);if(vcpu->arch.state==KVMPPC_VCPU_RUNNABLE){-kvmppc_remove_runnable(vc,vcpu);+kvmppc_remove_runnable(vc,vcpu,mftb());vcpu->stat.signal_exits++;run->exit_reason=KVM_EXIT_INTR;vcpu->arch.ret=-EINTR;
@@ -4532,6 +4531,7 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit,structkvm*kvm=vcpu->kvm;structkvm_nested_guest*nested=vcpu->arch.nested;unsignedlongflags;+u64tb;trace_kvmppc_run_vcpu_enter(vcpu);
@@ -4542,7 +4542,6 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit,vc=vcpu->arch.vcore;vcpu->arch.ceded=0;vcpu->arch.run_task=current;-vcpu->arch.stolen_logged=vcore_stolen_time(vc,mftb());vcpu->arch.state=KVMPPC_VCPU_RUNNABLE;vcpu->arch.busy_preempt=TB_NIL;vcpu->arch.last_inst=KVM_INST_FETCH_FAILED;
@@ -4567,7 +4566,6 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit,kvmppc_update_vpas(vcpu);init_vcore_to_run(vc);-vc->preempt_tb=TB_NIL;preempt_disable();pcpu=smp_processor_id();
@@ -4577,6 +4575,7 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit,/* flags save not required, but irq_pmu has no disable/enable API */powerpc_local_irq_pmu_save(flags);+if(signal_pending(current))gotosigpend;if(need_resched()||!kvm->arch.mmu_ready)
@@ -4599,12 +4598,17 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit,gotoout;}+tb=mftb();++vcpu->arch.stolen_logged=vcore_stolen_time(vc,tb);+vc->preempt_tb=TB_NIL;+kvmppc_clear_host_core(pcpu);local_paca->kvm_hstate.napping=0;local_paca->kvm_hstate.kvm_split_mode=NULL;kvmppc_start_thread(vcpu,vc);-kvmppc_create_dtl_entry(vcpu,vc);+kvmppc_create_dtl_entry(vcpu,vc,tb);trace_kvm_guest_enter(vcpu);vc->vcore_state=VCORE_RUNNING;
@@ -4619,7 +4623,7 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit,/* Tell lockdep that we're about to enable interrupts */trace_hardirqs_on();-trap=kvmhv_p9_guest_entry(vcpu,time_limit,lpcr);+trap=kvmhv_p9_guest_entry(vcpu,time_limit,lpcr,&tb);vcpu->arch.trap=trap;trace_hardirqs_off();
@@ -4648,7 +4652,7 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit,*byL2andtheL1decrementerisprovidedinhdec_expires*/if(kvmppc_core_pending_dec(vcpu)&&-((get_tb()<kvmppc_dec_expires_host_tb(vcpu))||+((tb<kvmppc_dec_expires_host_tb(vcpu))||(trap==BOOK3S_INTERRUPT_SYSCALL&&kvmppc_get_gpr(vcpu,3)==H_ENTER_NESTED)))kvmppc_core_dequeue_dec(vcpu);
@@ -4684,7 +4688,7 @@ int kvmhv_run_single_vcpu(struct kvm_vcpu *vcpu, u64 time_limit,trace_kvmppc_run_core(vc,1);done:-kvmppc_remove_runnable(vc,vcpu);+kvmppc_remove_runnable(vc,vcpu,tb);trace_kvmppc_run_vcpu_exit(vcpu);returnvcpu->arch.ret;
@@ -203,8 +203,7 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcunsignedlonghost_dawr1;unsignedlonghost_dawrx1;-tb=mftb();-hdec=time_limit-tb;+hdec=time_limit-*tb;if(hdec<0)returnBOOK3S_INTERRUPT_HV_DECREMENTER;
@@ -230,11 +229,13 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpc}if(vc->tb_offset){-u64new_tb=tb+vc->tb_offset;+u64new_tb=*tb+vc->tb_offset;mtspr(SPRN_TBU40,new_tb);-tb=mftb();-if((tb&0xffffff)<(new_tb&0xffffff))-mtspr(SPRN_TBU40,new_tb+0x1000000);+if((mftb()&0xffffff)<(new_tb&0xffffff)){+new_tb+=0x1000000;+mtspr(SPRN_TBU40,new_tb);+}+*tb=new_tb;vc->tb_offset_applied=vc->tb_offset;}
@@ -317,7 +318,7 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpc*/mtspr(SPRN_HDEC,hdec);-mtspr(SPRN_DEC,vcpu->arch.dec_expires-tb);+mtspr(SPRN_DEC,vcpu->arch.dec_expires-*tb);mtspr(SPRN_DAR,vcpu->arch.shregs.dar);mtspr(SPRN_DSISR,vcpu->arch.shregs.dsisr);
@@ -451,15 +452,17 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcdec=mfspr(SPRN_DEC);if(!(lpcr&LPCR_LD))/* Sign extend if not using large decrementer */dec=(s32)dec;-tb=mftb();-vcpu->arch.dec_expires=dec+tb;+*tb=mftb();+vcpu->arch.dec_expires=dec+*tb;if(vc->tb_offset_applied){-u64new_tb=tb-vc->tb_offset_applied;+u64new_tb=*tb-vc->tb_offset_applied;mtspr(SPRN_TBU40,new_tb);-tb=mftb();-if((tb&0xffffff)<(new_tb&0xffffff))-mtspr(SPRN_TBU40,new_tb+0x1000000);+if((mftb()&0xffffff)<(new_tb&0xffffff)){+new_tb+=0x1000000;+mtspr(SPRN_TBU40,new_tb);+}+*tb=new_tb;vc->tb_offset_applied=0;}
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:08:26
Keep better track of the current SPR value in places where
they are to be loaded with a new context, to reduce expensive
mtSPR operations.
-73 cycles (7354) POWER9 virt-mode NULL hcall
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 64 ++++++++++++++++++++++--------------
1 file changed, 39 insertions(+), 25 deletions(-)
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:08:55
This juggles SPR switching on the entry and exit sides to be more
symmetric, which makes the next refactoring patch possible with no
functional change.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
@@ -228,6 +228,9 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpchost_dawrx1=mfspr(SPRN_DAWRX1);}+local_paca->kvm_hstate.host_purr=mfspr(SPRN_PURR);+local_paca->kvm_hstate.host_spurr=mfspr(SPRN_SPURR);+if(vc->tb_offset){u64new_tb=*tb+vc->tb_offset;mtspr(SPRN_TBU40,new_tb);
@@ -244,8 +247,6 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcmtspr(SPRN_DPDES,vc->dpdes);mtspr(SPRN_VTB,vc->vtb);-local_paca->kvm_hstate.host_purr=mfspr(SPRN_PURR);-local_paca->kvm_hstate.host_spurr=mfspr(SPRN_SPURR);mtspr(SPRN_PURR,vcpu->arch.purr);mtspr(SPRN_SPURR,vcpu->arch.spurr);
@@ -433,10 +434,8 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpc/* Advance host PURR/SPURR by the amount used by guest */purr=mfspr(SPRN_PURR);spurr=mfspr(SPRN_SPURR);-mtspr(SPRN_PURR,local_paca->kvm_hstate.host_purr+-purr-vcpu->arch.purr);-mtspr(SPRN_SPURR,local_paca->kvm_hstate.host_spurr+-spurr-vcpu->arch.spurr);+local_paca->kvm_hstate.host_purr+=purr-vcpu->arch.purr;+local_paca->kvm_hstate.host_spurr+=spurr-vcpu->arch.spurr;vcpu->arch.purr=purr;vcpu->arch.spurr=spurr;
@@ -449,6 +448,9 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcvcpu->arch.shregs.sprg2=mfspr(SPRN_SPRG2);vcpu->arch.shregs.sprg3=mfspr(SPRN_SPRG3);+vc->dpdes=mfspr(SPRN_DPDES);+vc->vtb=mfspr(SPRN_VTB);+dec=mfspr(SPRN_DEC);if(!(lpcr&LPCR_LD))/* Sign extend if not using large decrementer */dec=(s32)dec;
@@ -466,6 +468,9 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcvc->tb_offset_applied=0;}+mtspr(SPRN_PURR,local_paca->kvm_hstate.host_purr);+mtspr(SPRN_SPURR,local_paca->kvm_hstate.host_spurr);+/* Preserve PSSCR[FAKE_SUSPEND] until we've called kvmppc_save_tm_hv */mtspr(SPRN_PSSCR,host_psscr|(local_paca->kvm_hstate.fake_suspend<<PSSCR_FAKE_SUSPEND_LG));
@@ -494,8 +499,6 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcif(cpu_has_feature(CPU_FTR_ARCH_31))asmvolatile(PPC_CP_ABORT);-vc->dpdes=mfspr(SPRN_DPDES);-vc->vtb=mfspr(SPRN_VTB);mtspr(SPRN_DPDES,0);if(vc->pcr)mtspr(SPRN_PCR,PCR_MASK);
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:09:42
This should be no functional difference but makes the caller easier
to read.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 55 +++++++++++++++++++++---------------
1 file changed, 33 insertions(+), 22 deletions(-)
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:10:14
Move the P9 guest/host register switching functions to the built-in
P9 entry code, and export it for nested to use as well.
This allows more flexibility in scheduling these supervisor privileged
SPR accesses with the HV privileged and PR SPR accesses in the low level
entry code.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 351 +-------------------------
arch/powerpc/kvm/book3s_hv.h | 39 +++
arch/powerpc/kvm/book3s_hv_p9_entry.c | 332 ++++++++++++++++++++++++
3 files changed, 372 insertions(+), 350 deletions(-)
create mode 100644 arch/powerpc/kvm/book3s_hv.h
@@ -3675,356 +3676,6 @@ static noinline void kvmppc_run_core(struct kvmppc_vcore *vc)trace_kvmppc_run_core(vc,1);}-/*-*Privileged(non-hypervisor)hostregisterstosave.-*/-structp9_host_os_sprs{-unsignedlongdscr;-unsignedlongtidr;-unsignedlongiamr;-unsignedlongamr;-unsignedlongfscr;--unsignedintpmc1;-unsignedintpmc2;-unsignedintpmc3;-unsignedintpmc4;-unsignedintpmc5;-unsignedintpmc6;-unsignedlongmmcr0;-unsignedlongmmcr1;-unsignedlongmmcr2;-unsignedlongmmcr3;-unsignedlongmmcra;-unsignedlongsiar;-unsignedlongsier1;-unsignedlongsier2;-unsignedlongsier3;-unsignedlongsdar;-};--staticvoidfreeze_pmu(unsignedlongmmcr0,unsignedlongmmcra)-{-if(!(mmcr0&MMCR0_FC))-gotodo_freeze;-if(mmcra&MMCRA_SAMPLE_ENABLE)-gotodo_freeze;-if(cpu_has_feature(CPU_FTR_ARCH_31)){-if(!(mmcr0&MMCR0_PMCCEXT))-gotodo_freeze;-if(!(mmcra&MMCRA_BHRB_DISABLE))-gotodo_freeze;-}-return;--do_freeze:-mmcr0=MMCR0_FC;-mmcra=0;-if(cpu_has_feature(CPU_FTR_ARCH_31)){-mmcr0|=MMCR0_PMCCEXT;-mmcra=MMCRA_BHRB_DISABLE;-}--mtspr(SPRN_MMCR0,mmcr0);-mtspr(SPRN_MMCRA,mmcra);-isync();-}--staticvoidswitch_pmu_to_guest(structkvm_vcpu*vcpu,-structp9_host_os_sprs*host_os_sprs)-{-structlppaca*lp;-intload_pmu=1;--lp=vcpu->arch.vpa.pinned_addr;-if(lp)-load_pmu=lp->pmcregs_in_use;--if(load_pmu)-vcpu->arch.hfscr|=HFSCR_PM;--/* Save host */-if(ppc_get_pmu_inuse()){-/*-*ItmightbebettertoputPMUhandling(atleastforthe-*host)intheperfsubsystembecauseitknowsmoreaboutwhat-*isbeingused.-*/--/* POWER9, POWER10 do not implement HPMC or SPMC */--host_os_sprs->mmcr0=mfspr(SPRN_MMCR0);-host_os_sprs->mmcra=mfspr(SPRN_MMCRA);--freeze_pmu(host_os_sprs->mmcr0,host_os_sprs->mmcra);--host_os_sprs->pmc1=mfspr(SPRN_PMC1);-host_os_sprs->pmc2=mfspr(SPRN_PMC2);-host_os_sprs->pmc3=mfspr(SPRN_PMC3);-host_os_sprs->pmc4=mfspr(SPRN_PMC4);-host_os_sprs->pmc5=mfspr(SPRN_PMC5);-host_os_sprs->pmc6=mfspr(SPRN_PMC6);-host_os_sprs->mmcr1=mfspr(SPRN_MMCR1);-host_os_sprs->mmcr2=mfspr(SPRN_MMCR2);-host_os_sprs->sdar=mfspr(SPRN_SDAR);-host_os_sprs->siar=mfspr(SPRN_SIAR);-host_os_sprs->sier1=mfspr(SPRN_SIER);--if(cpu_has_feature(CPU_FTR_ARCH_31)){-host_os_sprs->mmcr3=mfspr(SPRN_MMCR3);-host_os_sprs->sier2=mfspr(SPRN_SIER2);-host_os_sprs->sier3=mfspr(SPRN_SIER3);-}-}--#ifdef CONFIG_PPC_PSERIES-if(kvmhv_on_pseries()){-if(vcpu->arch.vpa.pinned_addr){-structlppaca*lp=vcpu->arch.vpa.pinned_addr;-get_lppaca()->pmcregs_in_use=lp->pmcregs_in_use;-}else{-get_lppaca()->pmcregs_in_use=1;-}-}-#endif--/* Load guest */-if(vcpu->arch.hfscr&HFSCR_PM){-mtspr(SPRN_PMC1,vcpu->arch.pmc[0]);-mtspr(SPRN_PMC2,vcpu->arch.pmc[1]);-mtspr(SPRN_PMC3,vcpu->arch.pmc[2]);-mtspr(SPRN_PMC4,vcpu->arch.pmc[3]);-mtspr(SPRN_PMC5,vcpu->arch.pmc[4]);-mtspr(SPRN_PMC6,vcpu->arch.pmc[5]);-mtspr(SPRN_MMCR1,vcpu->arch.mmcr[1]);-mtspr(SPRN_MMCR2,vcpu->arch.mmcr[2]);-mtspr(SPRN_SDAR,vcpu->arch.sdar);-mtspr(SPRN_SIAR,vcpu->arch.siar);-mtspr(SPRN_SIER,vcpu->arch.sier[0]);--if(cpu_has_feature(CPU_FTR_ARCH_31)){-mtspr(SPRN_MMCR3,vcpu->arch.mmcr[4]);-mtspr(SPRN_SIER2,vcpu->arch.sier[1]);-mtspr(SPRN_SIER3,vcpu->arch.sier[2]);-}--/* Set MMCRA then MMCR0 last */-mtspr(SPRN_MMCRA,vcpu->arch.mmcra);-mtspr(SPRN_MMCR0,vcpu->arch.mmcr[0]);-/* No isync necessary because we're starting counters */-}-}--staticvoidswitch_pmu_to_host(structkvm_vcpu*vcpu,-structp9_host_os_sprs*host_os_sprs)-{-structlppaca*lp;-intsave_pmu=1;--lp=vcpu->arch.vpa.pinned_addr;-if(lp)-save_pmu=lp->pmcregs_in_use;--if(save_pmu){-vcpu->arch.mmcr[0]=mfspr(SPRN_MMCR0);-vcpu->arch.mmcra=mfspr(SPRN_MMCRA);--freeze_pmu(vcpu->arch.mmcr[0],vcpu->arch.mmcra);--vcpu->arch.pmc[0]=mfspr(SPRN_PMC1);-vcpu->arch.pmc[1]=mfspr(SPRN_PMC2);-vcpu->arch.pmc[2]=mfspr(SPRN_PMC3);-vcpu->arch.pmc[3]=mfspr(SPRN_PMC4);-vcpu->arch.pmc[4]=mfspr(SPRN_PMC5);-vcpu->arch.pmc[5]=mfspr(SPRN_PMC6);-vcpu->arch.mmcr[1]=mfspr(SPRN_MMCR1);-vcpu->arch.mmcr[2]=mfspr(SPRN_MMCR2);-vcpu->arch.sdar=mfspr(SPRN_SDAR);-vcpu->arch.siar=mfspr(SPRN_SIAR);-vcpu->arch.sier[0]=mfspr(SPRN_SIER);--if(cpu_has_feature(CPU_FTR_ARCH_31)){-vcpu->arch.mmcr[3]=mfspr(SPRN_MMCR3);-vcpu->arch.sier[1]=mfspr(SPRN_SIER2);-vcpu->arch.sier[2]=mfspr(SPRN_SIER3);-}--}elseif(vcpu->arch.hfscr&HFSCR_PM){-/*-*TheguestaccessedPMCSPRswithoutspecifyingtheyshould-*bepreserved.Stopthemfromcountingiftheguesthad-*startedanything.-*/-freeze_pmu(mfspr(SPRN_MMCR0),mfspr(SPRN_MMCRA));--/*-*Demand-faultPMUregisteraccessintheguest.-*-*Thisisusedtograbtheguest'sVPApmcregs_in_usevalue-*andreflectitintothehost'sVPAinthecaseofanested-*hypervisor.-*-*Italsoavoidshavingtozero-outSPRsaftereachguest-*exittoavoidside-channelswhen.-*-*Thisisclearedherewhenweexittheguest,solaterHFSCR-*interrupthandlingcanadditbacktoruntheguestwith-*PMenablednexttime.-*/-vcpu->arch.hfscr&=~HFSCR_PM;-}/* otherwise the PMU should still be frozen from guest entry */--#ifdef CONFIG_PPC_PSERIES-if(kvmhv_on_pseries())-get_lppaca()->pmcregs_in_use=ppc_get_pmu_inuse();-#endif--if(ppc_get_pmu_inuse()){-mtspr(SPRN_PMC1,host_os_sprs->pmc1);-mtspr(SPRN_PMC2,host_os_sprs->pmc2);-mtspr(SPRN_PMC3,host_os_sprs->pmc3);-mtspr(SPRN_PMC4,host_os_sprs->pmc4);-mtspr(SPRN_PMC5,host_os_sprs->pmc5);-mtspr(SPRN_PMC6,host_os_sprs->pmc6);-mtspr(SPRN_MMCR1,host_os_sprs->mmcr1);-mtspr(SPRN_MMCR2,host_os_sprs->mmcr2);-mtspr(SPRN_SDAR,host_os_sprs->sdar);-mtspr(SPRN_SIAR,host_os_sprs->siar);-mtspr(SPRN_SIER,host_os_sprs->sier1);--if(cpu_has_feature(CPU_FTR_ARCH_31)){-mtspr(SPRN_MMCR3,host_os_sprs->mmcr3);-mtspr(SPRN_SIER2,host_os_sprs->sier2);-mtspr(SPRN_SIER3,host_os_sprs->sier3);-}--/* Set MMCRA then MMCR0 last */-mtspr(SPRN_MMCRA,host_os_sprs->mmcra);-mtspr(SPRN_MMCR0,host_os_sprs->mmcr0);-isync();-}-}--staticvoidload_spr_state(structkvm_vcpu*vcpu,-structp9_host_os_sprs*host_os_sprs)-{-mtspr(SPRN_TAR,vcpu->arch.tar);-mtspr(SPRN_EBBHR,vcpu->arch.ebbhr);-mtspr(SPRN_EBBRR,vcpu->arch.ebbrr);-mtspr(SPRN_BESCR,vcpu->arch.bescr);--if(!cpu_has_feature(CPU_FTR_ARCH_31))-mtspr(SPRN_TIDR,vcpu->arch.tid);-if(host_os_sprs->iamr!=vcpu->arch.iamr)-mtspr(SPRN_IAMR,vcpu->arch.iamr);-if(host_os_sprs->amr!=vcpu->arch.amr)-mtspr(SPRN_AMR,vcpu->arch.amr);-if(vcpu->arch.uamor!=0)-mtspr(SPRN_UAMOR,vcpu->arch.uamor);-if(host_os_sprs->fscr!=vcpu->arch.fscr)-mtspr(SPRN_FSCR,vcpu->arch.fscr);-if(host_os_sprs->dscr!=vcpu->arch.dscr)-mtspr(SPRN_DSCR,vcpu->arch.dscr);-if(vcpu->arch.pspb!=0)-mtspr(SPRN_PSPB,vcpu->arch.pspb);--/*-*DAR,DSISR,andfornestedHV,SPRGsmustbesetwithMSR[RI]-*clear(orhstatesetappropriatelytocatchthoseregisters-*beingclobberedifwetakeaMCEorSRESET),sothosearedone-*later.-*/--if(!(vcpu->arch.ctrl&1))-mtspr(SPRN_CTRLT,0);-}--staticvoidstore_spr_state(structkvm_vcpu*vcpu)-{-vcpu->arch.tar=mfspr(SPRN_TAR);-vcpu->arch.ebbhr=mfspr(SPRN_EBBHR);-vcpu->arch.ebbrr=mfspr(SPRN_EBBRR);-vcpu->arch.bescr=mfspr(SPRN_BESCR);--if(!cpu_has_feature(CPU_FTR_ARCH_31))-vcpu->arch.tid=mfspr(SPRN_TIDR);-vcpu->arch.iamr=mfspr(SPRN_IAMR);-vcpu->arch.amr=mfspr(SPRN_AMR);-vcpu->arch.uamor=mfspr(SPRN_UAMOR);-vcpu->arch.fscr=mfspr(SPRN_FSCR);-vcpu->arch.dscr=mfspr(SPRN_DSCR);-vcpu->arch.pspb=mfspr(SPRN_PSPB);--vcpu->arch.ctrl=mfspr(SPRN_CTRLF);-}--staticvoidload_vcpu_state(structkvm_vcpu*vcpu,-structp9_host_os_sprs*host_os_sprs)-{-if(cpu_has_feature(CPU_FTR_TM)||-cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))-kvmppc_restore_tm_hv(vcpu,vcpu->arch.shregs.msr,true);--load_spr_state(vcpu,host_os_sprs);--load_fp_state(&vcpu->arch.fp);-#ifdef CONFIG_ALTIVEC-load_vr_state(&vcpu->arch.vr);-#endif-mtspr(SPRN_VRSAVE,vcpu->arch.vrsave);-}--staticvoidstore_vcpu_state(structkvm_vcpu*vcpu)-{-store_spr_state(vcpu);--store_fp_state(&vcpu->arch.fp);-#ifdef CONFIG_ALTIVEC-store_vr_state(&vcpu->arch.vr);-#endif-vcpu->arch.vrsave=mfspr(SPRN_VRSAVE);--if(cpu_has_feature(CPU_FTR_TM)||-cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))-kvmppc_save_tm_hv(vcpu,vcpu->arch.shregs.msr,true);-}--staticvoidsave_p9_host_os_sprs(structp9_host_os_sprs*host_os_sprs)-{-if(!cpu_has_feature(CPU_FTR_ARCH_31))-host_os_sprs->tidr=mfspr(SPRN_TIDR);-host_os_sprs->iamr=mfspr(SPRN_IAMR);-host_os_sprs->amr=mfspr(SPRN_AMR);-host_os_sprs->fscr=mfspr(SPRN_FSCR);-host_os_sprs->dscr=mfspr(SPRN_DSCR);-}--/* vcpu guest regs must already be saved */-staticvoidrestore_p9_host_os_sprs(structkvm_vcpu*vcpu,-structp9_host_os_sprs*host_os_sprs)-{-mtspr(SPRN_SPRG_VDSO_WRITE,local_paca->sprg_vdso);--if(!cpu_has_feature(CPU_FTR_ARCH_31))-mtspr(SPRN_TIDR,host_os_sprs->tidr);-if(host_os_sprs->iamr!=vcpu->arch.iamr)-mtspr(SPRN_IAMR,host_os_sprs->iamr);-if(vcpu->arch.uamor!=0)-mtspr(SPRN_UAMOR,0);-if(host_os_sprs->amr!=vcpu->arch.amr)-mtspr(SPRN_AMR,host_os_sprs->amr);-if(host_os_sprs->fscr!=vcpu->arch.fscr)-mtspr(SPRN_FSCR,host_os_sprs->fscr);-if(host_os_sprs->dscr!=vcpu->arch.dscr)-mtspr(SPRN_DSCR,host_os_sprs->dscr);-if(vcpu->arch.pspb!=0)-mtspr(SPRN_PSPB,0);--/* Save guest CTRL register, set runlatch to 1 */-if(!(vcpu->arch.ctrl&1))-mtspr(SPRN_CTRLT,1);-}-staticinlineboolhcall_is_xics(unsignedlongreq){returnreq==H_EOI||req==H_CPPR||req==H_IPI||
@@ -4,8 +4,340 @@#include<asm/asm-prototypes.h>#include<asm/dbell.h>#include<asm/kvm_ppc.h>+#include<asm/pmc.h>#include<asm/ppc-opcode.h>+#include"book3s_hv.h"++staticvoidfreeze_pmu(unsignedlongmmcr0,unsignedlongmmcra)+{+if(!(mmcr0&MMCR0_FC))+gotodo_freeze;+if(mmcra&MMCRA_SAMPLE_ENABLE)+gotodo_freeze;+if(cpu_has_feature(CPU_FTR_ARCH_31)){+if(!(mmcr0&MMCR0_PMCCEXT))+gotodo_freeze;+if(!(mmcra&MMCRA_BHRB_DISABLE))+gotodo_freeze;+}+return;++do_freeze:+mmcr0=MMCR0_FC;+mmcra=0;+if(cpu_has_feature(CPU_FTR_ARCH_31)){+mmcr0|=MMCR0_PMCCEXT;+mmcra=MMCRA_BHRB_DISABLE;+}++mtspr(SPRN_MMCR0,mmcr0);+mtspr(SPRN_MMCRA,mmcra);+isync();+}++voidswitch_pmu_to_guest(structkvm_vcpu*vcpu,+structp9_host_os_sprs*host_os_sprs)+{+structlppaca*lp;+intload_pmu=1;++lp=vcpu->arch.vpa.pinned_addr;+if(lp)+load_pmu=lp->pmcregs_in_use;++if(load_pmu)+vcpu->arch.hfscr|=HFSCR_PM;++/* Save host */+if(ppc_get_pmu_inuse()){+/*+*ItmightbebettertoputPMUhandling(atleastforthe+*host)intheperfsubsystembecauseitknowsmoreaboutwhat+*isbeingused.+*/++/* POWER9, POWER10 do not implement HPMC or SPMC */++host_os_sprs->mmcr0=mfspr(SPRN_MMCR0);+host_os_sprs->mmcra=mfspr(SPRN_MMCRA);++freeze_pmu(host_os_sprs->mmcr0,host_os_sprs->mmcra);++host_os_sprs->pmc1=mfspr(SPRN_PMC1);+host_os_sprs->pmc2=mfspr(SPRN_PMC2);+host_os_sprs->pmc3=mfspr(SPRN_PMC3);+host_os_sprs->pmc4=mfspr(SPRN_PMC4);+host_os_sprs->pmc5=mfspr(SPRN_PMC5);+host_os_sprs->pmc6=mfspr(SPRN_PMC6);+host_os_sprs->mmcr1=mfspr(SPRN_MMCR1);+host_os_sprs->mmcr2=mfspr(SPRN_MMCR2);+host_os_sprs->sdar=mfspr(SPRN_SDAR);+host_os_sprs->siar=mfspr(SPRN_SIAR);+host_os_sprs->sier1=mfspr(SPRN_SIER);++if(cpu_has_feature(CPU_FTR_ARCH_31)){+host_os_sprs->mmcr3=mfspr(SPRN_MMCR3);+host_os_sprs->sier2=mfspr(SPRN_SIER2);+host_os_sprs->sier3=mfspr(SPRN_SIER3);+}+}++#ifdef CONFIG_PPC_PSERIES+if(kvmhv_on_pseries()){+if(vcpu->arch.vpa.pinned_addr){+structlppaca*lp=vcpu->arch.vpa.pinned_addr;+get_lppaca()->pmcregs_in_use=lp->pmcregs_in_use;+}else{+get_lppaca()->pmcregs_in_use=1;+}+}+#endif++/* Load guest */+if(vcpu->arch.hfscr&HFSCR_PM){+mtspr(SPRN_PMC1,vcpu->arch.pmc[0]);+mtspr(SPRN_PMC2,vcpu->arch.pmc[1]);+mtspr(SPRN_PMC3,vcpu->arch.pmc[2]);+mtspr(SPRN_PMC4,vcpu->arch.pmc[3]);+mtspr(SPRN_PMC5,vcpu->arch.pmc[4]);+mtspr(SPRN_PMC6,vcpu->arch.pmc[5]);+mtspr(SPRN_MMCR1,vcpu->arch.mmcr[1]);+mtspr(SPRN_MMCR2,vcpu->arch.mmcr[2]);+mtspr(SPRN_SDAR,vcpu->arch.sdar);+mtspr(SPRN_SIAR,vcpu->arch.siar);+mtspr(SPRN_SIER,vcpu->arch.sier[0]);++if(cpu_has_feature(CPU_FTR_ARCH_31)){+mtspr(SPRN_MMCR3,vcpu->arch.mmcr[4]);+mtspr(SPRN_SIER2,vcpu->arch.sier[1]);+mtspr(SPRN_SIER3,vcpu->arch.sier[2]);+}++/* Set MMCRA then MMCR0 last */+mtspr(SPRN_MMCRA,vcpu->arch.mmcra);+mtspr(SPRN_MMCR0,vcpu->arch.mmcr[0]);+/* No isync necessary because we're starting counters */+}+}+EXPORT_SYMBOL_GPL(switch_pmu_to_guest);++voidswitch_pmu_to_host(structkvm_vcpu*vcpu,+structp9_host_os_sprs*host_os_sprs)+{+structlppaca*lp;+intsave_pmu=1;++lp=vcpu->arch.vpa.pinned_addr;+if(lp)+save_pmu=lp->pmcregs_in_use;++if(save_pmu){+vcpu->arch.mmcr[0]=mfspr(SPRN_MMCR0);+vcpu->arch.mmcra=mfspr(SPRN_MMCRA);++freeze_pmu(vcpu->arch.mmcr[0],vcpu->arch.mmcra);++vcpu->arch.pmc[0]=mfspr(SPRN_PMC1);+vcpu->arch.pmc[1]=mfspr(SPRN_PMC2);+vcpu->arch.pmc[2]=mfspr(SPRN_PMC3);+vcpu->arch.pmc[3]=mfspr(SPRN_PMC4);+vcpu->arch.pmc[4]=mfspr(SPRN_PMC5);+vcpu->arch.pmc[5]=mfspr(SPRN_PMC6);+vcpu->arch.mmcr[1]=mfspr(SPRN_MMCR1);+vcpu->arch.mmcr[2]=mfspr(SPRN_MMCR2);+vcpu->arch.sdar=mfspr(SPRN_SDAR);+vcpu->arch.siar=mfspr(SPRN_SIAR);+vcpu->arch.sier[0]=mfspr(SPRN_SIER);++if(cpu_has_feature(CPU_FTR_ARCH_31)){+vcpu->arch.mmcr[3]=mfspr(SPRN_MMCR3);+vcpu->arch.sier[1]=mfspr(SPRN_SIER2);+vcpu->arch.sier[2]=mfspr(SPRN_SIER3);+}++}elseif(vcpu->arch.hfscr&HFSCR_PM){+/*+*TheguestaccessedPMCSPRswithoutspecifyingtheyshould+*bepreserved.Stopthemfromcountingiftheguesthad+*startedanything.+*/+freeze_pmu(mfspr(SPRN_MMCR0),mfspr(SPRN_MMCRA));++/*+*Demand-faultPMUregisteraccessintheguest.+*+*Thisisusedtograbtheguest'sVPApmcregs_in_usevalue+*andreflectitintothehost'sVPAinthecaseofanested+*hypervisor.+*+*Italsoavoidshavingtozero-outSPRsaftereachguest+*exittoavoidside-channelswhen.+*+*Thisisclearedherewhenweexittheguest,solaterHFSCR+*interrupthandlingcanadditbacktoruntheguestwith+*PMenablednexttime.+*/+vcpu->arch.hfscr&=~HFSCR_PM;+}/* otherwise the PMU should still be frozen from guest entry */+++#ifdef CONFIG_PPC_PSERIES+if(kvmhv_on_pseries())+get_lppaca()->pmcregs_in_use=ppc_get_pmu_inuse();+#endif++if(ppc_get_pmu_inuse()){+mtspr(SPRN_PMC1,host_os_sprs->pmc1);+mtspr(SPRN_PMC2,host_os_sprs->pmc2);+mtspr(SPRN_PMC3,host_os_sprs->pmc3);+mtspr(SPRN_PMC4,host_os_sprs->pmc4);+mtspr(SPRN_PMC5,host_os_sprs->pmc5);+mtspr(SPRN_PMC6,host_os_sprs->pmc6);+mtspr(SPRN_MMCR1,host_os_sprs->mmcr1);+mtspr(SPRN_MMCR2,host_os_sprs->mmcr2);+mtspr(SPRN_SDAR,host_os_sprs->sdar);+mtspr(SPRN_SIAR,host_os_sprs->siar);+mtspr(SPRN_SIER,host_os_sprs->sier1);++if(cpu_has_feature(CPU_FTR_ARCH_31)){+mtspr(SPRN_MMCR3,host_os_sprs->mmcr3);+mtspr(SPRN_SIER2,host_os_sprs->sier2);+mtspr(SPRN_SIER3,host_os_sprs->sier3);+}++/* Set MMCRA then MMCR0 last */+mtspr(SPRN_MMCRA,host_os_sprs->mmcra);+mtspr(SPRN_MMCR0,host_os_sprs->mmcr0);+isync();+}+}+EXPORT_SYMBOL_GPL(switch_pmu_to_host);++staticvoidload_spr_state(structkvm_vcpu*vcpu,+structp9_host_os_sprs*host_os_sprs)+{+mtspr(SPRN_TAR,vcpu->arch.tar);+mtspr(SPRN_EBBHR,vcpu->arch.ebbhr);+mtspr(SPRN_EBBRR,vcpu->arch.ebbrr);+mtspr(SPRN_BESCR,vcpu->arch.bescr);++if(!cpu_has_feature(CPU_FTR_ARCH_31))+mtspr(SPRN_TIDR,vcpu->arch.tid);+if(host_os_sprs->iamr!=vcpu->arch.iamr)+mtspr(SPRN_IAMR,vcpu->arch.iamr);+if(host_os_sprs->amr!=vcpu->arch.amr)+mtspr(SPRN_AMR,vcpu->arch.amr);+if(vcpu->arch.uamor!=0)+mtspr(SPRN_UAMOR,vcpu->arch.uamor);+if(host_os_sprs->fscr!=vcpu->arch.fscr)+mtspr(SPRN_FSCR,vcpu->arch.fscr);+if(host_os_sprs->dscr!=vcpu->arch.dscr)+mtspr(SPRN_DSCR,vcpu->arch.dscr);+if(vcpu->arch.pspb!=0)+mtspr(SPRN_PSPB,vcpu->arch.pspb);++/*+*DAR,DSISR,andfornestedHV,SPRGsmustbesetwithMSR[RI]+*clear(orhstatesetappropriatelytocatchthoseregisters+*beingclobberedifwetakeaMCEorSRESET),sothosearedone+*later.+*/++if(!(vcpu->arch.ctrl&1))+mtspr(SPRN_CTRLT,0);+}++staticvoidstore_spr_state(structkvm_vcpu*vcpu)+{+vcpu->arch.tar=mfspr(SPRN_TAR);+vcpu->arch.ebbhr=mfspr(SPRN_EBBHR);+vcpu->arch.ebbrr=mfspr(SPRN_EBBRR);+vcpu->arch.bescr=mfspr(SPRN_BESCR);++if(!cpu_has_feature(CPU_FTR_ARCH_31))+vcpu->arch.tid=mfspr(SPRN_TIDR);+vcpu->arch.iamr=mfspr(SPRN_IAMR);+vcpu->arch.amr=mfspr(SPRN_AMR);+vcpu->arch.uamor=mfspr(SPRN_UAMOR);+vcpu->arch.fscr=mfspr(SPRN_FSCR);+vcpu->arch.dscr=mfspr(SPRN_DSCR);+vcpu->arch.pspb=mfspr(SPRN_PSPB);++vcpu->arch.ctrl=mfspr(SPRN_CTRLF);+}++voidload_vcpu_state(structkvm_vcpu*vcpu,+structp9_host_os_sprs*host_os_sprs)+{+if(cpu_has_feature(CPU_FTR_TM)||+cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))+kvmppc_restore_tm_hv(vcpu,vcpu->arch.shregs.msr,true);++load_spr_state(vcpu,host_os_sprs);++load_fp_state(&vcpu->arch.fp);+#ifdef CONFIG_ALTIVEC+load_vr_state(&vcpu->arch.vr);+#endif+mtspr(SPRN_VRSAVE,vcpu->arch.vrsave);+}+EXPORT_SYMBOL_GPL(load_vcpu_state);++voidstore_vcpu_state(structkvm_vcpu*vcpu)+{+store_spr_state(vcpu);++store_fp_state(&vcpu->arch.fp);+#ifdef CONFIG_ALTIVEC+store_vr_state(&vcpu->arch.vr);+#endif+vcpu->arch.vrsave=mfspr(SPRN_VRSAVE);++if(cpu_has_feature(CPU_FTR_TM)||+cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))+kvmppc_save_tm_hv(vcpu,vcpu->arch.shregs.msr,true);+}+EXPORT_SYMBOL_GPL(store_vcpu_state);++voidsave_p9_host_os_sprs(structp9_host_os_sprs*host_os_sprs)+{+if(!cpu_has_feature(CPU_FTR_ARCH_31))+host_os_sprs->tidr=mfspr(SPRN_TIDR);+host_os_sprs->iamr=mfspr(SPRN_IAMR);+host_os_sprs->amr=mfspr(SPRN_AMR);+host_os_sprs->fscr=mfspr(SPRN_FSCR);+host_os_sprs->dscr=mfspr(SPRN_DSCR);+}+EXPORT_SYMBOL_GPL(save_p9_host_os_sprs);++/* vcpu guest regs must already be saved */+voidrestore_p9_host_os_sprs(structkvm_vcpu*vcpu,+structp9_host_os_sprs*host_os_sprs)+{+mtspr(SPRN_SPRG_VDSO_WRITE,local_paca->sprg_vdso);++if(!cpu_has_feature(CPU_FTR_ARCH_31))+mtspr(SPRN_TIDR,host_os_sprs->tidr);+if(host_os_sprs->iamr!=vcpu->arch.iamr)+mtspr(SPRN_IAMR,host_os_sprs->iamr);+if(vcpu->arch.uamor!=0)+mtspr(SPRN_UAMOR,0);+if(host_os_sprs->amr!=vcpu->arch.amr)+mtspr(SPRN_AMR,host_os_sprs->amr);+if(host_os_sprs->fscr!=vcpu->arch.fscr)+mtspr(SPRN_FSCR,host_os_sprs->fscr);+if(host_os_sprs->dscr!=vcpu->arch.dscr)+mtspr(SPRN_DSCR,host_os_sprs->dscr);+if(vcpu->arch.pspb!=0)+mtspr(SPRN_PSPB,0);++/* Save guest CTRL register, set runlatch to 1 */+if(!(vcpu->arch.ctrl&1))+mtspr(SPRN_CTRLT,1);+}+EXPORT_SYMBOL_GPL(restore_p9_host_os_sprs);+#ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMINGstaticvoid__start_timing(structkvm_vcpu*vcpu,structkvmhv_tb_accumulator*next){
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:10:39
This is just refactoring.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 125 +++++++++++++++++++----------------
1 file changed, 67 insertions(+), 58 deletions(-)
@@ -3692,6 +3692,72 @@ static void vcpu_vpa_increment_dispatch(struct kvm_vcpu *vcpu)}}+/* call our hypervisor to load up HV regs and go */+staticintkvmhv_vcpu_entry_p9_nested(structkvm_vcpu*vcpu,u64time_limit,unsignedlonglpcr,u64*tb)+{+structkvmppc_vcore*vc=vcpu->arch.vcore;+unsignedlonghost_psscr;+structhv_guest_statehvregs;+inttrap;+s64dec;++/*+*Weneedtosaveandrestoretheguestvisiblepartofthe+*psscr(i.e.usingSPRN_PSSCR_PR)sincethehypervisor+*doesn'tdothisforus.Noteonlyrequiredifpseriessince+*thisisdoneinkvmhv_vcpu_entry_p9()belowotherwise.+*/+host_psscr=mfspr(SPRN_PSSCR_PR);+mtspr(SPRN_PSSCR_PR,vcpu->arch.psscr);+kvmhv_save_hv_regs(vcpu,&hvregs);+hvregs.lpcr=lpcr;+vcpu->arch.regs.msr=vcpu->arch.shregs.msr;+hvregs.version=HV_GUEST_STATE_VERSION;+if(vcpu->arch.nested){+hvregs.lpid=vcpu->arch.nested->shadow_lpid;+hvregs.vcpu_token=vcpu->arch.nested_vcpu_id;+}else{+hvregs.lpid=vcpu->kvm->arch.lpid;+hvregs.vcpu_token=vcpu->vcpu_id;+}+hvregs.hdec_expiry=time_limit;++/*+*WhensettingDEC,wemustalwaysdealwithirq_work_raise+*viaNMIvssettingDEC.Theproblemoccursrightaswe+*switchintoguestmodeifaNMIhitsandsetspendingwork+*andsetsDEC,thenthatwillapplytotheguestandnot+*bringusbacktothehost.+*+*irq_work_raisecouldcheckaflag(orpossiblyLPCR[HDICE]+*forexample)andsetHDECto1?Thatwouldn'tsolvethe+*nestedhvcasewhichneedstoabortthehcallorzerothe+*timelimit.+*+*XXX:Anotherday'sproblem.+*/+mtspr(SPRN_DEC,kvmppc_dec_expires_host_tb(vcpu)-*tb);++mtspr(SPRN_DAR,vcpu->arch.shregs.dar);+mtspr(SPRN_DSISR,vcpu->arch.shregs.dsisr);+trap=plpar_hcall_norets(H_ENTER_NESTED,__pa(&hvregs),+__pa(&vcpu->arch.regs));+kvmhv_restore_hv_return_state(vcpu,&hvregs);+vcpu->arch.shregs.msr=vcpu->arch.regs.msr;+vcpu->arch.shregs.dar=mfspr(SPRN_DAR);+vcpu->arch.shregs.dsisr=mfspr(SPRN_DSISR);+vcpu->arch.psscr=mfspr(SPRN_PSSCR_PR);+mtspr(SPRN_PSSCR_PR,host_psscr);++dec=mfspr(SPRN_DEC);+if(!(lpcr&LPCR_LD))/* Sign extend if not using large decrementer */+dec=(s32)dec;+*tb=mftb();+vcpu->arch.dec_expires=dec+(*tb+vc->tb_offset);++returntrap;+}+/**GuestentryforPOWER9andlaterCPUs.*/
@@ -3752,63 +3817,7 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,switch_pmu_to_guest(vcpu,&host_os_sprs);if(kvmhv_on_pseries()){-/*-*Weneedtosaveandrestoretheguestvisiblepartofthe-*psscr(i.e.usingSPRN_PSSCR_PR)sincethehypervisor-*doesn'tdothisforus.Noteonlyrequiredifpseriessince-*thisisdoneinkvmhv_vcpu_entry_p9()belowotherwise.-*/-unsignedlonghost_psscr;-/* call our hypervisor to load up HV regs and go */-structhv_guest_statehvregs;--host_psscr=mfspr(SPRN_PSSCR_PR);-mtspr(SPRN_PSSCR_PR,vcpu->arch.psscr);-kvmhv_save_hv_regs(vcpu,&hvregs);-hvregs.lpcr=lpcr;-vcpu->arch.regs.msr=vcpu->arch.shregs.msr;-hvregs.version=HV_GUEST_STATE_VERSION;-if(vcpu->arch.nested){-hvregs.lpid=vcpu->arch.nested->shadow_lpid;-hvregs.vcpu_token=vcpu->arch.nested_vcpu_id;-}else{-hvregs.lpid=vcpu->kvm->arch.lpid;-hvregs.vcpu_token=vcpu->vcpu_id;-}-hvregs.hdec_expiry=time_limit;--/*-*WhensettingDEC,wemustalwaysdealwithirq_work_raise-*viaNMIvssettingDEC.Theproblemoccursrightaswe-*switchintoguestmodeifaNMIhitsandsetspendingwork-*andsetsDEC,thenthatwillapplytotheguestandnot-*bringusbacktothehost.-*-*irq_work_raisecouldcheckaflag(orpossiblyLPCR[HDICE]-*forexample)andsetHDECto1?Thatwouldn'tsolvethe-*nestedhvcasewhichneedstoabortthehcallorzerothe-*timelimit.-*-*XXX:Anotherday'sproblem.-*/-mtspr(SPRN_DEC,kvmppc_dec_expires_host_tb(vcpu)-*tb);--mtspr(SPRN_DAR,vcpu->arch.shregs.dar);-mtspr(SPRN_DSISR,vcpu->arch.shregs.dsisr);-trap=plpar_hcall_norets(H_ENTER_NESTED,__pa(&hvregs),-__pa(&vcpu->arch.regs));-kvmhv_restore_hv_return_state(vcpu,&hvregs);-vcpu->arch.shregs.msr=vcpu->arch.regs.msr;-vcpu->arch.shregs.dar=mfspr(SPRN_DAR);-vcpu->arch.shregs.dsisr=mfspr(SPRN_DSISR);-vcpu->arch.psscr=mfspr(SPRN_PSSCR_PR);-mtspr(SPRN_PSSCR_PR,host_psscr);--dec=mfspr(SPRN_DEC);-if(!(lpcr&LPCR_LD))/* Sign extend if not using large decrementer */-dec=(s32)dec;-*tb=mftb();-vcpu->arch.dec_expires=dec+(*tb+vc->tb_offset);+trap=kvmhv_vcpu_entry_p9_nested(vcpu,time_limit,lpcr,tb);/* H_CEDE has to be handled now, not later */if(trap==BOOK3S_INTERRUPT_SYSCALL&&!vcpu->arch.nested&&
@@ -3708,6 +3714,26 @@ static int kvmhv_vcpu_entry_p9_nested(struct kvm_vcpu *vcpu, u64 time_limit, uns*thisisdoneinkvmhv_vcpu_entry_p9()belowotherwise.*/host_psscr=mfspr(SPRN_PSSCR_PR);++hard_irq_disable();+if(lazy_irq_pending())+return0;++/* MSR bits may have been cleared by context switch */+msr=0;+if(IS_ENABLED(CONFIG_PPC_FPU))+msr|=MSR_FP;+if(cpu_has_feature(CPU_FTR_ALTIVEC))+msr|=MSR_VEC;+if(cpu_has_feature(CPU_FTR_VSX))+msr|=MSR_VSX;+if(cpu_has_feature(CPU_FTR_TM)||+cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))+msr|=MSR_TM;+msr=msr_check_and_set(msr);++load_vcpu_state(vcpu,&host_os_sprs);+mtspr(SPRN_PSSCR_PR,vcpu->arch.psscr);kvmhv_save_hv_regs(vcpu,&hvregs);hvregs.lpcr=lpcr;
@@ -3749,12 +3775,20 @@ static int kvmhv_vcpu_entry_p9_nested(struct kvm_vcpu *vcpu, u64 time_limit, unsvcpu->arch.psscr=mfspr(SPRN_PSSCR_PR);mtspr(SPRN_PSSCR_PR,host_psscr);+store_vcpu_state(vcpu);+dec=mfspr(SPRN_DEC);if(!(lpcr&LPCR_LD))/* Sign extend if not using large decrementer */dec=(s32)dec;*tb=mftb();vcpu->arch.dec_expires=dec+(*tb+vc->tb_offset);+timer_rearm_host_dec(*tb);++restore_p9_host_os_sprs(vcpu,&host_os_sprs);++switch_pmu_to_host(vcpu,&host_os_sprs);+returntrap;}
@@ -3778,33 +3810,6 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,vcpu->arch.ceded=0;-save_p9_host_os_sprs(&host_os_sprs);--/*-*ThiscouldbecombinedwithMSR[RI]clearing,butthatexpands-*theunrecoverablewindow.Itwouldbebettertocoverunrecoverable-*withKVMbadinterrupthandlingratherthanuseMSR[RI]atall.-*-*MuchmoredifficultandlessworthwhiletocombinewithIR/DR-*disable.-*/-hard_irq_disable();-if(lazy_irq_pending())-return0;--/* MSR bits may have been cleared by context switch */-msr=0;-if(IS_ENABLED(CONFIG_PPC_FPU))-msr|=MSR_FP;-if(cpu_has_feature(CPU_FTR_ALTIVEC))-msr|=MSR_VEC;-if(cpu_has_feature(CPU_FTR_VSX))-msr|=MSR_VSX;-if(cpu_has_feature(CPU_FTR_TM)||-cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))-msr|=MSR_TM;-msr=msr_check_and_set(msr);-kvmppc_subcore_enter_guest();vc->entry_exit_map=1;
@@ -546,9 +547,6 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcvcpu->arch.ceded=0;-/* Could avoid mfmsr by passing around, but probably no big deal */-msr=mfmsr();-host_hfscr=mfspr(SPRN_HFSCR);host_ciabr=mfspr(SPRN_CIABR);host_dawr0=mfspr(SPRN_DAWR0);
@@ -563,6 +561,38 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpclocal_paca->kvm_hstate.host_purr=mfspr(SPRN_PURR);local_paca->kvm_hstate.host_spurr=mfspr(SPRN_SPURR);+switch_pmu_to_guest(vcpu,&host_os_sprs);++save_p9_host_os_sprs(&host_os_sprs);++/*+*ThiscouldbecombinedwithMSR[RI]clearing,butthatexpands+*theunrecoverablewindow.Itwouldbebettertocoverunrecoverable+*withKVMbadinterrupthandlingratherthanuseMSR[RI]atall.+*+*MuchmoredifficultandlessworthwhiletocombinewithIR/DR+*disable.+*/+hard_irq_disable();+if(lazy_irq_pending()){+trap=0;+gotoout;+}++/* MSR bits may have been cleared by context switch */+msr=0;+if(IS_ENABLED(CONFIG_PPC_FPU))+msr|=MSR_FP;+if(cpu_has_feature(CPU_FTR_ALTIVEC))+msr|=MSR_VEC;+if(cpu_has_feature(CPU_FTR_VSX))+msr|=MSR_VSX;+if(cpu_has_feature(CPU_FTR_TM)||+cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))+msr|=MSR_TM;+msr=msr_check_and_set(msr);+/* Save MSR for restore. This is after hard disable, so EE is clear. */+if(vc->tb_offset){u64new_tb=*tb+vc->tb_offset;mtspr(SPRN_TBU40,new_tb);
@@ -623,6 +653,8 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpclocal_paca->kvm_hstate.in_guest=KVM_GUEST_MODE_HV_P9;+load_vcpu_state(vcpu,&host_os_sprs);+/**Hashhost,hashguest,orradixguestwithprefetchbug,allhave*todisabletheMMUbeforeswitchingtoguestMMUstate.
@@ -783,6 +815,17 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcvc->dpdes=mfspr(SPRN_DPDES);vc->vtb=mfspr(SPRN_VTB);+save_clear_guest_mmu(kvm,vcpu);+switch_mmu_to_host(kvm,host_pidr);++/*+*Ifweareinrealmode,onlyswitchMMUonaftertheMMUis+*switchedtohost,toavoidtheP9_RADIX_PREFETCH_BUG.+*/+__mtmsrd(msr,0);++store_vcpu_state(vcpu);+dec=mfspr(SPRN_DEC);if(!(lpcr&LPCR_LD))/* Sign extend if not using large decrementer */dec=(s32)dec;
@@ -815,6 +858,19 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcmtspr(SPRN_DAWRX1,host_dawrx1);}+mtspr(SPRN_DPDES,0);+if(vc->pcr)+mtspr(SPRN_PCR,PCR_MASK);++/* HDEC must be at least as large as DEC, so decrementer_max fits */+mtspr(SPRN_HDEC,decrementer_max);++timer_rearm_host_dec(*tb);++restore_p9_host_os_sprs(vcpu,&host_os_sprs);++local_paca->kvm_hstate.in_guest=KVM_GUEST_MODE_NONE;+if(kvm_is_radix(kvm)){/**Sincethisisradix,doaeieio;tlbsync;ptesyncsequence
@@ -831,22 +887,8 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcif(cpu_has_feature(CPU_FTR_ARCH_31))asmvolatile(PPC_CP_ABORT);-mtspr(SPRN_DPDES,0);-if(vc->pcr)-mtspr(SPRN_PCR,PCR_MASK);--/* HDEC must be at least as large as DEC, so decrementer_max fits */-mtspr(SPRN_HDEC,decrementer_max);--save_clear_guest_mmu(kvm,vcpu);-switch_mmu_to_host(kvm,host_pidr);-local_paca->kvm_hstate.in_guest=KVM_GUEST_MODE_NONE;--/*-*Ifweareinrealmode,onlyswitchMMUonaftertheMMUis-*switchedtohost,toavoidtheP9_RADIX_PREFETCH_BUG.-*/-__mtmsrd(msr,0);+out:+switch_pmu_to_host(vcpu,&host_os_sprs);end_timing(vcpu);
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:11:35
If TM is not active, only TM register state needs to be saved.
-348 cycles (7218) POWER9 virt-mode NULL hcall
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv_p9_entry.c | 24 ++++++++++++++++++++----
1 file changed, 20 insertions(+), 4 deletions(-)
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:11:58
This moves PMU switch to guest as late as possible in entry, and switch
back to host as early as possible at exit. This helps the host get the
most perf coverage of KVM entry/exit code as possible.
This is slightly suboptimal for SPR scheduling point of view when the
PMU is enabled, but when perf is disabled there is no real difference.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 6 ++----
arch/powerpc/kvm/book3s_hv_p9_entry.c | 6 ++----
2 files changed, 4 insertions(+), 8 deletions(-)
@@ -1523,7 +1523,8 @@ XXX benchmark guest exitsunsignedlongvsid;longerr;-if(vcpu->arch.fault_dsisr==HDSISR_CANARY){+if(cpu_has_feature(CPU_FTR_P9_RADIX_PREFETCH_BUG)&&+unlikely(vcpu->arch.fault_dsisr==HDSISR_CANARY)){r=RESUME_GUEST;/* Just retry if it's the canary */break;}
@@ -618,24 +618,29 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcvc->tb_offset_applied=vc->tb_offset;}-if(vc->pcr)-mtspr(SPRN_PCR,vc->pcr|PCR_MASK);-mtspr(SPRN_DPDES,vc->dpdes);mtspr(SPRN_VTB,vc->vtb);-mtspr(SPRN_PURR,vcpu->arch.purr);mtspr(SPRN_SPURR,vcpu->arch.spurr);+if(vc->pcr)+mtspr(SPRN_PCR,vc->pcr|PCR_MASK);+if(vc->dpdes)+mtspr(SPRN_DPDES,vc->dpdes);+if(dawr_enabled()){-mtspr(SPRN_DAWR0,vcpu->arch.dawr0);-mtspr(SPRN_DAWRX0,vcpu->arch.dawrx0);+if(vcpu->arch.dawr0!=host_dawr0)+mtspr(SPRN_DAWR0,vcpu->arch.dawr0);+if(vcpu->arch.dawrx0!=host_dawrx0)+mtspr(SPRN_DAWRX0,vcpu->arch.dawrx0);if(cpu_has_feature(CPU_FTR_DAWR1)){-mtspr(SPRN_DAWR1,vcpu->arch.dawr1);-mtspr(SPRN_DAWRX1,vcpu->arch.dawrx1);+if(vcpu->arch.dawr1!=host_dawr1)+mtspr(SPRN_DAWR1,vcpu->arch.dawr1);+if(vcpu->arch.dawrx1!=host_dawrx1)+mtspr(SPRN_DAWRX1,vcpu->arch.dawrx1);}}-mtspr(SPRN_CIABR,vcpu->arch.ciabr);-mtspr(SPRN_IC,vcpu->arch.ic);+if(vcpu->arch.ciabr!=host_ciabr)+mtspr(SPRN_CIABR,vcpu->arch.ciabr);mtspr(SPRN_PSSCR,vcpu->arch.psscr|PSSCR_EC|(local_paca->kvm_hstate.fake_suspend<<PSSCR_FAKE_SUSPEND_LG));
@@ -833,17 +838,6 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcvc->dpdes=mfspr(SPRN_DPDES);vc->vtb=mfspr(SPRN_VTB);-save_clear_guest_mmu(kvm,vcpu);-switch_mmu_to_host(kvm,host_pidr);--/*-*Ifweareinrealmode,onlyswitchMMUonaftertheMMUis-*switchedtohost,toavoidtheP9_RADIX_PREFETCH_BUG.-*/-__mtmsrd(msr,0);--store_vcpu_state(vcpu);-dec=mfspr(SPRN_DEC);if(!(lpcr&LPCR_LD))/* Sign extend if not using large decrementer */dec=(s32)dec;
@@ -861,6 +855,19 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcvc->tb_offset_applied=0;}+save_clear_guest_mmu(kvm,vcpu);+switch_mmu_to_host(kvm,host_pidr);++/*+*EnableMSRhereinordertohavefacilitiesenabledtosave+*guestregisters.ThisenablesMMU(ifwewereinrealmode),so+*onlyswitchMMUonaftertheMMUisswitchedtohost,toavoid+*theP9_RADIX_PREFETCH_BUGorhashguestcontext.+*/+__mtmsrd(msr,0);++store_vcpu_state(vcpu);+mtspr(SPRN_PURR,local_paca->kvm_hstate.host_purr);mtspr(SPRN_SPURR,local_paca->kvm_hstate.host_spurr);
@@ -868,15 +875,21 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcmtspr(SPRN_PSSCR,host_psscr|(local_paca->kvm_hstate.fake_suspend<<PSSCR_FAKE_SUSPEND_LG));mtspr(SPRN_HFSCR,host_hfscr);-mtspr(SPRN_CIABR,host_ciabr);-mtspr(SPRN_DAWR0,host_dawr0);-mtspr(SPRN_DAWRX0,host_dawrx0);+if(vcpu->arch.ciabr!=host_ciabr)+mtspr(SPRN_CIABR,host_ciabr);+if(vcpu->arch.dawr0!=host_dawr0)+mtspr(SPRN_DAWR0,host_dawr0);+if(vcpu->arch.dawrx0!=host_dawrx0)+mtspr(SPRN_DAWRX0,host_dawrx0);if(cpu_has_feature(CPU_FTR_DAWR1)){-mtspr(SPRN_DAWR1,host_dawr1);-mtspr(SPRN_DAWRX1,host_dawrx1);+if(vcpu->arch.dawr1!=host_dawr1)+mtspr(SPRN_DAWR1,host_dawr1);+if(vcpu->arch.dawrx1!=host_dawrx1)+mtspr(SPRN_DAWRX1,host_dawrx1);}-mtspr(SPRN_DPDES,0);+if(vc->dpdes)+mtspr(SPRN_DPDES,0);if(vc->pcr)mtspr(SPRN_PCR,PCR_MASK);
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:13:16
Use HFSCR facility disabling to implement demand faulting for EBB, with
a hysteresis counter similar to the load_fp etc counters in context
switching that implement the equivalent demand faulting for userspace
facilities.
This speeds up guest entry/exit by avoiding the register save/restore
when a guest is not frequently using them. When a guest does use them
often, there will be some additional demand fault overhead, but these
are not commonly used facilities.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kvm/book3s_hv.c | 11 +++++++++++
arch/powerpc/kvm/book3s_hv_nested.c | 3 ++-
arch/powerpc/kvm/book3s_hv_p9_entry.c | 26 ++++++++++++++++++++------
4 files changed, 34 insertions(+), 7 deletions(-)
@@ -168,7 +168,8 @@ static void sanitise_hv_regs(struct kvm_vcpu *vcpu, struct hv_guest_state *hr)*butpreservetheinterruptcausefieldandfacilitiesthatmight*bedisabledfordemandfaultingintheL1.*/-hr->hfscr&=(HFSCR_INTR_CAUSE|HFSCR_PM|vcpu->arch.hfscr);+hr->hfscr&=(HFSCR_INTR_CAUSE|HFSCR_PM|HFSCR_EBB|+vcpu->arch.hfscr);/* Don't let data address watchpoint match in hypervisor state */hr->dawrx0&=~DAWRX_HYP;
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:13:40
Use HFSCR facility disabling to implement demand faulting for TM, with
a hysteresis counter similar to the load_fp etc counters in context
switching that implement the equivalent demand faulting for userspace
facilities.
This speeds up guest entry/exit by avoiding the register save/restore
when a guest is not frequently using them. When a guest does use them
often, there will be some additional demand fault overhead, but these
are not commonly used facilities.
-304 cycles (6681) POWER9 virt-mode NULL hcall with the previous patch
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/kvm/book3s_hv.c | 21 +++++++++++++++++----
arch/powerpc/kvm/book3s_hv_nested.c | 2 +-
arch/powerpc/kvm/book3s_hv_p9_entry.c | 18 ++++++++++++------
4 files changed, 31 insertions(+), 11 deletions(-)
@@ -168,7 +168,7 @@ static void sanitise_hv_regs(struct kvm_vcpu *vcpu, struct hv_guest_state *hr)*butpreservetheinterruptcausefieldandfacilitiesthatmight*bedisabledfordemandfaultingintheL1.*/-hr->hfscr&=(HFSCR_INTR_CAUSE|HFSCR_PM|HFSCR_EBB|+hr->hfscr&=(HFSCR_INTR_CAUSE|HFSCR_PM|HFSCR_TM|HFSCR_EBB|vcpu->arch.hfscr);/* Don't let data address watchpoint match in hypervisor state */
@@ -326,6 +328,9 @@ void store_vcpu_state(struct kvm_vcpu *vcpu)vcpu->arch.tfhar=mfspr(SPRN_TFHAR);vcpu->arch.tfiar=mfspr(SPRN_TFIAR);}+vcpu->arch.load_tm++;/* see load_ebb comment for details */+if(!vcpu->arch.load_tm)+vcpu->arch.hfscr&=~HFSCR_TM;}}EXPORT_SYMBOL_GPL(store_vcpu_state);
@@ -615,8 +620,9 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcmsr|=MSR_VEC;if(cpu_has_feature(CPU_FTR_VSX))msr|=MSR_VSX;-if(cpu_has_feature(CPU_FTR_TM)||-cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))+if((cpu_has_feature(CPU_FTR_TM)||+cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))&&+(vcpu->arch.hfscr&HFSCR_TM))msr|=MSR_TM;msr=msr_check_and_set(msr);/* Save MSR for restore. This is after hard disable, so EE is clear. */
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:14:13
Linux implements SPR save/restore including storage space for registers
in the task struct for process context switching. Make use of this
similarly to the way we make use of the context switching fp/vec save
restore.
This improves code reuse, allows some stack space to be saved, and helps
with avoiding VRSAVE updates if they are not required.
-61 cycles (6620) POWER9 virt-mode NULL hcall
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/switch_to.h | 2 +
arch/powerpc/kernel/process.c | 6 ++
arch/powerpc/kvm/book3s_hv.c | 22 +------
arch/powerpc/kvm/book3s_hv.h | 3 -
arch/powerpc/kvm/book3s_hv_p9_entry.c | 88 +++++++++++++++++++--------
5 files changed, 72 insertions(+), 49 deletions(-)
@@ -4410,9 +4410,6 @@ static int kvmppc_vcpu_run_hv(struct kvm_vcpu *vcpu)structkvm_run*run=vcpu->run;intr;intsrcu_idx;-unsignedlongebb_regs[3]={};/* shut up GCC */-unsignedlonguser_tar=0;-unsignedintuser_vrsave;structkvm*kvm;unsignedlongmsr;
@@ -4473,14 +4470,7 @@ static int kvmppc_vcpu_run_hv(struct kvm_vcpu *vcpu)save_user_regs_kvm();-/* Save userspace EBB and other register values */-if(cpu_has_feature(CPU_FTR_ARCH_207S)){-ebb_regs[0]=mfspr(SPRN_EBBHR);-ebb_regs[1]=mfspr(SPRN_EBBRR);-ebb_regs[2]=mfspr(SPRN_BESCR);-user_tar=mfspr(SPRN_TAR);-}-user_vrsave=mfspr(SPRN_VRSAVE);+kvmppc_save_current_sprs();vcpu->arch.waitp=&vcpu->arch.vcore->wait;vcpu->arch.pgdir=kvm->mm->pgd;
@@ -4521,17 +4511,9 @@ static int kvmppc_vcpu_run_hv(struct kvm_vcpu *vcpu)}}while(is_kvmppc_resume_guest(r));-/* Restore userspace EBB and other register values */-if(cpu_has_feature(CPU_FTR_ARCH_207S)){-mtspr(SPRN_EBBHR,ebb_regs[0]);-mtspr(SPRN_EBBRR,ebb_regs[1]);-mtspr(SPRN_BESCR,ebb_regs[2]);-mtspr(SPRN_TAR,user_tar);-}-mtspr(SPRN_VRSAVE,user_vrsave);-vcpu->arch.state=KVMPPC_VCPU_NOTREADY;atomic_dec(&kvm->arch.vcpus_running);+returnr;}
@@ -217,15 +217,26 @@ EXPORT_SYMBOL_GPL(switch_pmu_to_host);staticvoidload_spr_state(structkvm_vcpu*vcpu,structp9_host_os_sprs*host_os_sprs){+/* TAR is very fast */mtspr(SPRN_TAR,vcpu->arch.tar);+#ifdef CONFIG_ALTIVEC+if(cpu_has_feature(CPU_FTR_ALTIVEC)&&+current->thread.vrsave!=vcpu->arch.vrsave)+mtspr(SPRN_VRSAVE,vcpu->arch.vrsave);+#endif+if(vcpu->arch.hfscr&HFSCR_EBB){-mtspr(SPRN_EBBHR,vcpu->arch.ebbhr);-mtspr(SPRN_EBBRR,vcpu->arch.ebbrr);-mtspr(SPRN_BESCR,vcpu->arch.bescr);+if(current->thread.ebbhr!=vcpu->arch.ebbhr)+mtspr(SPRN_EBBHR,vcpu->arch.ebbhr);+if(current->thread.ebbrr!=vcpu->arch.ebbrr)+mtspr(SPRN_EBBRR,vcpu->arch.ebbrr);+if(current->thread.bescr!=vcpu->arch.bescr)+mtspr(SPRN_BESCR,vcpu->arch.bescr);}-if(!cpu_has_feature(CPU_FTR_ARCH_31))+if(!cpu_has_feature(CPU_FTR_ARCH_31)&&+current->thread.tidr!=vcpu->arch.tid)mtspr(SPRN_TIDR,vcpu->arch.tid);if(host_os_sprs->iamr!=vcpu->arch.iamr)mtspr(SPRN_IAMR,vcpu->arch.iamr);
@@ -350,26 +352,60 @@ EXPORT_SYMBOL_GPL(save_p9_host_os_sprs);voidrestore_p9_host_os_sprs(structkvm_vcpu*vcpu,structp9_host_os_sprs*host_os_sprs){+/*+*current->thread.xxxregistersmustallberestoredtohost+*valuesbeforeapotentialcontextswitch,othrewisethecontext+*switchitselfwilloverwritecurrent->thread.xxxwiththevalues+*fromtheguestSPRs.+*/+mtspr(SPRN_SPRG_VDSO_WRITE,local_paca->sprg_vdso);-if(!cpu_has_feature(CPU_FTR_ARCH_31))-mtspr(SPRN_TIDR,host_os_sprs->tidr);+if(!cpu_has_feature(CPU_FTR_ARCH_31)&&+current->thread.tidr!=vcpu->arch.tid)+mtspr(SPRN_TIDR,current->thread.tidr);if(host_os_sprs->iamr!=vcpu->arch.iamr)mtspr(SPRN_IAMR,host_os_sprs->iamr);if(vcpu->arch.uamor!=0)mtspr(SPRN_UAMOR,0);if(host_os_sprs->amr!=vcpu->arch.amr)mtspr(SPRN_AMR,host_os_sprs->amr);-if(host_os_sprs->fscr!=vcpu->arch.fscr)-mtspr(SPRN_FSCR,host_os_sprs->fscr);-if(host_os_sprs->dscr!=vcpu->arch.dscr)-mtspr(SPRN_DSCR,host_os_sprs->dscr);+if(current->thread.fscr!=vcpu->arch.fscr)+mtspr(SPRN_FSCR,current->thread.fscr);+if(current->thread.dscr!=vcpu->arch.dscr)+mtspr(SPRN_DSCR,current->thread.dscr);if(vcpu->arch.pspb!=0)mtspr(SPRN_PSPB,0);/* Save guest CTRL register, set runlatch to 1 */if(!(vcpu->arch.ctrl&1))mtspr(SPRN_CTRLT,1);++#ifdef CONFIG_ALTIVEC+if(cpu_has_feature(CPU_FTR_ALTIVEC)&&+vcpu->arch.vrsave!=current->thread.vrsave)+mtspr(SPRN_VRSAVE,current->thread.vrsave);+#endif+if(vcpu->arch.hfscr&HFSCR_EBB){+if(vcpu->arch.bescr!=current->thread.bescr)+mtspr(SPRN_BESCR,current->thread.bescr);+if(vcpu->arch.ebbhr!=current->thread.ebbhr)+mtspr(SPRN_EBBHR,current->thread.ebbhr);+if(vcpu->arch.ebbrr!=current->thread.ebbrr)+mtspr(SPRN_EBBRR,current->thread.ebbrr);++/*+*Thisislikeload_fpincontextswitching,turnoffthe+*facilityafteritwrapstheu8totryavoidingsaving+*andrestoringtheregisterseachpartitionswitch.+*/+vcpu->arch.load_ebb++;+if(!vcpu->arch.load_ebb)+vcpu->arch.hfscr&=~HFSCR_EBB;+}++if(vcpu->arch.tar!=current->thread.tar)+mtspr(SPRN_TAR,current->thread.tar);}EXPORT_SYMBOL_GPL(restore_p9_host_os_sprs);
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:14:36
Tighten up partition switching code synchronisation and comments.
In particular, hwsync ; isync is required after the last access that is
performed in the context of a partition, before the partition is
switched away from.
-301 cycles (6319) POWER9 virt-mode NULL hcall
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_64_mmu_radix.c | 4 +++
arch/powerpc/kvm/book3s_hv_p9_entry.c | 40 +++++++++++++++++++-------
2 files changed, 33 insertions(+), 11 deletions(-)
@@ -53,6 +53,8 @@ unsigned long __kvmhv_copy_tofrom_guest_radix(int lpid, int pid,preempt_disable();+asmvolatile("hwsync":::"memory");+isync();/* switch the lpid first to avoid running host with unallocated pid */old_lpid=mfspr(SPRN_LPID);if(old_lpid!=lpid)
@@ -69,6 +71,8 @@ unsigned long __kvmhv_copy_tofrom_guest_radix(int lpid, int pid,elseret=copy_to_user_nofault((void__user*)to,from,n);+asmvolatile("hwsync":::"memory");+isync();/* switch the pid first to avoid running host with unallocated pid */if(quadrant==1&&pid!=old_pid)mtspr(SPRN_PID,old_pid);
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:15:00
Some of the DAWR SPR access is already predicated on dawr_enabled(),
apply this to the remainder of the accesses.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv_p9_entry.c | 34 ++++++++++++++++-----------
1 file changed, 20 insertions(+), 14 deletions(-)
@@ -621,6 +621,7 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcunsignedlonghost_dawr0;unsignedlonghost_dawrx0;unsignedlonghost_psscr;+unsignedlonghost_hpsscr;unsignedlonghost_pidr;unsignedlonghost_dawr1;unsignedlonghost_dawrx1;
@@ -638,7 +639,9 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpchost_hfscr=mfspr(SPRN_HFSCR);host_ciabr=mfspr(SPRN_CIABR);-host_psscr=mfspr(SPRN_PSSCR);+host_psscr=mfspr(SPRN_PSSCR_PR);+if(cpu_has_feature(CPU_FTRS_POWER9_DD2_2))+host_hpsscr=mfspr(SPRN_PSSCR);host_pidr=mfspr(SPRN_PID);if(dawr_enabled()){
@@ -719,8 +722,14 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcif(vcpu->arch.ciabr!=host_ciabr)mtspr(SPRN_CIABR,vcpu->arch.ciabr);-mtspr(SPRN_PSSCR,vcpu->arch.psscr|PSSCR_EC|-(local_paca->kvm_hstate.fake_suspend<<PSSCR_FAKE_SUSPEND_LG));++if(cpu_has_feature(CPU_FTRS_POWER9_DD2_2)){+mtspr(SPRN_PSSCR,vcpu->arch.psscr|PSSCR_EC|+(local_paca->kvm_hstate.fake_suspend<<PSSCR_FAKE_SUSPEND_LG));+}else{+if(vcpu->arch.psscr!=host_psscr)+mtspr(SPRN_PSSCR_PR,vcpu->arch.psscr);+}mtspr(SPRN_HFSCR,vcpu->arch.hfscr);
@@ -905,7 +914,7 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcvcpu->arch.ic=mfspr(SPRN_IC);vcpu->arch.pid=mfspr(SPRN_PID);-vcpu->arch.psscr=mfspr(SPRN_PSSCR)&PSSCR_GUEST_VIS;+vcpu->arch.psscr=mfspr(SPRN_PSSCR_PR);vcpu->arch.shregs.sprg0=mfspr(SPRN_SPRG0);vcpu->arch.shregs.sprg1=mfspr(SPRN_SPRG1);
@@ -948,9 +957,12 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcmtspr(SPRN_PURR,local_paca->kvm_hstate.host_purr);mtspr(SPRN_SPURR,local_paca->kvm_hstate.host_spurr);-/* Preserve PSSCR[FAKE_SUSPEND] until we've called kvmppc_save_tm_hv */-mtspr(SPRN_PSSCR,host_psscr|-(local_paca->kvm_hstate.fake_suspend<<PSSCR_FAKE_SUSPEND_LG));+if(cpu_has_feature(CPU_FTRS_POWER9_DD2_2)){+/* Preserve PSSCR[FAKE_SUSPEND] until we've called kvmppc_save_tm_hv */+mtspr(SPRN_PSSCR,host_hpsscr|+(local_paca->kvm_hstate.fake_suspend<<PSSCR_FAKE_SUSPEND_LG));+}+mtspr(SPRN_HFSCR,host_hfscr);if(vcpu->arch.ciabr!=host_ciabr)mtspr(SPRN_CIABR,host_ciabr);
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:15:59
Use the existing TLB flushing logic to IPI the previous CPU and run the
necessary barriers before running a guest vCPU on a new physical CPU,
to do the necessary radix GTSE barriers for handling the case of an
interrupted guest tlbie sequence.
This results in more IPIs than the TLB flush logic requires, but it's
a significant win for common case scheduling when the vCPU remains on
the same physical CPU.
-522 cycles (5754) POWER9 virt-mode NULL hcall
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 31 +++++++++++++++++++++++----
arch/powerpc/kvm/book3s_hv_p9_entry.c | 9 --------
2 files changed, 27 insertions(+), 13 deletions(-)
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:16:23
mftb() is expensive and one can be avoided on nested guest dispatch.
If the time checking code distinguishes between the L0 timer and the
nested HV timer, then both can be tested in the same place with the
same mftb() value.
This also nicely illustrates the relationship between the L0 and nested
HV timers.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/kvm_asm.h | 1 +
arch/powerpc/kvm/book3s_hv.c | 12 ++++++++++++
arch/powerpc/kvm/book3s_hv_nested.c | 5 -----
3 files changed, 13 insertions(+), 5 deletions(-)
@@ -1410,6 +1410,10 @@ static int kvmppc_handle_exit_hv(struct kvm_vcpu *vcpu,run->ready_for_interrupt_injection=1;switch(vcpu->arch.trap){/* We're good on these - the host merely wanted to get our attention */+caseBOOK3S_INTERRUPT_NESTED_HV_DECREMENTER:+WARN_ON_ONCE(1);/* Should never happen */+vcpu->arch.trap=BOOK3S_INTERRUPT_HV_DECREMENTER;+fallthrough;caseBOOK3S_INTERRUPT_HV_DECREMENTER:vcpu->stat.dec_exits++;r=RESUME_GUEST;
@@ -1737,6 +1741,12 @@ static int kvmppc_handle_nested_exit(struct kvm_vcpu *vcpu)vcpu->stat.ext_intr_exits++;r=RESUME_GUEST;break;+/* These need to go to the nested HV */+caseBOOK3S_INTERRUPT_NESTED_HV_DECREMENTER:+vcpu->arch.trap=BOOK3S_INTERRUPT_HV_DECREMENTER;+vcpu->stat.dec_exits++;+r=RESUME_HOST;+break;/* SR/HMI/PMI are HV interrupts that host has handled. Resume guest.*/caseBOOK3S_INTERRUPT_HMI:caseBOOK3S_INTERRUPT_PERFMON:
@@ -3855,6 +3865,8 @@ static int kvmhv_p9_guest_entry(struct kvm_vcpu *vcpu, u64 time_limit,returnBOOK3S_INTERRUPT_HV_DECREMENTER;if(next_timer<time_limit)time_limit=next_timer;+elseif(*tb>=time_limit)/* nested time limit */+returnBOOK3S_INTERRUPT_NESTED_HV_DECREMENTER;vcpu->arch.ceded=0;
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:16:46
Rearrange the MSR saving on entry so it does not follow the mtmsrd to
disable interrupts, avoiding a possible RAW scoreboard stall.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/include/asm/kvm_book3s_64.h | 2 +
arch/powerpc/kvm/book3s_hv.c | 18 ++-----
arch/powerpc/kvm/book3s_hv_p9_entry.c | 66 +++++++++++++++---------
3 files changed, 47 insertions(+), 39 deletions(-)
@@ -3769,24 +3771,10 @@ static int kvmhv_vcpu_entry_p9_nested(struct kvm_vcpu *vcpu, u64 time_limit, uns*/host_psscr=mfspr(SPRN_PSSCR_PR);-hard_irq_disable();+kvmppc_msr_hard_disable_set_facilities(vcpu,msr);if(lazy_irq_pending())return0;-/* MSR bits may have been cleared by context switch */-msr=0;-if(IS_ENABLED(CONFIG_PPC_FPU))-msr|=MSR_FP;-if(cpu_has_feature(CPU_FTR_ALTIVEC))-msr|=MSR_VEC;-if(cpu_has_feature(CPU_FTR_VSX))-msr|=MSR_VSX;-if((cpu_has_feature(CPU_FTR_TM)||-cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))&&-(vcpu->arch.hfscr&HFSCR_TM))-msr|=MSR_TM;-msr=msr_check_and_set(msr);-load_vcpu_state(vcpu,&host_os_sprs);if(vcpu->arch.psscr!=host_psscr)
@@ -604,6 +604,44 @@ static void save_clear_guest_mmu(struct kvm *kvm, struct kvm_vcpu *vcpu)}}+unsignedlongkvmppc_msr_hard_disable_set_facilities(structkvm_vcpu*vcpu,unsignedlongmsr)+{+unsignedlongmsr_needed=0;++msr&=~MSR_EE;++/* MSR bits may have been cleared by context switch so must recheck */+if(IS_ENABLED(CONFIG_PPC_FPU))+msr_needed|=MSR_FP;+if(cpu_has_feature(CPU_FTR_ALTIVEC))+msr_needed|=MSR_VEC;+if(cpu_has_feature(CPU_FTR_VSX))+msr_needed|=MSR_VSX;+if((cpu_has_feature(CPU_FTR_TM)||+cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))&&+(vcpu->arch.hfscr&HFSCR_TM))+msr_needed|=MSR_TM;++/*+*ThiscouldbecombinedwithMSR[RI]clearing,butthatexpands+*theunrecoverablewindow.Itwouldbebettertocoverunrecoverable+*withKVMbadinterrupthandlingratherthanuseMSR[RI]atall.+*+*MuchmoredifficultandlessworthwhiletocombinewithIR/DR+*disable.+*/+if((msr&msr_needed)!=msr_needed){+msr|=msr_needed;+__mtmsrd(msr,0);+}else{+__hard_irq_disable();+}+local_paca->irq_happened|=PACA_IRQ_HARD_DIS;++returnmsr;+}+EXPORT_SYMBOL_GPL(kvmppc_msr_hard_disable_set_facilities);+intkvmhv_vcpu_entry_p9(structkvm_vcpu*vcpu,u64time_limit,unsignedlonglpcr,u64*tb){structp9_host_os_sprshost_os_sprs;
@@ -637,6 +675,9 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcvcpu->arch.ceded=0;+/* Save MSR for restore, with EE clear. */+msr=mfmsr()&~MSR_EE;+host_hfscr=mfspr(SPRN_HFSCR);host_ciabr=mfspr(SPRN_CIABR);host_psscr=mfspr(SPRN_PSSCR_PR);
@@ -658,35 +699,12 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcsave_p9_host_os_sprs(&host_os_sprs);-/*-*ThiscouldbecombinedwithMSR[RI]clearing,butthatexpands-*theunrecoverablewindow.Itwouldbebettertocoverunrecoverable-*withKVMbadinterrupthandlingratherthanuseMSR[RI]atall.-*-*MuchmoredifficultandlessworthwhiletocombinewithIR/DR-*disable.-*/-hard_irq_disable();+msr=kvmppc_msr_hard_disable_set_facilities(vcpu,msr);if(lazy_irq_pending()){trap=0;gotoout;}-/* MSR bits may have been cleared by context switch */-msr=0;-if(IS_ENABLED(CONFIG_PPC_FPU))-msr|=MSR_FP;-if(cpu_has_feature(CPU_FTR_ALTIVEC))-msr|=MSR_VEC;-if(cpu_has_feature(CPU_FTR_VSX))-msr|=MSR_VSX;-if((cpu_has_feature(CPU_FTR_TM)||-cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))&&-(vcpu->arch.hfscr&HFSCR_TM))-msr|=MSR_TM;-msr=msr_check_and_set(msr);-/* Save MSR for restore. This is after hard disable, so EE is clear. */-if(vc->tb_offset){u64new_tb=*tb+vc->tb_offset;mtspr(SPRN_TBU40,new_tb);
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-06-22 11:17:10
slbmfee/slbmfev instructions are very expensive, moreso than a regular
mfspr instruction, so minimising them significantly improves hash guest
exit performance. The slbmfev is only required if slbmfee found a valid
SLB entry.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv_p9_entry.c | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
This register is not architected and not implemented in POWER9 or 10,
it just reads back zeroes for compatibility.
-78 cycles (9255) cycles POWER9 virt-mode NULL hcall
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
@@ -667,7 +667,6 @@ static unsigned long power9_idle_stop(unsigned long psscr)sprs.purr=mfspr(SPRN_PURR);sprs.spurr=mfspr(SPRN_SPURR);sprs.dscr=mfspr(SPRN_DSCR);-sprs.wort=mfspr(SPRN_WORT);sprs.ciabr=mfspr(SPRN_CIABR);sprs.mmcra=mfspr(SPRN_MMCRA);
@@ -785,7 +784,6 @@ static unsigned long power9_idle_stop(unsigned long psscr)mtspr(SPRN_PURR,sprs.purr);mtspr(SPRN_SPURR,sprs.spurr);mtspr(SPRN_DSCR,sprs.dscr);-mtspr(SPRN_WORT,sprs.wort);mtspr(SPRN_CIABR,sprs.ciabr);mtspr(SPRN_MMCRA,sprs.mmcra);
Some of the DAWR SPR access is already predicated on dawr_enabled(),
apply this to the remainder of the accesses.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv_p9_entry.c | 34 ++++++++++++++++-----------
1 file changed, 20 insertions(+), 14 deletions(-)
@@ -638,13 +638,16 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpchost_hfscr=mfspr(SPRN_HFSCR);host_ciabr=mfspr(SPRN_CIABR);-host_dawr0=mfspr(SPRN_DAWR0);-host_dawrx0=mfspr(SPRN_DAWRX0);host_psscr=mfspr(SPRN_PSSCR);host_pidr=mfspr(SPRN_PID);-if(cpu_has_feature(CPU_FTR_DAWR1)){-host_dawr1=mfspr(SPRN_DAWR1);-host_dawrx1=mfspr(SPRN_DAWRX1);++if(dawr_enabled()){+host_dawr0=mfspr(SPRN_DAWR0);+host_dawrx0=mfspr(SPRN_DAWRX0);+if(cpu_has_feature(CPU_FTR_DAWR1)){+host_dawr1=mfspr(SPRN_DAWR1);+host_dawrx1=mfspr(SPRN_DAWRX1);
The userspace needs to enable DAWR1 via KVM_CAP_PPC_DAWR1. That cap is
not even implemented in QEMU currently, so we never allow the guest to
set vcpu->arch.dawr1. If we check for kvm->arch.dawr1_enabled instead of
the CPU feature, we could shave some more time here.
This register controls supervisor SPR modifications, and as such is only
relevant for KVM. KVM always sets AMOR to ~0 on guest entry, and never
restores it coming back out to the host, so it can be kept constant and
avoid the mtSPR in KVM guest entry.
-21 cycles (9116) cycles POWER9 virt-mode NULL hcall
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
@@ -306,8 +306,8 @@ struct p7_sprs {/* per thread SPRs that get lost in shallow states */u64amr;u64iamr;-u64amor;u64uamor;+/* amor is restored to constant ~0 */};staticunsignedlongpower7_idle_insn(unsignedlongtype)
@@ -378,7 +378,6 @@ static unsigned long power7_idle_insn(unsigned long type)if(cpu_has_feature(CPU_FTR_ARCH_207S)){sprs.amr=mfspr(SPRN_AMR);sprs.iamr=mfspr(SPRN_IAMR);-sprs.amor=mfspr(SPRN_AMOR);sprs.uamor=mfspr(SPRN_UAMOR);}
@@ -397,7 +396,7 @@ static unsigned long power7_idle_insn(unsigned long type)*/mtspr(SPRN_AMR,sprs.amr);mtspr(SPRN_IAMR,sprs.iamr);-mtspr(SPRN_AMOR,sprs.amor);+mtspr(SPRN_AMOR,~0);mtspr(SPRN_UAMOR,sprs.uamor);}}
@@ -687,7 +686,6 @@ static unsigned long power9_idle_stop(unsigned long psscr)sprs.amr=mfspr(SPRN_AMR);sprs.iamr=mfspr(SPRN_IAMR);-sprs.amor=mfspr(SPRN_AMOR);sprs.uamor=mfspr(SPRN_UAMOR);srr1=isa300_idle_stop_mayloss(psscr);/* go idle */
@@ -708,7 +706,7 @@ static unsigned long power9_idle_stop(unsigned long psscr)*/mtspr(SPRN_AMR,sprs.amr);mtspr(SPRN_IAMR,sprs.iamr);-mtspr(SPRN_AMOR,sprs.amor);+mtspr(SPRN_AMOR,~0);mtspr(SPRN_UAMOR,sprs.uamor);/*
HV interrupts may be taken with the MMU enabled when radix guests are
running. Enable LPCR[HAIL] on ISA v3.1 processors for radix guests.
Make this depend on the host LPCR[HAIL] being enabled. Currently that is
always enabled, but having this test means any issue that might require
LPCR[HAIL] to be disabled in the host will not have to be duplicated in
KVM.
-1380 cycles on P10 NULL hcall entry+exit
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
@@ -2948,6 +2948,13 @@ static void kvmppc_start_thread(struct kvm_vcpu *vcpu, struct kvmppc_vcore *vc)kvmppc_ipi_thread(cpu);}+/* Old path does this in asm */+staticvoidkvmppc_stop_thread(structkvm_vcpu*vcpu)+{+vcpu->cpu=-1;+vcpu->arch.thread_cpu=-1;+}+staticvoidkvmppc_wait_for_nap(intn_threads){intcpu=smp_processor_id();
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-07-01 08:05:12
Excerpts from Fabiano Rosas's message of July 1, 2021 3:51 am:
Nicholas Piggin [off-list ref] writes:
quoted
Some of the DAWR SPR access is already predicated on dawr_enabled(),
apply this to the remainder of the accesses.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv_p9_entry.c | 34 ++++++++++++++++-----------
1 file changed, 20 insertions(+), 14 deletions(-)
@@ -638,13 +638,16 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpchost_hfscr=mfspr(SPRN_HFSCR);host_ciabr=mfspr(SPRN_CIABR);-host_dawr0=mfspr(SPRN_DAWR0);-host_dawrx0=mfspr(SPRN_DAWRX0);host_psscr=mfspr(SPRN_PSSCR);host_pidr=mfspr(SPRN_PID);-if(cpu_has_feature(CPU_FTR_DAWR1)){-host_dawr1=mfspr(SPRN_DAWR1);-host_dawrx1=mfspr(SPRN_DAWRX1);++if(dawr_enabled()){+host_dawr0=mfspr(SPRN_DAWR0);+host_dawrx0=mfspr(SPRN_DAWRX0);+if(cpu_has_feature(CPU_FTR_DAWR1)){+host_dawr1=mfspr(SPRN_DAWR1);+host_dawrx1=mfspr(SPRN_DAWRX1);
The userspace needs to enable DAWR1 via KVM_CAP_PPC_DAWR1. That cap is
not even implemented in QEMU currently, so we never allow the guest to
set vcpu->arch.dawr1. If we check for kvm->arch.dawr1_enabled instead of
the CPU feature, we could shave some more time here.
KVM PMU management code looks for particular frozen/disabled bits in
the PMU registers so it knows whether it must clear them when coming
out of a guest or not. Setting this up helps KVM make these optimisations
without getting confused. Longer term the better approach might be to
move guest/host PMU switching to the perf subsystem.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/cpu_setup_power.c | 4 ++--
arch/powerpc/kernel/dt_cpu_ftrs.c | 6 +++---
arch/powerpc/kvm/book3s_hv.c | 5 +++++
arch/powerpc/perf/core-book3s.c | 7 +++++++
4 files changed, 17 insertions(+), 5 deletions(-)
Sticky point here is, currently if not frozen, pmc5/6 will
keep countering. And not freezing them at boot is quiet useful
sometime, like say when running in a simulation where we could calculate
approx CPIs for micro benchmarks without perf subsystem.
@@ -2593,6 +2593,11 @@ static int kvmppc_core_vcpu_create_hv(struct kvm_vcpu *vcpu)#endif#endifvcpu->arch.mmcr[0]=MMCR0_FC;+if(cpu_has_feature(CPU_FTR_ARCH_31)){+vcpu->arch.mmcr[0]|=MMCR0_PMCCEXT;+vcpu->arch.mmcra=MMCRA_BHRB_DISABLE;+}+vcpu->arch.ctrl=CTRL_RUNLATCH;/* default to host PVR, since we can't spoof it */kvmppc_set_pvr_hv(vcpu,mfspr(SPRN_PVR));
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-07-02 00:27:44
Excerpts from Madhavan Srinivasan's message of July 1, 2021 11:17 pm:
On 6/22/21 4:27 PM, Nicholas Piggin wrote:
quoted
KVM PMU management code looks for particular frozen/disabled bits in
the PMU registers so it knows whether it must clear them when coming
out of a guest or not. Setting this up helps KVM make these optimisations
without getting confused. Longer term the better approach might be to
move guest/host PMU switching to the perf subsystem.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/cpu_setup_power.c | 4 ++--
arch/powerpc/kernel/dt_cpu_ftrs.c | 6 +++---
arch/powerpc/kvm/book3s_hv.c | 5 +++++
arch/powerpc/perf/core-book3s.c | 7 +++++++
4 files changed, 17 insertions(+), 5 deletions(-)
Sticky point here is, currently if not frozen, pmc5/6 will
keep countering. And not freezing them at boot is quiet useful
sometime, like say when running in a simulation where we could calculate
approx CPIs for micro benchmarks without perf subsystem.
You even can't use the sysfs files in this sim environment? In that case
what if we added a boot option that could set some things up? In that
case possibly you could even gather some more types of events too.
Thanks,
Nick
On 22-Jun-2021, at 4:27 PM, Nicholas Piggin [off-list ref] wrote:
Move the P9 guest/host register switching functions to the built-in
P9 entry code, and export it for nested to use as well.
This allows more flexibility in scheduling these supervisor privileged
SPR accesses with the HV privileged and PR SPR accesses in the low level
entry code.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 351 +-------------------------
arch/powerpc/kvm/book3s_hv.h | 39 +++
arch/powerpc/kvm/book3s_hv_p9_entry.c | 332 ++++++++++++++++++++++++
3 files changed, 372 insertions(+), 350 deletions(-)
create mode 100644 arch/powerpc/kvm/book3s_hv.h
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-07-08 12:46:28
Excerpts from Nicholas Piggin's message of July 2, 2021 10:27 am:
Excerpts from Madhavan Srinivasan's message of July 1, 2021 11:17 pm:
quoted
On 6/22/21 4:27 PM, Nicholas Piggin wrote:
quoted
KVM PMU management code looks for particular frozen/disabled bits in
the PMU registers so it knows whether it must clear them when coming
out of a guest or not. Setting this up helps KVM make these optimisations
without getting confused. Longer term the better approach might be to
move guest/host PMU switching to the perf subsystem.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/cpu_setup_power.c | 4 ++--
arch/powerpc/kernel/dt_cpu_ftrs.c | 6 +++---
arch/powerpc/kvm/book3s_hv.c | 5 +++++
arch/powerpc/perf/core-book3s.c | 7 +++++++
4 files changed, 17 insertions(+), 5 deletions(-)
Sticky point here is, currently if not frozen, pmc5/6 will
keep countering. And not freezing them at boot is quiet useful
sometime, like say when running in a simulation where we could calculate
approx CPIs for micro benchmarks without perf subsystem.
You even can't use the sysfs files in this sim environment? In that case
what if we added a boot option that could set some things up? In that
case possibly you could even gather some more types of events too.
What if we added this to allow sim environments to run PMC5/6 and
additionally specify MMCR1 without userspace involvement?
Thanks,
Nick
---
@@ -2425,8 +2425,24 @@ int register_power_pmu(struct power_pmu *pmu)}#ifdef CONFIG_PPC64+staticboolpmu_override=false;+staticunsignedlongpmu_override_val;+staticvoiddo_pmu_override(void*data)+{+ppc_set_pmu_inuse(1);+if(pmu_override_val)+mtspr(SPRN_MMCR1,pmu_override_val);+mtspr(SPRN_MMCR0,mfspr(SPRN_MMCR0)&~MMCR0_FC);+}+staticint__initinit_ppc64_pmu(void){+if(cpu_has_feature(CPU_FTR_HVMODE)&&pmu_override){+printk(KERN_WARNING"perf: disabling perf due to pmu= command line option.\n");+on_each_cpu(do_pmu_override,NULL,1);+return0;+}+/* run through all the pmu drivers one at a time */if(!init_power5_pmu())return0;
@@ -2448,4 +2464,23 @@ static int __init init_ppc64_pmu(void)returninit_generic_compat_pmu();}early_initcall(init_ppc64_pmu);++staticint__initpmu_setup(char*str)+{+unsignedlongval;++if(!early_cpu_has_feature(CPU_FTR_HVMODE))+return0;++pmu_override=true;++if(kstrtoul(str,0,&val))+val=0;++pmu_override_val=val;++return1;+}+__setup("pmu=",pmu_setup);+#endif
Use HFSCR facility disabling to implement demand faulting for EBB, with
a hysteresis counter similar to the load_fp etc counters in context
switching that implement the equivalent demand faulting for userspace
facilities.
This speeds up guest entry/exit by avoiding the register save/restore
when a guest is not frequently using them. When a guest does use them
often, there will be some additional demand fault overhead, but these
are not commonly used facilities.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
@@ -168,7 +168,8 @@ static void sanitise_hv_regs(struct kvm_vcpu *vcpu, struct hv_guest_state *hr)*butpreservetheinterruptcausefieldandfacilitiesthatmight*bedisabledfordemandfaultingintheL1.*/-hr->hfscr&=(HFSCR_INTR_CAUSE|HFSCR_PM|vcpu->arch.hfscr);+hr->hfscr&=(HFSCR_INTR_CAUSE|HFSCR_PM|HFSCR_EBB|+vcpu->arch.hfscr);/* Don't let data address watchpoint match in hypervisor state */hr->dawrx0&=~DAWRX_HYP;
Use HFSCR facility disabling to implement demand faulting for TM, with
a hysteresis counter similar to the load_fp etc counters in context
switching that implement the equivalent demand faulting for userspace
facilities.
This speeds up guest entry/exit by avoiding the register save/restore
when a guest is not frequently using them. When a guest does use them
often, there will be some additional demand fault overhead, but these
are not commonly used facilities.
-304 cycles (6681) POWER9 virt-mode NULL hcall with the previous patch
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
@@ -168,7 +168,7 @@ static void sanitise_hv_regs(struct kvm_vcpu *vcpu, struct hv_guest_state *hr)*butpreservetheinterruptcausefieldandfacilitiesthatmight*bedisabledfordemandfaultingintheL1.*/-hr->hfscr&=(HFSCR_INTR_CAUSE|HFSCR_PM|HFSCR_EBB|+hr->hfscr&=(HFSCR_INTR_CAUSE|HFSCR_PM|HFSCR_TM|HFSCR_EBB|vcpu->arch.hfscr);/* Don't let data address watchpoint match in hypervisor state */
@@ -326,6 +328,9 @@ void store_vcpu_state(struct kvm_vcpu *vcpu)vcpu->arch.tfhar=mfspr(SPRN_TFHAR);vcpu->arch.tfiar=mfspr(SPRN_TFIAR);}+vcpu->arch.load_tm++;/* see load_ebb comment for details */+if(!vcpu->arch.load_tm)+vcpu->arch.hfscr&=~HFSCR_TM;}}EXPORT_SYMBOL_GPL(store_vcpu_state);
@@ -615,8 +620,9 @@ int kvmhv_vcpu_entry_p9(struct kvm_vcpu *vcpu, u64 time_limit, unsigned long lpcmsr|=MSR_VEC;if(cpu_has_feature(CPU_FTR_VSX))msr|=MSR_VSX;-if(cpu_has_feature(CPU_FTR_TM)||-cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))+if((cpu_has_feature(CPU_FTR_TM)||+cpu_has_feature(CPU_FTR_P9_TM_HV_ASSIST))&&+(vcpu->arch.hfscr&HFSCR_TM))msr|=MSR_TM;msr=msr_check_and_set(msr);/* Save MSR for restore. This is after hard disable, so EE is clear. */
trace_kvmppc_run_core(vc, 1);
}
+/*
+ * Privileged (non-hypervisor) host registers to save.
+ */
+struct p9_host_os_sprs {
+ unsigned long dscr;
+ unsigned long tidr;
+ unsigned long iamr;
+ unsigned long amr;
+ unsigned long fscr;
+
+ unsigned int pmc1;
+ unsigned int pmc2;
+ unsigned int pmc3;
+ unsigned int pmc4;
+ unsigned int pmc5;
+ unsigned int pmc6;
+ unsigned long mmcr0;
+ unsigned long mmcr1;
+ unsigned long mmcr2;
+ unsigned long mmcr3;
+ unsigned long mmcra;
+ unsigned long siar;
+ unsigned long sier1;
+ unsigned long sier2;
+ unsigned long sier3;
+ unsigned long sdar;
+};
+
+static void freeze_pmu(unsigned long mmcr0, unsigned long mmcra)
+{
+ if (!(mmcr0 & MMCR0_FC))
+ goto do_freeze;
+ if (mmcra & MMCRA_SAMPLE_ENABLE)
+ goto do_freeze;
+ if (cpu_has_feature(CPU_FTR_ARCH_31)) {
+ if (!(mmcr0 & MMCR0_PMCCEXT))
+ goto do_freeze;
+ if (!(mmcra & MMCRA_BHRB_DISABLE))
+ goto do_freeze;
+ }
+ return;
Hi Nick
When freezing the PMU, do we need to also set pmcregs_in_use to zero ?
Also, why we need these above conditions like MMCRA_SAMPLE_ENABLE, MMCR0_PMCCEXT checks also before freezing ?
blr
/*
+ * void kvmhv_load_host_pmu(void)
+ *
* Reload host PMU state saved in the PACA by kvmhv_save_host_pmu.
*/
-_GLOBAL(kvmhv_load_host_pmu)
-EXPORT_SYMBOL_GPL(kvmhv_load_host_pmu)
+kvmhv_load_host_pmu:
mflr r0
lbz r4, PACA_PMCINUSE(r13) /* is the host using the PMU? */
cmpwi r4, 0
@@ -2886,25 +2878,18 @@ BEGIN_FTR_SECTION
mtspr SPRN_MMCR2, r8
mtspr SPRN_SIER, r9
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
-BEGIN_FTR_SECTION
- ld r5, HSTATE_MMCR3(r13)
- ld r6, HSTATE_SIER2(r13)
- ld r7, HSTATE_SIER3(r13)
- mtspr SPRN_MMCR3, r5
- mtspr SPRN_SIER2, r6
- mtspr SPRN_SIER3, r7
-END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
mtspr SPRN_MMCR0, r3
isync
mtlr r0
23: blr
/*
+ * void kvmhv_save_guest_pmu(struct kvm_vcpu *vcpu, bool pmu_in_use)
+ *
* Save guest PMU state into the vcpu struct.
* r3 = vcpu, r4 = full save flag (PMU in use flag set in VPA)
*/
-_GLOBAL(kvmhv_save_guest_pmu)
-EXPORT_SYMBOL_GPL(kvmhv_save_guest_pmu)
+kvmhv_save_guest_pmu:
mr r9, r3
mr r8, r4
BEGIN_FTR_SECTION
On 22-Jun-2021, at 4:27 PM, Nicholas Piggin [off-list ref] wrote:
KVM PMU management code looks for particular frozen/disabled bits in
the PMU registers so it knows whether it must clear them when coming
out of a guest or not. Setting this up helps KVM make these optimisations
without getting confused. Longer term the better approach might be to
move guest/host PMU switching to the perf subsystem.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/cpu_setup_power.c | 4 ++--
arch/powerpc/kernel/dt_cpu_ftrs.c | 6 +++---
arch/powerpc/kvm/book3s_hv.c | 5 +++++
arch/powerpc/perf/core-book3s.c | 7 +++++++
4 files changed, 17 insertions(+), 5 deletions(-)
Hi Nick,
We are setting these bits in “power_pmu_disable” function. And disable will be called before any event gets deleted/stopped. Can you please help to understand why this is needed in power_pmu_enable path also ?
Thanks
Athira
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-07-12 02:41:41
Excerpts from Athira Rajeev's message of July 10, 2021 12:50 pm:
quoted
On 22-Jun-2021, at 4:27 PM, Nicholas Piggin [off-list ref] wrote:
KVM PMU management code looks for particular frozen/disabled bits in
the PMU registers so it knows whether it must clear them when coming
out of a guest or not. Setting this up helps KVM make these optimisations
without getting confused. Longer term the better approach might be to
move guest/host PMU switching to the perf subsystem.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/cpu_setup_power.c | 4 ++--
arch/powerpc/kernel/dt_cpu_ftrs.c | 6 +++---
arch/powerpc/kvm/book3s_hv.c | 5 +++++
arch/powerpc/perf/core-book3s.c | 7 +++++++
4 files changed, 17 insertions(+), 5 deletions(-)
Hi Nick,
We are setting these bits in “power_pmu_disable” function. And disable will be called before any event gets deleted/stopped. Can you please help to understand why this is needed in power_pmu_enable path also ?
I'll have to go back and check what I needed it for.
Basically what I'm trying to achieve is that when the guest and host
are not running perf, then the registers should match. This way the host
can test them with mfspr but does not need to fix them with mtspr.
It's not too important for performance after TM facility demand faulting
and the nested guest PMU fix means you can usually just skip that
entirely, but I think it's cleaner. I'll double check my perf/ changes
it's possible that part should be split out or is unnecessary.
Thanks,
Nick
trace_kvmppc_run_core(vc, 1);
}
+/*
+ * Privileged (non-hypervisor) host registers to save.
+ */
+struct p9_host_os_sprs {
+ unsigned long dscr;
+ unsigned long tidr;
+ unsigned long iamr;
+ unsigned long amr;
+ unsigned long fscr;
+
+ unsigned int pmc1;
+ unsigned int pmc2;
+ unsigned int pmc3;
+ unsigned int pmc4;
+ unsigned int pmc5;
+ unsigned int pmc6;
+ unsigned long mmcr0;
+ unsigned long mmcr1;
+ unsigned long mmcr2;
+ unsigned long mmcr3;
+ unsigned long mmcra;
+ unsigned long siar;
+ unsigned long sier1;
+ unsigned long sier2;
+ unsigned long sier3;
+ unsigned long sdar;
+};
+
+static void freeze_pmu(unsigned long mmcr0, unsigned long mmcra)
+{
+ if (!(mmcr0 & MMCR0_FC))
+ goto do_freeze;
+ if (mmcra & MMCRA_SAMPLE_ENABLE)
+ goto do_freeze;
+ if (cpu_has_feature(CPU_FTR_ARCH_31)) {
+ if (!(mmcr0 & MMCR0_PMCCEXT))
+ goto do_freeze;
+ if (!(mmcra & MMCRA_BHRB_DISABLE))
+ goto do_freeze;
+ }
+ return;
Hi Nick
When freezing the PMU, do we need to also set pmcregs_in_use to zero ?
Not immediately, we still need to save out the values of the PMU
registers. If we clear pmcregs_in_use, then our hypervisor can discard
the contents of those registers at any time.
Also, why we need these above conditions like MMCRA_SAMPLE_ENABLE, MMCR0_PMCCEXT checks also before freezing ?
Basically just because that's the condition we wnat to set the PMU to
before entering the guest if the guest does not have its own PMU
registers in use.
I'm not entirely sure this is correct / optimal for perf though, so we
should double check that. I think some of this stuff should be wrapped
up and put into perf/ subdirectory as I've said before. KVM shouldn't
need to know about exactly how PMU is to be set up and managed by
perf, we should just be able to ask perf to save/restore/switch state.
Thanks,
Nick
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-07-12 02:51:15
Excerpts from Athira Rajeev's message of July 8, 2021 3:32 pm:
quoted
On 22-Jun-2021, at 4:27 PM, Nicholas Piggin [off-list ref] wrote:
Move the P9 guest/host register switching functions to the built-in
P9 entry code, and export it for nested to use as well.
This allows more flexibility in scheduling these supervisor privileged
SPR accesses with the HV privileged and PR SPR accesses in the low level
entry code.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kvm/book3s_hv.c | 351 +-------------------------
arch/powerpc/kvm/book3s_hv.h | 39 +++
arch/powerpc/kvm/book3s_hv_p9_entry.c | 332 ++++++++++++++++++++++++
3 files changed, 372 insertions(+), 350 deletions(-)
create mode 100644 arch/powerpc/kvm/book3s_hv.h
Excerpts from Madhavan Srinivasan's message of July 1, 2021 11:17 pm:
quoted
On 6/22/21 4:27 PM, Nicholas Piggin wrote:
quoted
KVM PMU management code looks for particular frozen/disabled bits in
the PMU registers so it knows whether it must clear them when coming
out of a guest or not. Setting this up helps KVM make these optimisations
without getting confused. Longer term the better approach might be to
move guest/host PMU switching to the perf subsystem.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/cpu_setup_power.c | 4 ++--
arch/powerpc/kernel/dt_cpu_ftrs.c | 6 +++---
arch/powerpc/kvm/book3s_hv.c | 5 +++++
arch/powerpc/perf/core-book3s.c | 7 +++++++
4 files changed, 17 insertions(+), 5 deletions(-)
Sticky point here is, currently if not frozen, pmc5/6 will
keep countering. And not freezing them at boot is quiet useful
sometime, like say when running in a simulation where we could calculate
approx CPIs for micro benchmarks without perf subsystem.
Sorry for a delayed response
You even can't use the sysfs files in this sim environment? In that case
Yes it is possible. Just that we need to have additional patch to maintain
for the sim.
what if we added a boot option that could set some things up? In that
case possibly you could even gather some more types of events too.
Having a boot option will be a over-kill :). I guess we could have
this under config option?
trace_kvmppc_run_core(vc, 1);
}
+/*
+ * Privileged (non-hypervisor) host registers to save.
+ */
+struct p9_host_os_sprs {
+ unsigned long dscr;
+ unsigned long tidr;
+ unsigned long iamr;
+ unsigned long amr;
+ unsigned long fscr;
+
+ unsigned int pmc1;
+ unsigned int pmc2;
+ unsigned int pmc3;
+ unsigned int pmc4;
+ unsigned int pmc5;
+ unsigned int pmc6;
+ unsigned long mmcr0;
+ unsigned long mmcr1;
+ unsigned long mmcr2;
+ unsigned long mmcr3;
+ unsigned long mmcra;
+ unsigned long siar;
+ unsigned long sier1;
+ unsigned long sier2;
+ unsigned long sier3;
+ unsigned long sdar;
+};
+
+static void freeze_pmu(unsigned long mmcr0, unsigned long mmcra)
+{
+ if (!(mmcr0 & MMCR0_FC))
+ goto do_freeze;
+ if (mmcra & MMCRA_SAMPLE_ENABLE)
+ goto do_freeze;
+ if (cpu_has_feature(CPU_FTR_ARCH_31)) {
+ if (!(mmcr0 & MMCR0_PMCCEXT))
+ goto do_freeze;
+ if (!(mmcra & MMCRA_BHRB_DISABLE))
+ goto do_freeze;
+ }
+ return;
Hi Nick
When freezing the PMU, do we need to also set pmcregs_in_use to zero ?
Not immediately, we still need to save out the values of the PMU
registers. If we clear pmcregs_in_use, then our hypervisor can discard
the contents of those registers at any time.
quoted
Also, why we need these above conditions like MMCRA_SAMPLE_ENABLE, MMCR0_PMCCEXT checks also before freezing ?
Basically just because that's the condition we wnat to set the PMU to
before entering the guest if the guest does not have its own PMU
registers in use.
I'm not entirely sure this is correct / optimal for perf though, so we
should double check that. I think some of this stuff should be wrapped
up and put into perf/ subdirectory as I've said before. KVM shouldn't
need to know about exactly how PMU is to be set up and managed by
perf, we should just be able to ask perf to save/restore/switch state.
Hi Nick,
Agree to your point. It makes sense that some of these perf code should be moved under perf/ directory.
Athira
From: Nicholas Piggin <npiggin@gmail.com> Date: 2021-07-14 12:39:50
Excerpts from Nicholas Piggin's message of July 12, 2021 12:41 pm:
Excerpts from Athira Rajeev's message of July 10, 2021 12:50 pm:
quoted
quoted
On 22-Jun-2021, at 4:27 PM, Nicholas Piggin [off-list ref] wrote:
KVM PMU management code looks for particular frozen/disabled bits in
the PMU registers so it knows whether it must clear them when coming
out of a guest or not. Setting this up helps KVM make these optimisations
without getting confused. Longer term the better approach might be to
move guest/host PMU switching to the perf subsystem.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/cpu_setup_power.c | 4 ++--
arch/powerpc/kernel/dt_cpu_ftrs.c | 6 +++---
arch/powerpc/kvm/book3s_hv.c | 5 +++++
arch/powerpc/perf/core-book3s.c | 7 +++++++
4 files changed, 17 insertions(+), 5 deletions(-)
Hi Nick,
We are setting these bits in “power_pmu_disable” function. And disable will be called before any event gets deleted/stopped. Can you please help to understand why this is needed in power_pmu_enable path also ?
I'll have to go back and check what I needed it for.
Okay, MMCRA is getting MMCRA_SDAR_MODE_DCACHE set on POWER9, by the looks.
That's not necessarily a problem, but KVM sets MMCRA to 0 to disable
SDAR updates. So KVM and perf don't agree on what the "correct" value
for disabled is. Which could be a problem with POWER10 not setting BHRB
disable before my series.
I'll get rid of this hunk for now, I expect things won't be exactly clean
or consistent until the KVM host PMU code is moved into perf/ though.
Thanks,
Nick
Excerpts from Nicholas Piggin's message of July 12, 2021 12:41 pm:
quoted
Excerpts from Athira Rajeev's message of July 10, 2021 12:50 pm:
quoted
quoted
On 22-Jun-2021, at 4:27 PM, Nicholas Piggin [off-list ref] wrote:
KVM PMU management code looks for particular frozen/disabled bits in
the PMU registers so it knows whether it must clear them when coming
out of a guest or not. Setting this up helps KVM make these optimisations
without getting confused. Longer term the better approach might be to
move guest/host PMU switching to the perf subsystem.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
arch/powerpc/kernel/cpu_setup_power.c | 4 ++--
arch/powerpc/kernel/dt_cpu_ftrs.c | 6 +++---
arch/powerpc/kvm/book3s_hv.c | 5 +++++
arch/powerpc/perf/core-book3s.c | 7 +++++++
4 files changed, 17 insertions(+), 5 deletions(-)
Hi Nick,
We are setting these bits in “power_pmu_disable” function. And disable will be called before any event gets deleted/stopped. Can you please help to understand why this is needed in power_pmu_enable path also ?
I'll have to go back and check what I needed it for.
Okay, MMCRA is getting MMCRA_SDAR_MODE_DCACHE set on POWER9, by the looks.
That's not necessarily a problem, but KVM sets MMCRA to 0 to disable
SDAR updates. So KVM and perf don't agree on what the "correct" value
for disabled is. Which could be a problem with POWER10 not setting BHRB
disable before my series.
Nick,
BHRB disable will be only known to P10 guest kernel and in case of
P9 guest kernel it is not known. And for the P10 host and guest,
I guess we set BHRB_DISABLE in cpu_setup code and also in power_pmu_disable().
So you areseeing P10 guest having MMCRA as zero during context switch?
Maddy
I'll get rid of this hunk for now, I expect things won't be exactly clean
or consistent until the KVM host PMU code is moved into perf/ though.
Thanks,
Nick