[PATCH] selftests/powerpc: Fix L1D flushing tests for Power10

The rfi_flush and entry_flush selftests work by using the PM_LD_MISS_L1
perf event to count L1D misses.  The value of this event has changed
over time:

- Power7 uses 0x400f0
- Power8 and Power9 use both 0x400f0 and 0x3e054
- Power10 uses only 0x3e054

Update these selftests to use the value 0x3e054 on P10 and later,
fixing the tests from finding 0 events.

Signed-off-by: Russell Currey <redacted>
---
 tools/testing/selftests/powerpc/security/entry_flush.c | 4 +++-
 tools/testing/selftests/powerpc/security/flush_utils.c | 9 +++++++++
 tools/testing/selftests/powerpc/security/flush_utils.h | 9 ++++++++-
 tools/testing/selftests/powerpc/security/rfi_flush.c   | 4 +++-
 4 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/tools/testing/selftests/powerpc/security/entry_flush.c b/tools/testing/selftests/powerpc/security/entry_flush.c
index 78cf914fa321..ffcc93be7df1 100644
--- a/tools/testing/selftests/powerpc/security/entry_flush.c
+++ b/tools/testing/selftests/powerpc/security/entry_flush.c

@@ -26,6 +26,7 @@ int entry_flush_test(void)
 	__u64 l1d_misses_total = 0;
 	unsigned long iterations = 100000, zero_size = 24 * 1024;
 	unsigned long l1d_misses_expected;
+	unsigned long perf_l1d_miss_event;
 	int rfi_flush_orig;
 	int entry_flush, entry_flush_orig;
 

@@ -53,7 +54,8 @@ int entry_flush_test(void)
 
 	entry_flush = entry_flush_orig;
 
-	fd = perf_event_open_counter(PERF_TYPE_RAW, /* L1d miss */ 0x400f0, -1);
+	perf_l1d_miss_event = get_perf_l1d_miss_event();
+	fd = perf_event_open_counter(PERF_TYPE_RAW, perf_l1d_miss_event, -1);
 	FAIL_IF(fd < 0);
 
 	p = (char *)memalign(zero_size, CACHELINE_SIZE);

diff --git a/tools/testing/selftests/powerpc/security/flush_utils.c b/tools/testing/selftests/powerpc/security/flush_utils.c
index 0c3c4c40c7fb..7a5ef1a7a228 100644
--- a/tools/testing/selftests/powerpc/security/flush_utils.c
+++ b/tools/testing/selftests/powerpc/security/flush_utils.c

@@ -68,3 +68,12 @@ void set_dscr(unsigned long val)
 
 	asm volatile("mtspr %1,%0" : : "r" (val), "i" (SPRN_DSCR));
 }
+
+unsigned long get_perf_l1d_miss_event(void)
+{
+	bool is_p10_or_later = ((mfspr(SPRN_PVR) >>  16) & 0xFFFF) >= 0x80;
+
+	if (is_p10_or_later)
+		return PERF_L1D_MISS_P10;
+	return PERF_L1D_MISS_P7;
+}

diff --git a/tools/testing/selftests/powerpc/security/flush_utils.h b/tools/testing/selftests/powerpc/security/flush_utils.h
index 07a5eb301466..c60d15f3eb4b 100644
--- a/tools/testing/selftests/powerpc/security/flush_utils.h
+++ b/tools/testing/selftests/powerpc/security/flush_utils.h

@@ -7,11 +7,18 @@
 #ifndef _SELFTESTS_POWERPC_SECURITY_FLUSH_UTILS_H
 #define _SELFTESTS_POWERPC_SECURITY_FLUSH_UTILS_H
 
-#define CACHELINE_SIZE 128
+#define CACHELINE_SIZE		128
+
+#define SPRN_PVR		287
+
+#define PERF_L1D_MISS_P7	0x400f0
+#define PERF_L1D_MISS_P10	0x3e054
 
 void syscall_loop(char *p, unsigned long iterations,
 		  unsigned long zero_size);
 
 void set_dscr(unsigned long val);
 
+unsigned long get_perf_l1d_miss_event(void);
+
 #endif /* _SELFTESTS_POWERPC_SECURITY_FLUSH_UTILS_H */

diff --git a/tools/testing/selftests/powerpc/security/rfi_flush.c b/tools/testing/selftests/powerpc/security/rfi_flush.c
index 7565fd786640..edf67c91ef79 100644
--- a/tools/testing/selftests/powerpc/security/rfi_flush.c
+++ b/tools/testing/selftests/powerpc/security/rfi_flush.c

@@ -26,6 +26,7 @@ int rfi_flush_test(void)
 	__u64 l1d_misses_total = 0;
 	unsigned long iterations = 100000, zero_size = 24 * 1024;
 	unsigned long l1d_misses_expected;
+	unsigned long perf_l1d_miss_event;
 	int rfi_flush_orig, rfi_flush;
 	int have_entry_flush, entry_flush_orig;
 

@@ -54,7 +55,8 @@ int rfi_flush_test(void)
 
 	rfi_flush = rfi_flush_orig;
 
-	fd = perf_event_open_counter(PERF_TYPE_RAW, /* L1d miss */ 0x400f0, -1);
+	perf_l1d_miss_event = get_perf_l1d_miss_event();
+	fd = perf_event_open_counter(PERF_TYPE_RAW, perf_l1d_miss_event, -1);
 	FAIL_IF(fd < 0);
 
 	p = (char *)memalign(zero_size, CACHELINE_SIZE);

-- 
2.30.1

Russell Currey [off-list ref] writes:

The rfi_flush and entry_flush selftests work by using the PM_LD_MISS_L1
perf event to count L1D misses.  The value of this event has changed
over time:

- Power7 uses 0x400f0
- Power8 and Power9 use both 0x400f0 and 0x3e054
- Power10 uses only 0x3e054

Update these selftests to use the value 0x3e054 on P10 and later,
fixing the tests from finding 0 events.

I wonder if we can just use the cache events that the kernel knows
about.

ie, switch the type to PERF_TYPE_HW_CACHE and the event to
PERF_COUNT_HW_CACHE_MISSES.

That would end up using the same event on power7 and power8:

$ git grep PERF_COUNT_HW_CACHE_MISSES arch/powerpc/perf/power{7,8,9,10}*.c
arch/powerpc/perf/power7-pmu.c: [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1,
arch/powerpc/perf/power8-pmu.c: [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1,
arch/powerpc/perf/power9-pmu.c: [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1_FIN,
arch/powerpc/perf/power10-pmu.c:        [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_MISS_L1,
arch/powerpc/perf/power10-pmu.c:        [PERF_COUNT_HW_CACHE_MISSES] =                  PM_LD_DEMAND_MISS_L1_FIN,

On power9 and power10 it's using slightly different events. But I think
it should still work, because these tests just counts misses
with/without the various flushes enabled.

The distinction between loads that miss at execute vs finish shouldn't
matter, but you'd need to test.

The advantage would be we wouldn't then need to update the test again
for future CPUs.

cheers