# \[PATCH 1/5\] powerpc: Remove flush\_instruction\_cache for book3s/32 - Subsystems: LINUX FOR POWERPC (32-BIT AND 64-BIT), THE REST - Maintainers: Madhavan Srinivasan, Linus Torvalds - List: linuxppc-dev - 8 messages, 2 authors - Page: https://ratatoskr.run/linuxppc-dev/2020/08/6067607/t ## \[PATCH 1/5\] powerpc: Remove flush\_instruction\_cache for book3s/32 - From: Christophe Leroy \ - Date: 2020-08-13 10:12:27 - Message: https://ratatoskr.run/linuxppc-dev/2020/08/6067607.md ```text The only callers of flush_instruction_cache() are: arch/powerpc/kernel/swsusp_booke.S: bl flush_instruction_cache arch/powerpc/mm/nohash/40x.c: flush_instruction_cache(); arch/powerpc/mm/nohash/44x.c: flush_instruction_cache(); arch/powerpc/mm/nohash/fsl_booke.c: flush_instruction_cache(); arch/powerpc/platforms/44x/machine_check.c: flush_instruction_cache(); arch/powerpc/platforms/44x/machine_check.c: flush_instruction_cache(); This function is not used by book3s/32, drop it. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/misc_32.S | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index b24f866fef81..bd870743c06f 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -271,9 +271,8 @@ _ASM_NOKPROBE_SYMBOL(real_writeb) /* * Flush instruction cache. - * This is a no-op on the 601. */ -#ifndef CONFIG_PPC_8xx +#if !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC_BOOK3S_32) _GLOBAL(flush_instruction_cache) #if defined(CONFIG_4xx) lis r3, KERNELBASE@h @@ -290,18 +289,11 @@ _GLOBAL(flush_instruction_cache) mfspr r3,SPRN_L1CSR1 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR mtspr SPRN_L1CSR1,r3 -#elif defined(CONFIG_PPC_BOOK3S_601) - blr /* for 601, do nothing */ -#else - /* 603/604 processor - use invalidate-all bit in HID0 */ - mfspr r3,SPRN_HID0 - ori r3,r3,HID0_ICFI - mtspr SPRN_HID0,r3 #endif /* CONFIG_4xx */ isync blr EXPORT_SYMBOL(flush_instruction_cache) -#endif /* CONFIG_PPC_8xx */ +#endif /* CONFIG_PPC_8xx || CONFIG_PPC_BOOK3S_32 */ /* * Copy a whole page. We use the dcbz instruction on the destination -- 2.25.0 ``` ## \[PATCH 5/5\] powerpc: Rewrite 4xx flush\_cache\_instruction() in C - From: Christophe Leroy \ - Date: 2020-08-13 10:12:10 - Message: https://ratatoskr.run/linuxppc-dev/2020/08/6067603.md ```text Nothing prevent flush_cache_instruction() from behing writen in C. Do it to improve readability and maintainability. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/misc_32.S | 13 ------------- arch/powerpc/mm/nohash/4xx.c | 15 +++++++++++++++ arch/powerpc/mm/nohash/Makefile | 1 + 3 files changed, 16 insertions(+), 13 deletions(-) create mode 100644 arch/powerpc/mm/nohash/4xx.c diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index 4f4a31d9fdd0..87717966f5cd 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -268,19 +268,6 @@ _ASM_NOKPROBE_SYMBOL(real_writeb) #endif /* CONFIG_40x */ - -/* - * Flush instruction cache. - */ -#ifdef CONFIG_4xx -_GLOBAL(flush_instruction_cache) - lis r3, KERNELBASE@h - iccci 0,r3 - isync - blr -EXPORT_SYMBOL(flush_instruction_cache) -#endif - /* * Copy a whole page. We use the dcbz instruction on the destination * to reduce memory traffic (it eliminates the unnecessary reads of diff --git a/arch/powerpc/mm/nohash/4xx.c b/arch/powerpc/mm/nohash/4xx.c new file mode 100644 index 000000000000..954c8aa42a32 --- /dev/null +++ b/arch/powerpc/mm/nohash/4xx.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * This file contains the routines for initializing the MMU + * on the 4xx series of chips. + */ + +#include +#include +#include + +void flush_instruction_cache(void) +{ + iccci((void*)KERNELBASE); + isync(); +} diff --git a/arch/powerpc/mm/nohash/Makefile b/arch/powerpc/mm/nohash/Makefile index 0424f6ce5bd8..a7f7211b6373 100644 --- a/arch/powerpc/mm/nohash/Makefile +++ b/arch/powerpc/mm/nohash/Makefile @@ -4,6 +4,7 @@ ccflags-$(CONFIG_PPC64) := $(NO_MINIMAL_TOC) obj-y += mmu_context.o tlb.o tlb_low.o obj-$(CONFIG_PPC_BOOK3E_64) += tlb_low_64e.o book3e_pgtable.o +obj-$(CONFIG_4xx) += 4xx.o obj-$(CONFIG_40x) += 40x.o obj-$(CONFIG_44x) += 44x.o obj-$(CONFIG_PPC_8xx) += 8xx.o -- 2.25.0 ``` ## \[PATCH 4/5\] powerpc: Rewrite FSL\_BOOKE flush\_cache\_instruction() in C - From: Christophe Leroy \ - Date: 2020-08-13 10:12:17 - Message: https://ratatoskr.run/linuxppc-dev/2020/08/6067604.md ```text Nothing prevent flush_cache_instruction() from behing writen in C. Do it to improve readability and maintainability. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/misc_32.S | 17 ----------------- arch/powerpc/mm/nohash/fsl_booke.c | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 17 deletions(-) diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index a8f6ef513115..4f4a31d9fdd0 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -281,23 +281,6 @@ _GLOBAL(flush_instruction_cache) EXPORT_SYMBOL(flush_instruction_cache) #endif -#ifdef CONFIG_FSL_BOOKE -_GLOBAL(flush_instruction_cache) -#ifdef CONFIG_E200 - mfspr r3,SPRN_L1CSR0 - ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC - /* msync; isync recommended here */ - mtspr SPRN_L1CSR0,r3 -#else - mfspr r3,SPRN_L1CSR1 - ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR - mtspr SPRN_L1CSR1,r3 -#endif - isync - blr -EXPORT_SYMBOL(flush_instruction_cache) -#endif - /* * Copy a whole page. We use the dcbz instruction on the destination * to reduce memory traffic (it eliminates the unnecessary reads of diff --git a/arch/powerpc/mm/nohash/fsl_booke.c b/arch/powerpc/mm/nohash/fsl_booke.c index 0c294827d6e5..36bda962d3b3 100644 --- a/arch/powerpc/mm/nohash/fsl_booke.c +++ b/arch/powerpc/mm/nohash/fsl_booke.c @@ -219,6 +219,22 @@ unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top) return tlbcam_addrs[tlbcam_index - 1].limit - PAGE_OFFSET + 1; } +void flush_instruction_cache(void) +{ + unsigned long tmp; + + if (IS_ENABLED(CONFIG_E200)) { + tmp = mfspr(SPRN_L1CSR0); + tmp |= L1CSR0_CFI | L1CSR0_CLFC; + mtspr(SPRN_L1CSR0, tmp); + } else { + tmp = mfspr(SPRN_L1CSR1); + tmp |= L1CSR1_ICFI | L1CSR1_ICLFR; + mtspr(SPRN_L1CSR1, tmp); + } + isync(); +} + /* * MMU_init_hw does the chip-specific initialization of the MMU hardware. */ -- 2.25.0 ``` ## \[PATCH 3/5\] powerpc: Remove flush\_instruction\_cache() on 8xx - From: Christophe Leroy \ - Date: 2020-08-13 10:12:21 - Message: https://ratatoskr.run/linuxppc-dev/2020/08/6067605.md ```text flush_instruction_cache() is never used on 8xx, remove it. Signed-off-by: Christophe Leroy --- arch/powerpc/mm/nohash/8xx.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/arch/powerpc/mm/nohash/8xx.c b/arch/powerpc/mm/nohash/8xx.c index d2b37146ae6c..231ca95f9ffb 100644 --- a/arch/powerpc/mm/nohash/8xx.c +++ b/arch/powerpc/mm/nohash/8xx.c @@ -244,13 +244,6 @@ void set_context(unsigned long id, pgd_t *pgd) mb(); } -void flush_instruction_cache(void) -{ - isync(); - mtspr(SPRN_IC_CST, IDC_INVALL); - isync(); -} - #ifdef CONFIG_PPC_KUEP void __init setup_kuep(bool disabled) { -- 2.25.0 ``` ## \[PATCH 2/5\] powerpc: Untangle flush\_instruction\_cache() - From: Christophe Leroy \ - Date: 2020-08-13 10:12:23 - Message: https://ratatoskr.run/linuxppc-dev/2020/08/6067606.md ```text flush_instruction_cache() is a mixup of each PPC32 sub-arch. Untangle it by making one complete function for each sub-arch. This makes it a lot more readable and maintainable. Signed-off-by: Christophe Leroy --- arch/powerpc/kernel/misc_32.S | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S index bd870743c06f..a8f6ef513115 100644 --- a/arch/powerpc/kernel/misc_32.S +++ b/arch/powerpc/kernel/misc_32.S @@ -272,28 +272,31 @@ _ASM_NOKPROBE_SYMBOL(real_writeb) /* * Flush instruction cache. */ -#if !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC_BOOK3S_32) +#ifdef CONFIG_4xx _GLOBAL(flush_instruction_cache) -#if defined(CONFIG_4xx) lis r3, KERNELBASE@h iccci 0,r3 -#elif defined(CONFIG_FSL_BOOKE) + isync + blr +EXPORT_SYMBOL(flush_instruction_cache) +#endif + +#ifdef CONFIG_FSL_BOOKE +_GLOBAL(flush_instruction_cache) #ifdef CONFIG_E200 mfspr r3,SPRN_L1CSR0 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC /* msync; isync recommended here */ mtspr SPRN_L1CSR0,r3 - isync - blr -#endif +#else mfspr r3,SPRN_L1CSR1 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR mtspr SPRN_L1CSR1,r3 -#endif /* CONFIG_4xx */ +#endif isync blr EXPORT_SYMBOL(flush_instruction_cache) -#endif /* CONFIG_PPC_8xx || CONFIG_PPC_BOOK3S_32 */ +#endif /* * Copy a whole page. We use the dcbz instruction on the destination -- 2.25.0 ``` ## Re: \[PATCH 1/5\] powerpc: Remove flush\_instruction\_cache for book3s/32 - From: Christoph Hellwig \ - Date: 2020-08-13 12:13:38 - Message: https://ratatoskr.run/linuxppc-dev/2020/08/6067678.md ```text On Thu, Aug 13, 2020 at 10:12:00AM +0000, Christophe Leroy wrote: > -#ifndef CONFIG_PPC_8xx > +#if !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC_BOOK3S_32) > _GLOBAL(flush_instruction_cache) > #if defined(CONFIG_4xx) > lis r3, KERNELBASE@h > @@ -290,18 +289,11 @@ _GLOBAL(flush_instruction_cache) > mfspr r3,SPRN_L1CSR1 > ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR > mtspr SPRN_L1CSR1,r3 > -#elif defined(CONFIG_PPC_BOOK3S_601) > - blr /* for 601, do nothing */ > -#else > - /* 603/604 processor - use invalidate-all bit in HID0 */ > - mfspr r3,SPRN_HID0 > - ori r3,r3,HID0_ICFI > - mtspr SPRN_HID0,r3 > #endif /* CONFIG_4xx */ > isync > blr > EXPORT_SYMBOL(flush_instruction_cache) > -#endif /* CONFIG_PPC_8xx */ > +#endif /* CONFIG_PPC_8xx || CONFIG_PPC_BOOK3S_32 */ What about untangling this into entirely separate versions instead of the ifdef mess? Also the export does not seem to be needed at all. ``` ## Re: \[PATCH 1/5\] powerpc: Remove flush\_instruction\_cache for book3s/32 - From: Christoph Hellwig \ - Date: 2020-08-13 12:14:20 - Message: https://ratatoskr.run/linuxppc-dev/2020/08/6067679.md ```text On Thu, Aug 13, 2020 at 01:13:08PM +0100, Christoph Hellwig wrote: > On Thu, Aug 13, 2020 at 10:12:00AM +0000, Christophe Leroy wrote: > > -#ifndef CONFIG_PPC_8xx > > +#if !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC_BOOK3S_32) > > _GLOBAL(flush_instruction_cache) > > #if defined(CONFIG_4xx) > > lis r3, KERNELBASE@h > > @@ -290,18 +289,11 @@ _GLOBAL(flush_instruction_cache) > > mfspr r3,SPRN_L1CSR1 > > ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR > > mtspr SPRN_L1CSR1,r3 > > -#elif defined(CONFIG_PPC_BOOK3S_601) > > - blr /* for 601, do nothing */ > > -#else > > - /* 603/604 processor - use invalidate-all bit in HID0 */ > > - mfspr r3,SPRN_HID0 > > - ori r3,r3,HID0_ICFI > > - mtspr SPRN_HID0,r3 > > #endif /* CONFIG_4xx */ > > isync > > blr > > EXPORT_SYMBOL(flush_instruction_cache) > > -#endif /* CONFIG_PPC_8xx */ > > +#endif /* CONFIG_PPC_8xx || CONFIG_PPC_BOOK3S_32 */ > > What about untangling this into entirely separate versions instead > of the ifdef mess? Also the export does not seem to be needed at all. Ok, I see that you do that later, sorry. ``` ## Re: \[PATCH 1/5\] powerpc: Remove flush\_instruction\_cache for book3s/32 - From: Christophe Leroy \ - Date: 2020-08-14 05:52:17 - Message: https://ratatoskr.run/linuxppc-dev/2020/08/6068238.md ```text Le 13/08/2020 à 14:14, Christoph Hellwig a écrit : > On Thu, Aug 13, 2020 at 01:13:08PM +0100, Christoph Hellwig wrote: >> On Thu, Aug 13, 2020 at 10:12:00AM +0000, Christophe Leroy wrote: >>> -#ifndef CONFIG_PPC_8xx >>> +#if !defined(CONFIG_PPC_8xx) && !defined(CONFIG_PPC_BOOK3S_32) >>> _GLOBAL(flush_instruction_cache) >>> #if defined(CONFIG_4xx) >>> lis r3, KERNELBASE@h >>> @@ -290,18 +289,11 @@ _GLOBAL(flush_instruction_cache) >>> mfspr r3,SPRN_L1CSR1 >>> ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR >>> mtspr SPRN_L1CSR1,r3 >>> -#elif defined(CONFIG_PPC_BOOK3S_601) >>> - blr /* for 601, do nothing */ >>> -#else >>> - /* 603/604 processor - use invalidate-all bit in HID0 */ >>> - mfspr r3,SPRN_HID0 >>> - ori r3,r3,HID0_ICFI >>> - mtspr SPRN_HID0,r3 >>> #endif /* CONFIG_4xx */ >>> isync >>> blr >>> EXPORT_SYMBOL(flush_instruction_cache) >>> -#endif /* CONFIG_PPC_8xx */ >>> +#endif /* CONFIG_PPC_8xx || CONFIG_PPC_BOOK3S_32 */ >> >> What about untangling this into entirely separate versions instead >> of the ifdef mess? Also the export does not seem to be needed at all. > > Ok, I see that you do that later, sorry. > In v2, I drop the untangling patch, because the series completely dismantles flush_instruction_cache() so there is no need for an ephemeral untanggled version of it. Christophe ```