The current ASRC driver hardcodes the input and output clocks used for
sample rate conversions. In order to allow greater flexibility and to
cover more use cases, it would be preferable to select the clocks using
device-tree properties.
This series also fix register configuration and clock assignment so
conversion can be conducted effectively in both directions with a good
quality.
Arnaud Ferraris (4):
dt-bindings: sound: fsl,asrc: add properties to select in/out clocks
ASoC: fsl_asrc: allow using arbitrary input and output clocks
ASoC: fsl_asrc: always use ratio for conversion
ASoC: fsl_asrc: swap input and output clocks in capture mode
Documentation/devicetree/bindings/sound/fsl,asrc.txt | 8 ++++++++
sound/soc/fsl/fsl_asrc.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-----
sound/soc/fsl/fsl_asrc_common.h | 3 +++
3 files changed, 75 insertions(+), 5 deletions(-)
The ASRC peripheral accepts a wide range of input and output clocks, but
no mechanism exists at the moment to define those as they are currently
hardcoded in the driver.
This commit adds new properties allowing selection of arbitrary input
and output clocks.
Signed-off-by: Arnaud Ferraris <redacted>
---
Documentation/devicetree/bindings/sound/fsl,asrc.txt | 8 ++++++++
1 file changed, 8 insertions(+)
@@ -55,6 +55,12 @@ Optional properties: Ends, which can replace the fsl,asrc-width. The value is 2 (S16_LE), or 6 (S24_LE).+ - fsl,asrc-input-clock : Input clock ID, defaults to INCLK_NONE+ (see enum asrc_inclk in fsl_asrc.h)++ - fsl,asrc-output-clock : Output clock ID, defaults to OUTCLK_ASRCK1_CLK+ (see enum asrc_outclk in fsl_asrc.h)+ Example: asrc: asrc@2034000 {
fsl_asrc currently uses hardcoded input and output clocks, preventing
its use for anything other than S/PDIF output.
This patch adds the ability to select any clock as input or output (by
using new DT properties), making it possible to use this peripheral in a
more advanced way.
Signed-off-by: Arnaud Ferraris <redacted>
---
sound/soc/fsl/fsl_asrc.c | 18 ++++++++++++++++--
sound/soc/fsl/fsl_asrc_common.h | 3 +++
2 files changed, 19 insertions(+), 2 deletions(-)
Even when not in "Ideal Ratio" mode, ASRC can use an internally measured
ratio, which greatly improves the conversion quality.
This patch ensures we always use at least the internal ratio.
Signed-off-by: Arnaud Ferraris <redacted>
---
sound/soc/fsl/fsl_asrc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
@@ -451,7 +451,7 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate)regmap_update_bits(asrc->regmap,REG_ASRCTR,ASRCTR_ATSi_MASK(index),ASRCTR_ATS(index));regmap_update_bits(asrc->regmap,REG_ASRCTR,-ASRCTR_USRi_MASK(index),0);+ASRCTR_USRi_MASK(index),ASRCTR_USR(index));/* Set the input and output clock sources */regmap_update_bits(asrc->regmap,REG_ASRCSR,
@@ -493,8 +493,7 @@ static int fsl_asrc_config_pair(struct fsl_asrc_pair *pair, bool use_ideal_rate)/* Enable Ideal Ratio mode */regmap_update_bits(asrc->regmap,REG_ASRCTR,-ASRCTR_IDRi_MASK(index)|ASRCTR_USRi_MASK(index),-ASRCTR_IDR(index)|ASRCTR_USR(index));+ASRCTR_IDRi_MASK(index),ASRCTR_IDR(index));fsl_asrc_sel_proc(inrate,outrate,&pre_proc,&post_proc);
The input clock is the reference clock we need to convert the stream to,
which therefore has to be the clock of the origin stream/device.
When the stream is bi-directional and we want ASRC to act on both
directions, we need to swap the input and output clocks between the
playback and capture streams.
As some of the clocks have different ID's depending on whether they are
used as input or output, this requires adding a new function to find the
output clock ID corresponding to a given input clock.
Signed-off-by: Arnaud Ferraris <redacted>
---
sound/soc/fsl/fsl_asrc.c | 50 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 48 insertions(+), 2 deletions(-)
Hi Arnaud,
On Thu, Jul 02, 2020 at 04:22:31PM +0200, Arnaud Ferraris wrote:
The current ASRC driver hardcodes the input and output clocks used for
sample rate conversions. In order to allow greater flexibility and to
cover more use cases, it would be preferable to select the clocks using
device-tree properties.
Hi Nic,
Le 02/07/2020 à 20:42, Nicolin Chen a écrit :
Hi Arnaud,
On Thu, Jul 02, 2020 at 04:22:31PM +0200, Arnaud Ferraris wrote:
quoted
The current ASRC driver hardcodes the input and output clocks used for
sample rate conversions. In order to allow greater flexibility and to
cover more use cases, it would be preferable to select the clocks using
device-tree properties.
Hi Nic,
Le 02/07/2020 à 20:42, Nicolin Chen a écrit :
Hi Arnaud,
On Thu, Jul 02, 2020 at 04:22:31PM +0200, Arnaud Ferraris wrote:
quoted
The current ASRC driver hardcodes the input and output clocks used for
sample rate conversions. In order to allow greater flexibility and to
cover more use cases, it would be preferable to select the clocks using
device-tree properties.
While working on fixing the automatic clock selection (see my v3), I
came across another potential issue, which would be better explained
with an example:
- Input has sample rate 8kHz and uses clock SSI1 with rate 512kHz
- Output has sample rate 16kHz and uses clock SSI2 with rate 1024kHz
Let's say my v3 patch is merged, then the selected input clock will be
SSI1, while the selected output clock will be SSI2. In that case, it's
all good, as the driver will calculate the dividers right.
Now, suppose a similar board has the input wired to SSI2 and output to
SSI1, meaning we're now in the following case:
- Input has sample rate 8kHz and uses clock SSI2 with rate 512kHz
- Output has sample rate 16kHz and uses clock SSI1 with rate 1024kHz
(the same result is achieved during capture with the initial example
setup, as input and output properties are then swapped)
In that case, the selected clocks will still be SSI1 for input (just
because it appears first in the clock table), and SSI2 for output,
meaning the calculated dividers will be:
- input: 512 / 16 => 32 (should be 64)
- output: 1024 / 8 => 128 (should be 64 here too)
---
I can't see how the clock selection algorithm could be made smart enough
to cover cases such as this one, as it would need to be aware of the
exact relationship between the sample rate and the clock rate (my
example demonstrates a case where the "sample rate to clock rate"
multiplier is identical for both input and output, but this can't be
assumed to be always the case).
Therefore, I still believe being able to force clock selection using
optional DT properties would make sense, while still using the
auto-selection by default.
Regards,
Arnaud
Having a quick review at your changes, I think the DT part may
not be necessary as it's more likely a software configuration.
I personally like the new auto-selecting solution more.
quoted
This series also fix register configuration and clock assignment so
conversion can be conducted effectively in both directions with a good
quality.
If there's any further change that you feel you can improve on
the top of mentioned change after rebasing, I'd like to review.
Thanks
Nic
On Fri, Jul 17, 2020 at 01:16:42PM +0200, Arnaud Ferraris wrote:
Hi Nic,
Le 02/07/2020 à 20:42, Nicolin Chen a écrit :
quoted
Hi Arnaud,
On Thu, Jul 02, 2020 at 04:22:31PM +0200, Arnaud Ferraris wrote:
quoted
The current ASRC driver hardcodes the input and output clocks used for
sample rate conversions. In order to allow greater flexibility and to
cover more use cases, it would be preferable to select the clocks using
device-tree properties.
While working on fixing the automatic clock selection (see my v3), I
came across another potential issue, which would be better explained
with an example:
- Input has sample rate 8kHz and uses clock SSI1 with rate 512kHz
- Output has sample rate 16kHz and uses clock SSI2 with rate 1024kHz
Let's say my v3 patch is merged, then the selected input clock will be
SSI1, while the selected output clock will be SSI2. In that case, it's
all good, as the driver will calculate the dividers right.
Now, suppose a similar board has the input wired to SSI2 and output to
SSI1, meaning we're now in the following case:
- Input has sample rate 8kHz and uses clock SSI2 with rate 512kHz
- Output has sample rate 16kHz and uses clock SSI1 with rate 1024kHz
(the same result is achieved during capture with the initial example
setup, as input and output properties are then swapped)
In that case, the selected clocks will still be SSI1 for input (just
because it appears first in the clock table), and SSI2 for output,
meaning the calculated dividers will be:
- input: 512 / 16 => 32 (should be 64)
- output: 1024 / 8 => 128 (should be 64 here too)
I don't get the 32, 128 and 64 parts. Would you please to elaborate
a bit? What you said sounds to me like the driver calculates wrong
dividers?