# \[PATCH\] powerpc/mm: Remove very old comment in hash-4k.h - From: Michael Ellerman \ - Date: 2018-11-27 08:20:43 - List: linuxppc-dev - Page: https://ratatoskr.run/linuxppc-dev/2018/11/9507373 - Thread: https://ratatoskr.run/linuxppc-dev/2018/11/9507373/t.md ```text This comment talks about PTEs being 64-bits and PMD/PGD being 32-bits, but that hasn't been true since 2005 when David Gibson implemented 4-level page tables in the commit titled "Four level pagetables for ppc64". Remove it. Signed-off-by: Michael Ellerman --- See: https://github.com/mpe/linux-fullhistory/commit/e28f7faf05159f1cfd564596f5e6178edba6bd49#diff-0adfdefb64f0f0ef306be06ce7f953ebL128 --- arch/powerpc/include/asm/book3s/64/hash-4k.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h index 15bc16b1dc9c..cf5ba5254299 100644 --- a/arch/powerpc/include/asm/book3s/64/hash-4k.h +++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h @@ -1,11 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ #ifndef _ASM_POWERPC_BOOK3S_64_HASH_4K_H #define _ASM_POWERPC_BOOK3S_64_HASH_4K_H -/* - * Entries per page directory level. The PTE level must use a 64b record - * for each page table entry. The PMD and PGD level use a 32b record for - * each entry by assuming that each entry is page aligned. - */ + #define H_PTE_INDEX_SIZE 9 #define H_PMD_INDEX_SIZE 7 #define H_PUD_INDEX_SIZE 9 -- 2.17.2 ```