[PATCH 7/7] powerpc/powernv/pci: Don't use the lower 4G TCEs in
From: Timothy Pearson <tpearson@raptorengineering.com>
Date: 2018-06-24 00:03:28
pseudo-DMA mode Four TCEs are reserved for legacy 32-bit DMA mappings in psuedo DMA mode. Mark these with an invalid address to avoid their use by the TCE cache mapper. Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> --- arch/powerpc/platforms/powernv/pci-ioda.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c b/arch/powerpc/platforms/powernv/pci-ioda.c
index a6097dd323f8..e8a1333f6b3e 100644
--- a/arch/powerpc/platforms/powernv/pci-ioda.c
+++ b/arch/powerpc/platforms/powernv/pci-ioda.c@@ -1783,7 +1783,7 @@ static bool pnv_pci_ioda_pe_single_vendor(struct pnv_ioda_pe *pe) static int pnv_pci_pseudo_bypass_setup(struct pnv_ioda_pe *pe) { - u64 tce_count, table_size, window_size; + u64 i, tce_count, table_size, window_size; struct pnv_phb *p = pe->phb; struct page *table_pages; __be64 *tces;
@@ -1835,6 +1835,12 @@ static int pnv_pci_pseudo_bypass_setup(struct pnv_ioda_pe *pe) /* mark the first 4GB as reserved so this can still be used for 32bit */ bitmap_set(pe->tce_bitmap, 0, 1ULL << (32 - p->ioda.max_tce_order)); + /* make sure reserved first 4GB TCEs are not used by the mapper + * set each address to -1, which will never match an incoming request + */ + for (i = 0; i < 4; i++) + pe->tce_tracker[i * 2] = -1; + pe_info(pe, "pseudo-bypass sizes: tracker %d bitmap %d TCEs %lld\n", tracker_entries, bitmap_size, tce_count);
--
2.17.1