From: Haren Myneni <hidden> Date: 2018-05-31 09:16:15
NX can set 3rd bit in CR register for XER[SO] (Summation overflow)
which is not related to paste request. The current paste function
returns failure for the successful request when this bit is set.
So mask this bit and check the proper return status.
Fixes: 2392c8c8c045 ("powerpc/powernv/vas: Define copy/paste interfaces")
Cc: stable@vger.kernel.org # v4.14+
Signed-off-by: Haren Myneni <haren@us.ibm.com>
@@ -9,7 +9,8 @@#include<asm/ppc-opcode.h>#define CR0_SHIFT 28-#define CR0_MASK 0xF+#define CR0_MASK 0xE /* 3rd bit undefined or set for XER[SO] */+/**Copy/pasteinstructions:*
From: Michael Ellerman <mpe@ellerman.id.au> Date: 2018-06-03 10:48:18
Hi Haren,
Haren Myneni [off-list ref] writes:
quoted hunk
NX can set 3rd bit in CR register for XER[SO] (Summation overflow)
which is not related to paste request. The current paste function
returns failure for the successful request when this bit is set.
So mask this bit and check the proper return status.
Fixes: 2392c8c8c045 ("powerpc/powernv/vas: Define copy/paste interfaces")
Cc: stable@vger.kernel.org # v4.14+
Signed-off-by: Haren Myneni <haren@us.ibm.com>
@@ -9,7 +9,8 @@#include<asm/ppc-opcode.h>#define CR0_SHIFT 28-#define CR0_MASK 0xF+#define CR0_MASK 0xE /* 3rd bit undefined or set for XER[SO] */+/**Copy/pasteinstructions:*
Unfortunately this no longer applies to my next branch, because those
macros have been moved out of this header as part of an unrelated patch.
The following patch should work instead, can you please confirm by
testing it?
@@ -41,5 +41,7 @@ static inline int vas_paste(void *paste_address, int offset):"b"(offset),"b"(paste_address):"memory","cr0");-return(cr>>CR0_SHIFT)&CR0_MASK;++/* We mask with 0xE to ignore SO */+return(cr>>CR0_SHIFT)&0xE;}
From: Haren Myneni <hidden> Date: 2018-06-04 02:16:08
On 06/03/2018 03:48 AM, Michael Ellerman wrote:
quoted hunk
Hi Haren,
Haren Myneni [off-list ref] writes:
quoted
NX can set 3rd bit in CR register for XER[SO] (Summation overflow)
which is not related to paste request. The current paste function
returns failure for the successful request when this bit is set.
So mask this bit and check the proper return status.
Fixes: 2392c8c8c045 ("powerpc/powernv/vas: Define copy/paste interfaces")
Cc: stable@vger.kernel.org # v4.14+
Signed-off-by: Haren Myneni <haren@us.ibm.com>
@@ -9,7 +9,8 @@#include<asm/ppc-opcode.h>#define CR0_SHIFT 28-#define CR0_MASK 0xF+#define CR0_MASK 0xE /* 3rd bit undefined or set for XER[SO] */+/**Copy/pasteinstructions:*
Unfortunately this no longer applies to my next branch, because those
macros have been moved out of this header as part of an unrelated patch.
The following patch should work instead, can you please confirm by
testing it?
@@ -41,5 +41,7 @@ static inline int vas_paste(void *paste_address, int offset):"b"(offset),"b"(paste_address):"memory","cr0");-return(cr>>CR0_SHIFT)&CR0_MASK;++/* We mask with 0xE to ignore SO */+return(cr>>CR0_SHIFT)&0xE;}
From: Michael Ellerman <mpe@ellerman.id.au> Date: 2018-06-04 09:11:28
Haren Myneni [off-list ref] writes:
On 06/03/2018 03:48 AM, Michael Ellerman wrote:
quoted
Haren Myneni [off-list ref] writes:
quoted
NX can set 3rd bit in CR register for XER[SO] (Summation overflow)
which is not related to paste request. The current paste function
returns failure for the successful request when this bit is set.
So mask this bit and check the proper return status.
Fixes: 2392c8c8c045 ("powerpc/powernv/vas: Define copy/paste interfaces")
Cc: stable@vger.kernel.org # v4.14+
Signed-off-by: Haren Myneni <haren@us.ibm.com>
@@ -9,7 +9,8 @@#include<asm/ppc-opcode.h>#define CR0_SHIFT 28-#define CR0_MASK 0xF+#define CR0_MASK 0xE /* 3rd bit undefined or set for XER[SO] */+/**Copy/pasteinstructions:*
Unfortunately this no longer applies to my next branch, because those
macros have been moved out of this header as part of an unrelated patch.
The following patch should work instead, can you please confirm by
testing it?
@@ -41,5 +41,7 @@ static inline int vas_paste(void *paste_address, int offset):"b"(offset),"b"(paste_address):"memory","cr0");-return(cr>>CR0_SHIFT)&CR0_MASK;++/* We mask with 0xE to ignore SO */+return(cr>>CR0_SHIFT)&0xE;}
Tested with this patch and it works.
Thanks. I sent a new version to the list and will apply that.
cheers