[PATCH] cxl: Enable NORST bit in PSL_DEBUG register for PSL9

Subsystems: char and misc drivers, the rest

STALE3068d

5 messages, 5 authors, 2018-03-14 · open the first message on its own page

[PATCH] cxl: Enable NORST bit in PSL_DEBUG register for PSL9

From: Vaibhav Jain <hidden>
Date: 2018-02-09 04:09:51

We enable the NORST bit by default for debug afu images to prevent
reset of AFU trace-data on a PCI link drop. For production AFU images
this bit is always ignored and PSL gets reconfigured anyways thereby
resetting the trace data. So setting this bit for non-debug images
doesn't have any impact.

Signed-off-by: Vaibhav Jain <redacted>
---
 drivers/misc/cxl/pci.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 758842f65a1b..c983f23cc2ed 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -503,8 +503,12 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
 	if (cxl_is_power9_dd1()) {
 		/* Disabling deadlock counter CAR */
 		cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL);
-	} else
-		cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x4000000000000000ULL);
+		/* Enable NORST */
+		cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);
+	} else {
+		/* Enable NORST and DD2 features */
+		cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
+	}
 
 	return 0;
 }
-- 
2.14.3

Re: [PATCH] cxl: Enable NORST bit in PSL_DEBUG register for PSL9

From: christophe lombard <hidden>
Date: 2018-02-09 08:26:08

Le 09/02/2018 à 05:09, Vaibhav Jain a écrit :
quoted hunk
We enable the NORST bit by default for debug afu images to prevent
reset of AFU trace-data on a PCI link drop. For production AFU images
this bit is always ignored and PSL gets reconfigured anyways thereby
resetting the trace data. So setting this bit for non-debug images
doesn't have any impact.

Signed-off-by: Vaibhav Jain <redacted>
---
  drivers/misc/cxl/pci.c | 8 ++++++--
  1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 758842f65a1b..c983f23cc2ed 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -503,8 +503,12 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
  	if (cxl_is_power9_dd1()) {
  		/* Disabling deadlock counter CAR */
  		cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL);
-	} else
-		cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x4000000000000000ULL);
+		/* Enable NORST */
+		cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);
+	} else {
+		/* Enable NORST and DD2 features */
+		cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
+	}

  	return 0;
  }
Reviewed-by: Christophe Lombard <redacted>

Re: [PATCH] cxl: Enable NORST bit in PSL_DEBUG register for PSL9

From: Frederic Barrat <hidden>
Date: 2018-02-09 14:56:26


Le 09/02/2018 à 05:09, Vaibhav Jain a écrit :
We enable the NORST bit by default for debug afu images to prevent
reset of AFU trace-data on a PCI link drop. For production AFU images
this bit is always ignored and PSL gets reconfigured anyways thereby
resetting the trace data. So setting this bit for non-debug images
doesn't have any impact.

Signed-off-by: Vaibhav Jain <redacted>
---
Acked-by: Frederic Barrat <redacted>

btw, we should start removing dd1 code, it's not like anybody is going 
to try that now.

   Fred
quoted hunk
  drivers/misc/cxl/pci.c | 8 ++++++--
  1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 758842f65a1b..c983f23cc2ed 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -503,8 +503,12 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
  	if (cxl_is_power9_dd1()) {
  		/* Disabling deadlock counter CAR */
  		cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL);
-	} else
-		cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x4000000000000000ULL);
+		/* Enable NORST */
+		cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);
+	} else {
+		/* Enable NORST and DD2 features */
+		cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0xC000000000000000ULL);
+	}

  	return 0;
  }

Re: [PATCH] cxl: Enable NORST bit in PSL_DEBUG register for PSL9

From: Andrew Donnellan <hidden>
Date: 2018-02-13 02:55:25

On 09/02/18 15:09, Vaibhav Jain wrote:
We enable the NORST bit by default for debug afu images to prevent
reset of AFU trace-data on a PCI link drop. For production AFU images
this bit is always ignored and PSL gets reconfigured anyways thereby
resetting the trace data. So setting this bit for non-debug images
doesn't have any impact.

Signed-off-by: Vaibhav Jain <redacted>
Acked-by: Andrew Donnellan <redacted>

-- 
Andrew Donnellan              OzLabs, ADL Canberra
andrew.donnellan@au1.ibm.com  IBM Australia Limited

Re: cxl: Enable NORST bit in PSL_DEBUG register for PSL9

From: Michael Ellerman <hidden>
Date: 2018-03-14 09:27:45

On Fri, 2018-02-09 at 04:09:16 UTC, Vaibhav Jain wrote:
We enable the NORST bit by default for debug afu images to prevent
reset of AFU trace-data on a PCI link drop. For production AFU images
this bit is always ignored and PSL gets reconfigured anyways thereby
resetting the trace data. So setting this bit for non-debug images
doesn't have any impact.

Signed-off-by: Vaibhav Jain <redacted>
Reviewed-by: Christophe Lombard <redacted>
Acked-by: Frederic Barrat <redacted>
Acked-by: Andrew Donnellan <redacted>
Applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/03ebb419b896e0fb2da3f34b57d45e

cheers
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