[PATCH v2 3/4] 44x/fsp2: tvsense workaround for dd1
From: Ivan Mikhaylov <hidden>
Date: 2017-12-01 15:59:11
Also in:
lkml
Subsystem:
linux for powerpc (32-bit and 64-bit), linux for powerpc embedded ppc4xx, the rest · Maintainers:
Madhavan Srinivasan, Linus Torvalds
TVSENSE(temperature and voltage sensors) reset is blocked (clock gated) by the POR default of the TVS sleep config bit. As a consequence, TVSENSE will provide erratic sensor values, which may result in spurious (parity) errors recorded in the CMU FIR and leading to erroneous interrupt requests once the CMU interrupt is unmasked. Purpose of this to set up CMU in working state in any cases even in case of parity errors. Reviewed-by: Alistair Popple <redacted> Signed-off-by: Ivan Mikhaylov <redacted> --- arch/powerpc/platforms/44x/fsp2.c | 17 +++++++++++++++++ 1 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/platforms/44x/fsp2.c b/arch/powerpc/platforms/44x/fsp2.c
index baed409..7c9bc93 100644
--- a/arch/powerpc/platforms/44x/fsp2.c
+++ b/arch/powerpc/platforms/44x/fsp2.c@@ -59,6 +59,23 @@ static int __init fsp2_probe(void) mtdcr(DCRN_PLB6_HD, 0xffff0000); mtdcr(DCRN_PLB6_SHD, 0xffff0000); + /* TVSENSE reset is blocked (clock gated) by the POR default of the TVS + * sleep config bit. As a consequence, TVSENSE will provide erratic + * sensor values, which may result in spurious (parity) errors + * recorded in the CMU FIR and leading to erroneous interrupt requests + * once the CMU interrupt is unmasked. + */ + + /* 1. set TVS1[UNDOZE] */ + val = mfcmu(CMUN_TVS1); + val |= 0x4; + mtcmu(CMUN_TVS1, val); + + /* 2. clear FIR[TVS] and FIR[TVSPAR] */ + val = mfcmu(CMUN_FIR0); + val |= 0x30000000; + mtcmu(CMUN_FIR0, val); + /* L2 machine checks */ mtl2(L2PLBMCKEN0, 0xffffffff); mtl2(L2PLBMCKEN1, 0x0000ffff);
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1.7.1