[PATCH] powerpc: Fix handling of alignment interrupt on dcbz instruction

This fixes the emulation of the dcbz instruction in the alignment
interrupt handler.  The error was that we were comparing just the
instruction type field of op.type rather than the whole thing,
and therefore the comparison "type != CACHEOP + DCBZ" was always
true.

Fixes: 31bfdb036f12 ("powerpc: Use instruction emulation infrastructure to handle alignment faults")
Signed-off-by: Paul Mackerras <redacted>
---
 arch/powerpc/kernel/align.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
index 26b9994d27ee..43ef25156480 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel/align.c

@@ -341,7 +341,7 @@ int fix_alignment(struct pt_regs *regs)
 
 	type = op.type & INSTR_TYPE_MASK;
 	if (!OP_IS_LOAD_STORE(type)) {
-		if (type != CACHEOP + DCBZ)
+		if (op.type != CACHEOP + DCBZ)
 			return -EINVAL;
 		PPC_WARN_ALIGNMENT(dcbz, regs);
 		r = emulate_dcbz(op.ea, regs);

-- 
2.11.0

Michal, Christian, can you please confirm this fixes the problems you were seeing.

cheers

On 13 September 2017 2:51:24 pm AEST, Paul Mackerras [off-list ref] wrote:

-- 
Sent from my Android phone with K-9 Mail. Please excuse my brevity.

On Wed, Sep 13 2017, Michael Ellerman wrote:

Michal, Christian, can you please confirm this fixes the problems you
were seeing.

Yes, it fixes my problem. Thanks.

-Michal

On 13 September 2017 at 09:15AM, Michal Sojka wrote:

On Wed, Sep 13 2017, Michael Ellerman wrote:

quoted

Michal, Christian, can you please confirm this fixes the problems you
were seeing.

Yes, it fixes my problem. Thanks.

-Michal

It also fixes my problem. Many thanks!

-- Christian