From: Oliver O'Halloran <oohall@gmail.com> Date: 2017-07-06 08:46:56
The workaround for the CELL timebase bug does not correctly mark cr0 as
being clobbered. This can result in GCC making some poor^W completely
broken optimisations.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
---
arch/powerpc/include/asm/reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
From: Michael Ellerman <mpe@ellerman.id.au> Date: 2017-07-10 11:50:07
Oliver O'Halloran [off-list ref] writes:
The workaround for the CELL timebase bug does not correctly mark cr0 as
being clobbered. This can result in GCC making some poor^W completely
broken optimisations.
Fruit 'n oats, how did we never notice that? Luck I guess. Or subtle
breakage that no one could pin down :E
I'll tag it for stable.
Your change log is not entirely fair, it's not GCC's fault, we changed
register state without telling it, so it's on us :) I'll reword it a
bit here.
cheers
Hi!
On Mon, Jul 10, 2017 at 09:50:06PM +1000, Michael Ellerman wrote:
Oliver O'Halloran [off-list ref] writes:
quoted
The workaround for the CELL timebase bug does not correctly mark cr0 as
being clobbered. This can result in GCC making some poor^W completely
broken optimisations.
Fruit 'n oats, how did we never notice that? Luck I guess. Or subtle
breakage that no one could pin down :E
GCC does not use cr0 before it has used cr7, cr5, cr6, cr1 (unless some
instruction _requires_ cr0, like record form ("dot") instructions, which
until recently were disabled when targetting Cell), so it isn't too easy
to hit the problem here. Maybe Oliver used a very new GCC? Or he was
unlucky.
I'll tag it for stable.
Your change log is not entirely fair, it's not GCC's fault, we changed
register state without telling it, so it's on us :) I'll reword it a
bit here.
Yep, GCC works fine here, GIGO etc. It isn't feasible to make GCC warn
for most inline asm problems, either (we do not parse the mnemonics in
the asm; this is a fundamental part of the design; you must express all
constraints as, well, constraints).
Segher
From: Michael Ellerman <mpe@ellerman.id.au> Date: 2017-07-11 02:33:45
Segher Boessenkool [off-list ref] writes:
Hi!
On Mon, Jul 10, 2017 at 09:50:06PM +1000, Michael Ellerman wrote:
quoted
Oliver O'Halloran [off-list ref] writes:
quoted
The workaround for the CELL timebase bug does not correctly mark cr0 as
being clobbered. This can result in GCC making some poor^W completely
broken optimisations.
Fruit 'n oats, how did we never notice that? Luck I guess. Or subtle
breakage that no one could pin down :E
GCC does not use cr0 before it has used cr7, cr5, cr6, cr1 (unless some
instruction _requires_ cr0, like record form ("dot") instructions, which
until recently were disabled when targetting Cell), so it isn't too easy
to hit the problem here. Maybe Oliver used a very new GCC? Or he was
unlucky.
Aha. I think he actually hit the bug elsewhere and then noticed it here
also? And yeah I think it was a dot instruction that triggered it.
quoted
I'll tag it for stable.
Your change log is not entirely fair, it's not GCC's fault, we changed
register state without telling it, so it's on us :) I'll reword it a
bit here.
Yep, GCC works fine here, GIGO etc. It isn't feasible to make GCC warn
for most inline asm problems, either (we do not parse the mnemonics in
the asm; this is a fundamental part of the design; you must express all
constraints as, well, constraints).
Ack. It's a terrible terrible interface, but that's the price we pay for
wanting to insert arbitrary bits of asm inside an otherwise compiled
language :)
When I get the time I might go through our inline asm and convert all
the cmpwi x,z to cmpwi cr0,x,z, so at least the cr0 usage is a little
more obvious.
cheers
From: Oliver <oohall@gmail.com> Date: 2017-07-11 04:02:54
On Mon, Jul 10, 2017 at 9:50 PM, Michael Ellerman [off-list ref] wrote:
Oliver O'Halloran [off-list ref] writes:
quoted
The workaround for the CELL timebase bug does not correctly mark cr0 as
being clobbered. This can result in GCC making some poor^W completely
broken optimisations.
Fruit 'n oats, how did we never notice that? Luck I guess. Or subtle
breakage that no one could pin down :E
Dumb luck probably. The workaround is inside a feature section which
depends on CPU_FTR_CELL_TB_BUG so you would only ever see a problem
when actually running on Cell (can't be that many people...). CR0
being volatile across function calls probably helped mask it too.
I'll tag it for stable.
Good idea.
Your change log is not entirely fair, it's not GCC's fault, we changed
register state without telling it, so it's on us :) I'll reword it a
bit here.
From: Michael Ellerman <hidden> Date: 2017-07-11 12:48:26
On Thu, 2017-07-06 at 08:46:43 UTC, Oliver O'Halloran wrote:
The workaround for the CELL timebase bug does not correctly mark cr0 as
being clobbered. This can result in GCC making some poor^W completely
broken optimisations.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>