On Fri, 2017-07-21 at 02:34PM, Michael Ellerman [off-list ref] wrote:

-----Original Message-----
From: Michael Ellerman [mailto:mpe@ellerman.id.au]
Sent: Friday, July 21, 2017 2:34 PM
To: Qiang Zhao <qiang.zhao@nxp.com>; oss@buserror.net
Cc: valentin.longchamp@keymile.com; linuxppc-dev@lists.ozlabs.org; linux-
kernel@vger.kernel.org; Qiang Zhao [off-list ref]
Subject: Re: [PATCH] qe: fix compile issue for arm64
=20
Zhao Qiang [off-list ref] writes:
=20

quoted

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
---
 drivers/soc/fsl/qe/qe.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c index

2ef6fc6..d48fa4a 100644

--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c

@@ -229,7 +229,9 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate,

unsigned int multiplier)

quoted

 	/* Errata QE_General4, which affects some MPC832x and MPC836x

SOCs, says

quoted

 	   that the BRG divisor must be even if you're not using divide-by-16
 	   mode. */
+#ifdef CONFIG_PPC
 	if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x)
+#endif
 		if (!div16 && (divisor & 1) && (divisor > 3))
 			divisor++;

=20
Are you sure that's what you want to do on arm64 ?

Is there any problem?

Best Regards
Qiang Zhao