Re: [PATCH 5/5] powerpc/smp: Add Power9 scheduler topology
From: Michael Ellerman <mpe@ellerman.id.au>
Date: 2017-03-15 11:33:41
From: Michael Ellerman <mpe@ellerman.id.au>
Date: 2017-03-15 11:33:41
Balbir Singh [off-list ref] writes:
On 02/03/17 11:49, Oliver O'Halloran wrote:quoted
In previous generations of Power processors each core had a private L2 cache. The Power9 processor has a slightly different architecture where the L2 cache is shared among pairs of cores rather than being completely private. Making the scheduler aware of this cache sharing allows the scheduler to make more intelligent migration decisions. When one core in the pair is overloaded tasks can be migrated to its paired core to improve throughput without cache-refilling penality typically associated with task migration.Could you please describe the changes to sched_domains w.r.t before and after for P9.
Yes please. cheers