[RFC PATCH 0/7] Machine check handling for Power9 with bacward compatibility.

@@ -23,6 +23,7 @@
 #define __ASM_PPC64_MCE_H__
 
 #include <linux/bitops.h>
+#include <asm/opal.h>
 
 /*
  * Machine Check bits on power7 and power8

@@ -66,109 +67,6 @@
 
 #define P8_DSISR_MC_SLB_ERRORS		(P7_DSISR_MC_SLB_ERRORS | \
 					 P8_DSISR_MC_ERAT_MULTIHIT_SEC)
-enum MCE_Version {
-	MCE_V1 = 1,
-};
-
-enum MCE_Severity {
-	MCE_SEV_NO_ERROR = 0,
-	MCE_SEV_WARNING = 1,
-	MCE_SEV_ERROR_SYNC = 2,
-	MCE_SEV_FATAL = 3,
-};
-
-enum MCE_Disposition {
-	MCE_DISPOSITION_RECOVERED = 0,
-	MCE_DISPOSITION_NOT_RECOVERED = 1,
-};
-
-enum MCE_Initiator {
-	MCE_INITIATOR_UNKNOWN = 0,
-	MCE_INITIATOR_CPU = 1,
-};
-
-enum MCE_ErrorType {
-	MCE_ERROR_TYPE_UNKNOWN = 0,
-	MCE_ERROR_TYPE_UE = 1,
-	MCE_ERROR_TYPE_SLB = 2,
-	MCE_ERROR_TYPE_ERAT = 3,
-	MCE_ERROR_TYPE_TLB = 4,
-};
-
-enum MCE_UeErrorType {
-	MCE_UE_ERROR_INDETERMINATE = 0,
-	MCE_UE_ERROR_IFETCH = 1,
-	MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
-	MCE_UE_ERROR_LOAD_STORE = 3,
-	MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
-};
-
-enum MCE_SlbErrorType {
-	MCE_SLB_ERROR_INDETERMINATE = 0,
-	MCE_SLB_ERROR_PARITY = 1,
-	MCE_SLB_ERROR_MULTIHIT = 2,
-};
-
-enum MCE_EratErrorType {
-	MCE_ERAT_ERROR_INDETERMINATE = 0,
-	MCE_ERAT_ERROR_PARITY = 1,
-	MCE_ERAT_ERROR_MULTIHIT = 2,
-};
-
-enum MCE_TlbErrorType {
-	MCE_TLB_ERROR_INDETERMINATE = 0,
-	MCE_TLB_ERROR_PARITY = 1,
-	MCE_TLB_ERROR_MULTIHIT = 2,
-};
-
-struct machine_check_event {
-	enum MCE_Version	version:8;	/* 0x00 */
-	uint8_t			in_use;		/* 0x01 */
-	enum MCE_Severity	severity:8;	/* 0x02 */
-	enum MCE_Initiator	initiator:8;	/* 0x03 */
-	enum MCE_ErrorType	error_type:8;	/* 0x04 */
-	enum MCE_Disposition	disposition:8;	/* 0x05 */
-	uint8_t			reserved_1[2];	/* 0x06 */
-	uint64_t		gpr3;		/* 0x08 */
-	uint64_t		srr0;		/* 0x10 */
-	uint64_t		srr1;		/* 0x18 */
-	union {					/* 0x20 */
-		struct {
-			enum MCE_UeErrorType ue_error_type:8;
-			uint8_t		effective_address_provided;
-			uint8_t		physical_address_provided;
-			uint8_t		reserved_1[5];
-			uint64_t	effective_address;
-			uint64_t	physical_address;
-			uint8_t		reserved_2[8];
-		} ue_error;
-
-		struct {
-			enum MCE_SlbErrorType slb_error_type:8;
-			uint8_t		effective_address_provided;
-			uint8_t		reserved_1[6];
-			uint64_t	effective_address;
-			uint8_t		reserved_2[16];
-		} slb_error;
-
-		struct {
-			enum MCE_EratErrorType erat_error_type:8;
-			uint8_t		effective_address_provided;
-			uint8_t		reserved_1[6];
-			uint64_t	effective_address;
-			uint8_t		reserved_2[16];
-		} erat_error;
-
-		struct {
-			enum MCE_TlbErrorType tlb_error_type:8;
-			uint8_t		effective_address_provided;
-			uint8_t		reserved_1[6];
-			uint64_t	effective_address;
-			uint8_t		reserved_2[16];
-		} tlb_error;
-	} u;
-};
-
 struct mce_error_info {
 	enum MCE_ErrorType error_type:8;
 	union {

@@ -189,10 +87,10 @@ struct mce_error_info {
 extern void save_mce_event(struct pt_regs *regs, long handled,
 			   struct mce_error_info *mce_err, uint64_t nip,
 			   uint64_t addr);
-extern int get_mce_event(struct machine_check_event *mce, bool release);
+extern int get_mce_event(struct OpalMachineCheckEvent *mce, bool release);
 extern void release_mce_event(void);
 extern void machine_check_queue_event(void);
-extern void machine_check_print_event_info(struct machine_check_event *evt);
-extern uint64_t get_mce_fault_addr(struct machine_check_event *evt);
+extern void machine_check_print_event_info(struct OpalMachineCheckEvent *evt);
+extern uint64_t get_mce_fault_addr(struct OpalMachineCheckEvent *evt);
 
 #endif /* __ASM_PPC64_MCE_H__ */

@@ -585,6 +585,182 @@ struct OpalHMIEvent {
 	} u;
 };
 
+/* Machine Check event */
+enum MCE_Version {
+	MCE_V1 = 1,
+};
+
+enum MCE_Severity {
+	MCE_SEV_NO_ERROR = 0,
+	MCE_SEV_WARNING = 1,
+	MCE_SEV_ERROR_SYNC = 2,
+	MCE_SEV_FATAL = 3,
+	MCE_SEV_ERROR_ASYNC = 4,
+};
+
+enum MCE_Disposition {
+	MCE_DISPOSITION_RECOVERED = 0,
+	MCE_DISPOSITION_NOT_RECOVERED = 1,
+};
+
+enum MCE_Initiator {
+	MCE_INITIATOR_UNKNOWN = 0,
+	MCE_INITIATOR_CPU = 1,
+};
+
+enum MCE_ErrorType {
+	MCE_ERROR_TYPE_UNKNOWN = 0,
+	MCE_ERROR_TYPE_UE = 1,
+	MCE_ERROR_TYPE_SLB = 2,
+	MCE_ERROR_TYPE_ERAT = 3,
+	MCE_ERROR_TYPE_TLB = 4,
+	MCE_ERROR_TYPE_NEST = 5,
+	MCE_ERROR_TYPE_CRESP = 6,
+	MCE_ERROR_TYPE_FSPACE = 7,
+	MCE_ERROR_TYPE_ASYNC = 8,
+};
+
+enum MCE_UeErrorType {
+	MCE_UE_ERROR_INDETERMINATE = 0,
+	MCE_UE_ERROR_IFETCH = 1,
+	MCE_UE_ERROR_PAGE_TABLE_WALK_IFETCH = 2,
+	MCE_UE_ERROR_LOAD_STORE = 3,
+	MCE_UE_ERROR_PAGE_TABLE_WALK_LOAD_STORE = 4,
+};
+
+enum MCE_SlbErrorType {
+	MCE_SLB_ERROR_INDETERMINATE = 0,
+	MCE_SLB_ERROR_PARITY = 1,
+	MCE_SLB_ERROR_MULTIHIT = 2,
+};
+
+enum MCE_EratErrorType {
+	MCE_ERAT_ERROR_INDETERMINATE = 0,
+	MCE_ERAT_ERROR_PARITY = 1,
+	MCE_ERAT_ERROR_MULTIHIT = 2,
+};
+
+enum MCE_TlbErrorType {
+	MCE_TLB_ERROR_INDETERMINATE = 0,
+	MCE_TLB_ERROR_PARITY = 1,
+	MCE_TLB_ERROR_MULTIHIT = 2,
+	MCE_TLB_ERROR_TLBIEL_PROG_ERROR = 3,
+};
+
+enum MCE_NestErrorType {
+	MCE_NEST_ERROR_ABRT_IFETCH = 0,
+	MCE_NEST_ERROR_ABRT_IFETCH_TABLEWALK = 1,
+	MCE_NEST_ERROR_ABRT_LOAD = 2,
+	MCE_NEST_ERROR_ABRT_LOAD_TABLEWALK = 3,
+};
+
+enum MCE_CrespErrorType {
+	MCE_CRESP_ERROR_BAD_RADDR_IFETCH = 0,
+	MCE_CRESP_ERROR_BAD_RADDR_IFETCH_TABLEWALK = 1,
+	MCE_CRESP_ERROR_BAD_RADDR_LOAD = 2,
+	MCE_CRESP_ERROR_BAD_RADDR_LOAD_TABLEWALK = 3,
+};
+
+enum MCE_FspaceErrorType {
+	MCE_FSPACE_ERROR_IFETCH = 0,
+	MCE_FSPACE_ERROR_IFETCH_TABLEWALK = 1,
+	MCE_FSPACE_ERROR_RADDR_TRANSLATION = 2,
+	MCE_FSPACE_ERROR_RADDR_LOAD = 3,
+};
+
+enum MCE_AsyncErrorType {
+	MCE_ASYNC_ERROR_REAL_ADDR_STORE = 0,
+	MCE_ASYNC_ERROR_NEST_ABRT_STORE = 1,
+};
+
+struct OpalMachineCheckEvent {
+	uint8_t			version;	/* 0x00 */
+	uint8_t			in_use;		/* 0x01 */
+	uint8_t			severity;	/* 0x02 */
+	uint8_t			initiator;	/* 0x03 */
+	uint8_t			error_type;	/* 0x04 */
+	uint8_t			disposition;	/* 0x05 */
+	uint8_t			reserved_1[2];	/* 0x06 */
+	uint64_t		gpr3;		/* 0x08 */
+	uint64_t		srr0;		/* 0x10 */
+	uint64_t		srr1;		/* 0x18 */
+
+	union {					/* 0x20 */
+		/* Next 32 bytes contains specific information of MCE error. */
+		struct {
+			/* enum MCE_UeErrorType */
+			uint8_t		ue_error_type;
+			uint8_t		effective_address_provided;
+			uint8_t		physical_address_provided;
+			uint8_t		reserved_1[5];
+			uint64_t	effective_address;
+			uint64_t	physical_address;
+			uint8_t		reserved_2[8];
+		} ue_error;
+
+		struct {
+			/* enum MCE_SlbErrorType */
+			uint8_t		slb_error_type;
+			uint8_t		effective_address_provided;
+			uint8_t		reserved_1[6];
+			uint64_t	effective_address;
+			uint8_t		reserved_2[16];
+		} slb_error;
+
+		struct {
+			/* enum MCE_EratErrorType */
+			uint8_t		erat_error_type;
+			uint8_t		effective_address_provided;
+			uint8_t		reserved_1[6];
+			uint64_t	effective_address;
+			uint8_t		reserved_2[16];
+		} erat_error;
+
+		struct {
+			/* enum MCE_TlbErrorType  */
+			uint8_t		tlb_error_type;
+			uint8_t		effective_address_provided;
+			uint8_t		reserved_1[6];
+			uint64_t	effective_address;
+			uint8_t		reserved_2[16];
+		} tlb_error;
+
+		struct {
+			/* enum MCE_NestErrorType */
+			uint8_t		nest_error_type;
+			uint8_t		effective_address_provided;
+			uint8_t		reserved_1[6];
+			uint64_t	effective_address;
+			uint8_t		reserved_2[16];
+		} nest_error;
+
+		struct {
+			/* enum MCE_CrespErrorType */
+			uint8_t		cresp_error_type;
+			uint8_t		effective_address_provided;
+			uint8_t		reserved_1[6];
+			uint64_t	effective_address;
+			uint8_t		reserved_2[16];
+		} cresp_error;
+
+		struct {
+			/* enum MCE_FspaceErrorType */
+			uint8_t		fspace_error_type;
+			uint8_t		effective_address_provided;
+			uint8_t		reserved_1[6];
+			uint64_t	effective_address;
+			uint8_t		reserved_2[16];
+		} fspace_error;
+
+		struct {
+			/* enum MCE_AsyncErrorType */
+			uint8_t		async_error_type;
+			uint8_t		reserved_1[7];
+			uint8_t		reserved_2[24];
+		} async_error;
+	} u;
+};
+
 enum {
 	OPAL_P7IOC_DIAG_TYPE_NONE	= 0,
 	OPAL_P7IOC_DIAG_TYPE_RGC	= 1,

@@ -30,18 +30,18 @@
 #include <asm/mce.h>
 
 static DEFINE_PER_CPU(int, mce_nest_count);
-static DEFINE_PER_CPU(struct machine_check_event[MAX_MC_EVT], mce_event);
+static DEFINE_PER_CPU(struct OpalMachineCheckEvent[MAX_MC_EVT], mce_event);
 
 /* Queue for delayed MCE events. */
 static DEFINE_PER_CPU(int, mce_queue_count);
-static DEFINE_PER_CPU(struct machine_check_event[MAX_MC_EVT], mce_event_queue);
+static DEFINE_PER_CPU(struct OpalMachineCheckEvent[MAX_MC_EVT], mce_event_queue);
 
 static void machine_check_process_queued_event(struct irq_work *work);
 static struct irq_work mce_event_process_work = {
         .func = machine_check_process_queued_event,
 };
 
-static void mce_set_error_info(struct machine_check_event *mce,
+static void mce_set_error_info(struct OpalMachineCheckEvent *mce,
 			       struct mce_error_info *mce_err)
 {
 	mce->error_type = mce_err->error_type;

@@ -73,7 +73,7 @@ void save_mce_event(struct pt_regs *regs, long handled,
 		    uint64_t nip, uint64_t addr)
 {
 	int index = __this_cpu_inc_return(mce_nest_count) - 1;
-	struct machine_check_event *mce = this_cpu_ptr(&mce_event[index]);
+	struct OpalMachineCheckEvent *mce = this_cpu_ptr(&mce_event[index]);
 
 	/*
 	 * Return if we don't have enough space to log mce event.

@@ -139,10 +139,10 @@ void save_mce_event(struct pt_regs *regs, long handled,
  * preemption will not be scheduled until ret_from_expect() routine
  * is called.
  */
-int get_mce_event(struct machine_check_event *mce, bool release)
+int get_mce_event(struct OpalMachineCheckEvent *mce, bool release)
 {
 	int index = __this_cpu_read(mce_nest_count) - 1;
-	struct machine_check_event *mc_evt;
+	struct OpalMachineCheckEvent *mc_evt;
 	int ret = 0;
 
 	/* Sanity check */

@@ -177,7 +177,7 @@ void release_mce_event(void)
 void machine_check_queue_event(void)
 {
 	int index;
-	struct machine_check_event evt;
+	struct OpalMachineCheckEvent evt;
 
 	if (!get_mce_event(&evt, MCE_EVENT_RELEASE))
 		return;

@@ -214,7 +214,7 @@ static void machine_check_process_queued_event(struct irq_work *work)
 	}
 }
 
-void machine_check_print_event_info(struct machine_check_event *evt)
+void machine_check_print_event_info(struct OpalMachineCheckEvent *evt)
 {
 	const char *level, *sevstr, *subtype;
 	static const char *mc_ue_types[] = {

@@ -322,7 +322,7 @@ void machine_check_print_event_info(struct machine_check_event *evt)
 	}
 }
 
-uint64_t get_mce_fault_addr(struct machine_check_event *evt)
+uint64_t get_mce_fault_addr(struct OpalMachineCheckEvent *evt)
 {
 	switch (evt->error_type) {
 	case MCE_ERROR_TYPE_UE:

@@ -392,7 +392,7 @@ int opal_put_chars(uint32_t vtermno, const char *data, int total_len)
 }
 
 static int opal_recover_mce(struct pt_regs *regs,
-					struct machine_check_event *evt)
+					struct OpalMachineCheckEvent *evt)
 {
 	int recovered = 0;
 	uint64_t ea = get_mce_fault_addr(evt);

@@ -432,7 +432,7 @@ static int opal_recover_mce(struct pt_regs *regs,
 
 int opal_machine_check(struct pt_regs *regs)
 {
-	struct machine_check_event evt;
+	struct OpalMachineCheckEvent evt;
 	int ret;
 
 	if (!get_mce_event(&evt, MCE_EVENT_RELEASE))

@@ -108,6 +108,8 @@ struct machdep_calls {
 
 	/* Early exception handlers called in realmode */
 	int		(*hmi_exception_early)(struct pt_regs *regs);
+	int		(*machine_check_early)(struct pt_regs *regs,
+							long *handled);
 
 	/* Called during machine check exception to retrive fixup address. */
 	bool		(*mce_check_early_recovery)(struct pt_regs *regs);

@@ -167,7 +167,8 @@
 #define OPAL_INT_EOI				124
 #define OPAL_INT_SET_MFRR			125
 #define OPAL_PCI_TCE_KILL			126
-#define OPAL_LAST				126
+#define OPAL_HANDLE_MACHINE_CHECK		145
+#define OPAL_LAST				145
 
 /* Device tree flags */
 

@@ -189,6 +189,8 @@ int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
 		uint64_t length);
 int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
 int64_t opal_handle_hmi(void);
+int64_t opal_rm_handle_machine_check(uint64_t srr0, uint64_t srr1, uint64_t dar,
+					uint64_t dsisr, uint64_t *mce);
 int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
 int64_t opal_unregister_dump_region(uint32_t id);
 int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);

@@ -279,6 +281,7 @@ extern int opal_hmi_handler_init(void);
 extern int opal_event_init(void);
 
 extern int opal_machine_check(struct pt_regs *regs);
+extern int opal_machine_check_early(struct pt_regs *regs, long *handled);
 extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
 extern int opal_hmi_exception_early(struct pt_regs *regs);
 extern int opal_handle_hmi_exception(struct pt_regs *regs);

@@ -302,12 +302,25 @@ void system_reset_exception(struct pt_regs *regs)
 long machine_check_early(struct pt_regs *regs)
 {
 	long handled = 0;
+	int rc = 0;
 
 	__this_cpu_inc(irq_stat.mce_exceptions);
 
 	add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
 
-	if (cur_cpu_spec && cur_cpu_spec->machine_check_early)
+	/*
+	 * See if platform is capable of handling machine check. (e.g. PowerNV
+	 * platform may take help from OPAL firmware to handle machine check.)
+	 * Otherwise fallthrough and allow CPU to handle this machine check.
+	 *
+	 * If rc == -1 then it means firmware does not provide support for
+	 * machine check handling for this CPU chip. Fallback to in-kernel
+	 * machine check handler.
+	 */
+	if (ppc_md.machine_check_early)
+		rc = ppc_md.machine_check_early(regs, &handled);
+
+	if (!rc && cur_cpu_spec && cur_cpu_spec->machine_check_early)
 		handled = cur_cpu_spec->machine_check_early(regs);
 	return handled;
 }

@@ -312,3 +312,4 @@ OPAL_CALL(opal_int_set_mfrr,			OPAL_INT_SET_MFRR);
 OPAL_CALL_REAL(opal_rm_int_set_mfrr,		OPAL_INT_SET_MFRR);
 OPAL_CALL(opal_pci_tce_kill,			OPAL_PCI_TCE_KILL);
 OPAL_CALL_REAL(opal_rm_pci_tce_kill,		OPAL_PCI_TCE_KILL);
+OPAL_CALL_REAL(opal_rm_handle_machine_check,		OPAL_HANDLE_MACHINE_CHECK);

@@ -488,6 +488,22 @@ int opal_machine_check(struct pt_regs *regs)
 	return 0;
 }
 
+/* Early mce handler called in real mode. */
+int opal_machine_check_early(struct pt_regs *regs, long *handled)
+{
+	int rc;
+	struct OpalMachineCheckEvent evt = { 0 };
+
+	*handled = 0;
+
+	rc = opal_rm_handle_machine_check(regs->nip, regs->msr, regs->dar,
+					regs->dsisr, (uint64_t *)&evt);
+	if (rc != OPAL_SUCCESS)
+		return -1;
+
+	return 0;
+}
+
 /* Early hmi handler called in real mode. */
 int opal_hmi_exception_early(struct pt_regs *regs)
 {

@@ -264,6 +264,10 @@ static void __init pnv_setup_machdep_opal(void)
 	ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;
 	ppc_md.hmi_exception_early = opal_hmi_exception_early;
 	ppc_md.handle_hmi_exception = opal_handle_hmi_exception;
+
+	/* Check if OPAL is capable of handling machine check. */
+	if (opal_check_token(OPAL_HANDLE_MACHINE_CHECK))
+		ppc_md.machine_check_early = opal_machine_check_early;
 }
 
 static int __init pnv_probe(void)

@@ -88,9 +88,12 @@ extern void save_mce_event(struct pt_regs *regs, long handled,
 			   struct mce_error_info *mce_err, uint64_t nip,
 			   uint64_t addr);
 extern int get_mce_event(struct OpalMachineCheckEvent *mce, bool release);
+extern int set_mce_event(struct OpalMachineCheckEvent *mce);
 extern void release_mce_event(void);
 extern void machine_check_queue_event(void);
 extern void machine_check_print_event_info(struct OpalMachineCheckEvent *evt);
 extern uint64_t get_mce_fault_addr(struct OpalMachineCheckEvent *evt);
+extern long handle_mce_errors(struct pt_regs *regs,
+					struct OpalMachineCheckEvent *evt);
 
 #endif /* __ASM_PPC64_MCE_H__ */

@@ -166,6 +166,32 @@ int get_mce_event(struct OpalMachineCheckEvent *mce, bool release)
 	return ret;
 }
 
+int set_mce_event(struct OpalMachineCheckEvent *mce)
+{
+	int index = __this_cpu_inc_return(mce_nest_count) - 1;
+	struct OpalMachineCheckEvent *mc_evt = this_cpu_ptr(&mce_event[index]);
+	int ret = 0;
+
+	/* Sanity check */
+	if (index < 0)
+		return ret;
+
+	/* Check if we have MCE info slot within array limit. */
+	if (index < MAX_MC_EVT) {
+		/* Copy the event structure and release the original */
+		if (mce) {
+			*mc_evt = *mce;
+			/* endian conversions */
+			mc_evt->srr0 = be64_to_cpu(mce->srr0);
+			mc_evt->srr1 = be64_to_cpu(mce->srr1);
+			mc_evt->u.ue_error.effective_address =
+				be64_to_cpu(mce->u.ue_error.effective_address);
+		}
+		ret = 1;
+	}
+	return ret;
+}
+
 void release_mce_event(void)
 {
 	get_mce_event(NULL, true);

@@ -372,3 +372,41 @@ long __machine_check_early_realmode_p8(struct pt_regs *regs)
 	save_mce_event(regs, handled, &mce_error_info, nip, addr);
 	return handled;
 }
+
+static long flush_tlb(void)
+{
+	long handled = 0;
+
+	if (cur_cpu_spec && cur_cpu_spec->flush_tlb) {
+		cur_cpu_spec->flush_tlb(TLB_INVAL_SCOPE_GLOBAL);
+		handled = 1;
+	}
+	return handled;
+}
+
+long handle_mce_errors(struct pt_regs *regs, struct OpalMachineCheckEvent *evt)
+{
+	long handled = 1;
+
+	if (evt->disposition == MCE_DISPOSITION_RECOVERED)
+		return handled;
+
+	switch (evt->error_type) {
+	case MCE_ERROR_TYPE_UE:
+		handled = mce_handle_ue_error(regs);
+		break;
+	case MCE_ERROR_TYPE_SLB:
+	case MCE_ERROR_TYPE_ERAT:
+		flush_and_reload_slb();
+		handled = 1;
+		break;
+	case MCE_ERROR_TYPE_TLB:
+		handled = flush_tlb();
+		break;
+	default:
+		handled = 0;
+	}
+	if (handled)
+		evt->disposition = MCE_DISPOSITION_RECOVERED;
+	return handled;
+}

@@ -501,6 +501,8 @@ int opal_machine_check_early(struct pt_regs *regs, long *handled)
 	if (rc != OPAL_SUCCESS)
 		return -1;
 
+	*handled = handle_mce_errors(regs, &evt);
+	set_mce_event(&evt);
 	return 0;
 }
 

@@ -238,6 +238,12 @@ BEGIN_FTR_SECTION
 	std	r9,_CCR(r1)		/* Save CR in stackframe */
 	/* Save r9 through r13 from EXMC save area to stack frame. */
 	EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
+	std	r0,GPR0(r1)	/* Save r0 */
+	EXCEPTION_PROLOG_COMMON_3(0x200)
+	bl	save_nvgprs
+	addi	r3,r1,STACK_FRAME_OVERHEAD
+	bl	machine_check_early
+	std	r3,RESULT(r1)	/* Save result */
 	mfmsr	r11			/* get MSR value */
 	ori	r11,r11,MSR_ME		/* turn on ME bit */
 	ori	r11,r11,MSR_RI		/* turn on RI bit */

@@ -345,12 +351,6 @@ EXC_COMMON_BEGIN(machine_check_common)
 	 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
 	 */
 EXC_COMMON_BEGIN(machine_check_handle_early)
-	std	r0,GPR0(r1)	/* Save r0 */
-	EXCEPTION_PROLOG_COMMON_3(0x200)
-	bl	save_nvgprs
-	addi	r3,r1,STACK_FRAME_OVERHEAD
-	bl	machine_check_early
-	std	r3,RESULT(r1)	/* Save result */
 	ld	r12,_MSR(r1)
 #ifdef	CONFIG_PPC_P7_NAP
 	/*

@@ -320,6 +320,8 @@ void machine_check_print_event_info(struct OpalMachineCheckEvent *evt)
 	       "Recovered" : "[Not recovered");
 	printk("%s  Initiator: %s\n", level,
 	       evt->initiator == MCE_INITIATOR_CPU ? "CPU" : "Unknown");
+	printk("%s  NIP [%016llx]: %pS\n", level, evt->srr0,
+							(void *)evt->srr0);
 	switch (evt->error_type) {
 	case MCE_ERROR_TYPE_UE:
 		subtype = evt->u.ue_error.ue_error_type <

@@ -91,7 +91,8 @@ extern int get_mce_event(struct OpalMachineCheckEvent *mce, bool release);
 extern int set_mce_event(struct OpalMachineCheckEvent *mce);
 extern void release_mce_event(void);
 extern void machine_check_queue_event(void);
-extern void machine_check_print_event_info(struct OpalMachineCheckEvent *evt);
+extern void machine_check_print_event_info(struct OpalMachineCheckEvent *evt,
+							bool user_mode);
 extern uint64_t get_mce_fault_addr(struct OpalMachineCheckEvent *evt);
 extern long handle_mce_errors(struct pt_regs *regs,
 					struct OpalMachineCheckEvent *evt);

@@ -235,12 +235,13 @@ static void machine_check_process_queued_event(struct irq_work *work)
 	while (__this_cpu_read(mce_queue_count) > 0) {
 		index = __this_cpu_read(mce_queue_count) - 1;
 		machine_check_print_event_info(
-				this_cpu_ptr(&mce_event_queue[index]));
+				this_cpu_ptr(&mce_event_queue[index]), false);
 		__this_cpu_dec(mce_queue_count);
 	}
 }
 
-void machine_check_print_event_info(struct OpalMachineCheckEvent *evt)
+void machine_check_print_event_info(struct OpalMachineCheckEvent *evt,
+							bool user_mode)
 {
 	const char *level, *sevstr, *subtype;
 	static const char *mc_ue_types[] = {

@@ -320,8 +321,13 @@ void machine_check_print_event_info(struct OpalMachineCheckEvent *evt)
 	       "Recovered" : "[Not recovered");
 	printk("%s  Initiator: %s\n", level,
 	       evt->initiator == MCE_INITIATOR_CPU ? "CPU" : "Unknown");
-	printk("%s  NIP [%016llx]: %pS\n", level, evt->srr0,
+	if (user_mode) {
+		printk("%s  NIP: [%016llx] PID: %d Comm: %s\n", level,
+				evt->srr0, current->pid, current->comm);
+	} else {
+		printk("%s  NIP [%016llx]: %pS\n", level, evt->srr0,
 							(void *)evt->srr0);
+	}
 	switch (evt->error_type) {
 	case MCE_ERROR_TYPE_UE:
 		subtype = evt->u.ue_error.ue_error_type <

@@ -444,7 +444,7 @@ int opal_machine_check(struct pt_regs *regs)
 		       evt.version);
 		return 0;
 	}
-	machine_check_print_event_info(&evt);
+	machine_check_print_event_info(&evt, user_mode(regs));
 
 	if (opal_recover_mce(regs, &evt))
 		return 1;

@@ -264,6 +264,29 @@ void machine_check_print_event_info(struct OpalMachineCheckEvent *evt)
 		"Indeterminate",
 		"Parity",
 		"Multihit",
+		"Tlbiel programming error",
+	};
+	static const char *mc_nest_types[] = {
+		"Ifetch due to foreign link time out",
+		"Instruction tablewalk due to foreign link time out",
+		"Foreign Link Time out for load",
+		"Foreign Link Time out for tablewalk",
+	};
+	static const char *mc_cresp_types[] = {
+		"Real Address error for an ifetch",
+		"Real Address error for an ifetch tablewalk",
+		"Bad real address for a load",
+		"Bad address for load/store tablewalk",
+	};
+	static const char *mc_fspace_types[] = {
+		"Instruction Fetch to foreign address space",
+		"I-side tablewalk host real addr in the foreign address range",
+		"Host real addess to foreign space",
+		"Load/store real address went to a foreign address",
+	};
+	static const char *mc_async_types[] = {
+		"Real address error (CRESP) from store",
+		"Foreign link time out (nest abort) due to a store instruction",
 	};
 
 	/* Print things out */

@@ -341,6 +364,43 @@ void machine_check_print_event_info(struct OpalMachineCheckEvent *evt)
 			printk("%s    Effective address: %016llx\n",
 			       level, evt->u.tlb_error.effective_address);
 		break;
+	case MCE_ERROR_TYPE_NEST:
+		subtype = evt->u.nest_error.nest_error_type <
+			ARRAY_SIZE(mc_nest_types) ?
+			mc_nest_types[evt->u.nest_error.nest_error_type]
+			: "Unknown";
+		printk("%s  Error type: NEST ABORT [%s]\n", level, subtype);
+		if (evt->u.nest_error.effective_address_provided)
+			printk("%s    Effective address: %016llx\n",
+			       level, evt->u.nest_error.effective_address);
+		break;
+	case MCE_ERROR_TYPE_CRESP:
+		subtype = evt->u.cresp_error.cresp_error_type <
+			ARRAY_SIZE(mc_cresp_types) ?
+			mc_cresp_types[evt->u.cresp_error.cresp_error_type]
+			: "Unknown";
+		printk("%s  Error type: CRESP [%s]\n", level, subtype);
+		if (evt->u.cresp_error.effective_address_provided)
+			printk("%s    Effective address: %016llx\n",
+			       level, evt->u.cresp_error.effective_address);
+		break;
+	case MCE_ERROR_TYPE_FSPACE:
+		subtype = evt->u.fspace_error.fspace_error_type <
+			ARRAY_SIZE(mc_fspace_types) ?
+			mc_fspace_types[evt->u.fspace_error.fspace_error_type]
+			: "Unknown";
+		printk("%s  Error type: FOREIGN SPACE [%s]\n", level, subtype);
+		if (evt->u.fspace_error.effective_address_provided)
+			printk("%s    Effective address: %016llx\n",
+			       level, evt->u.fspace_error.effective_address);
+		break;
+	case MCE_ERROR_TYPE_ASYNC:
+		subtype = evt->u.async_error.async_error_type <
+			ARRAY_SIZE(mc_async_types) ?
+			mc_async_types[evt->u.async_error.async_error_type]
+			: "Unknown";
+		printk("%s  Error type: ASYNC MC [%s]\n", level, subtype);
+		break;
 	default:
 	case MCE_ERROR_TYPE_UNKNOWN:
 		printk("%s  Error type: Unknown\n", level);

@@ -367,6 +427,14 @@ uint64_t get_mce_fault_addr(struct OpalMachineCheckEvent *evt)
 		if (evt->u.tlb_error.effective_address_provided)
 			return evt->u.tlb_error.effective_address;
 		break;
+	case MCE_ERROR_TYPE_NEST:
+		if (evt->u.nest_error.effective_address_provided)
+			return evt->u.nest_error.effective_address;
+		break;
+	case MCE_ERROR_TYPE_CRESP:
+		if (evt->u.cresp_error.effective_address_provided)
+			return evt->u.cresp_error.effective_address;
+		break;
 	default:
 	case MCE_ERROR_TYPE_UNKNOWN:
 		break;