[PATCH] powerpc/perf: Add constraints for power9 l2/l3 bus events
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From: Madhavan Srinivasan <hidden>
Date: 2016-11-30 13:08:19
Subsystem:
linux for powerpc (32-bit and 64-bit), the rest · Maintainers:
Madhavan Srinivasan, Linus Torvalds
In Power9, L2/L3 bus events are always available as a
"bank" of 4 events. To obtain the counts for any of the
l2/l3 bus events in a given bank, the user will have to
program PMC4 with corresponding l2/l3 bus event for that
bank. Patch adds a constraint check to enforce it.
Signed-off-by: Madhavan Srinivasan <redacted>
---
arch/powerpc/include/asm/perf_event_server.h | 1 +
arch/powerpc/perf/core-book3s.c | 4 ++++
arch/powerpc/perf/power9-pmu.c | 20 ++++++++++++++++++++
3 files changed, 25 insertions(+)
diff --git a/arch/powerpc/include/asm/perf_event_server.h b/arch/powerpc/include/asm/perf_event_server.h
index e157489ee7a1..3e6616c3e911 100644
--- a/arch/powerpc/include/asm/perf_event_server.h
+++ b/arch/powerpc/include/asm/perf_event_server.h@@ -38,6 +38,7 @@ struct power_pmu { unsigned long *valp); int (*get_alternatives)(u64 event_id, unsigned int flags, u64 alt[]); + int (*get_llevent_constraint)(u64 events[], int n_ev); u64 (*bhrb_filter_map)(u64 branch_sample_type); void (*config_bhrb)(u64 pmu_bhrb_filter); void (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c
index 72c27b8d2cf3..2cdf2647cdb0 100644
--- a/arch/powerpc/perf/core-book3s.c
+++ b/arch/powerpc/perf/core-book3s.c@@ -1267,6 +1267,10 @@ static void power_pmu_enable(struct pmu *pmu) goto out; } + if ( (ppmu->get_llevent_constraint) && + ppmu->get_llevent_constraint(cpuhw->events, cpuhw->n_events)) + goto out; + if (!(ppmu->flags & PPMU_ARCH_207S)) { /* * Add in MMCR0 freeze bits corresponding to the attr.exclude_*
diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c
index 8e9a81967ff8..d67d532116b3 100644
--- a/arch/powerpc/perf/power9-pmu.c
+++ b/arch/powerpc/perf/power9-pmu.c@@ -181,6 +181,25 @@ static void power9_config_bhrb(u64 pmu_bhrb_filter) mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter)); } +static int power9_llevent_get_constraint(u64 event[], int n_ev) +{ + int i; + unsigned int pmc, unit, mask = 0; + + for (i = 0; i < n_ev; ++i) { + pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; + unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; + if (unit >= 6 && unit <= 9) + mask |= 1 << (pmc - 1); + + } + + if ((mask) && ((mask & 0xf) < 0x8)) + return -1; + + return 0; +} + #define C(x) PERF_COUNT_HW_CACHE_##x /*
@@ -307,6 +326,7 @@ static struct power_pmu power9_pmu = { .cache_events = &power9_cache_events, .attr_groups = power9_pmu_attr_groups, .bhrb_nr = 32, + .get_llevent_constraint = power9_llevent_get_constraint, }; static int __init init_power9_pmu(void)
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2.7.4