[PATCH] powerpc/8xx: use SPRN_EIE and SPRN_EID to enable/disable interrupts

The 8xx has two special registers called EID (External Interrupt
Disable) and EIE (External Interrupt Enable) for clearing/setting
EE in MSR. It avoids the three instructions set mfmsr/ori/mtmsr or
mfmsr/rlwinm/mtmsr.

We just have to write something in the register to change MSR EE
bit. So we write r0 into the register, regardless of r0 value.

Signed-off-by: Christophe Leroy <redacted>
---
 arch/powerpc/include/asm/hw_irq.h  | 6 ++++++
 arch/powerpc/include/asm/reg.h     | 2 ++
 arch/powerpc/include/asm/reg_8xx.h | 5 +++++
 3 files changed, 13 insertions(+)

diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index c7d82ff..7ffb392 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h

@@ -155,6 +155,8 @@ static inline unsigned long arch_local_irq_save(void)
 	unsigned long flags = arch_local_save_flags();
 #ifdef CONFIG_BOOKE
 	asm volatile("wrteei 0" : : : "memory");
+#elif defined(CONFIG_PPC_8xx)
+	wrtspr(SPRN_EID);
 #else
 	SET_MSR_EE(flags & ~MSR_EE);
 #endif

@@ -165,6 +167,8 @@ static inline void arch_local_irq_disable(void)
 {
 #ifdef CONFIG_BOOKE
 	asm volatile("wrteei 0" : : : "memory");
+#elif defined(CONFIG_PPC_8xx)
+	wrtspr(SPRN_EID);
 #else
 	arch_local_irq_save();
 #endif

@@ -174,6 +178,8 @@ static inline void arch_local_irq_enable(void)
 {
 #ifdef CONFIG_BOOKE
 	asm volatile("wrteei 1" : : : "memory");
+#elif defined(CONFIG_PPC_8xx)
+	wrtspr(SPRN_EIE);
 #else
 	unsigned long msr = mfmsr();
 	SET_MSR_EE(msr | MSR_EE);

diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index f69f40f..4bbd9be 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h

@@ -1246,6 +1246,8 @@ static inline void mtmsr_isync(unsigned long val)
 				     : "r" ((unsigned long)(v)) \
 				     : "memory")
 #endif
+#define wrtspr(rn)	asm volatile("mtspr " __stringify(rn) ",0" : \
+				     : : "memory")
 
 extern void msr_check_and_set(unsigned long bits);
 extern bool strict_msr_control;

diff --git a/arch/powerpc/include/asm/reg_8xx.h b/arch/powerpc/include/asm/reg_8xx.h
index 6dae71f..d4bca3de 100644
--- a/arch/powerpc/include/asm/reg_8xx.h
+++ b/arch/powerpc/include/asm/reg_8xx.h

@@ -6,6 +6,11 @@
 
 #include <asm/mmu.h>
 
+/* Special MSR manipulation registers */
+#define SPRN_EIE	80	/* External interrupt enable (EE=1, RI=1) */
+#define SPRN_EID	81	/* External interrupt disable (EE=0, RI=1) */
+#define SPRN_NRI	81	/* Non Recoverable interrupt (EE=0, RI=0) */
+
 /* Cache control on the MPC8xx is provided through some additional
  * special purpose registers.
  */

-- 
2.1.0

On Thu, Aug 18, 2016 at 05:56:02PM +0200, Christophe Leroy wrote:

The 8xx has two special registers called EID (External Interrupt
Disable) and EIE (External Interrupt Enable) for clearing/setting
EE in MSR. It avoids the three instructions set mfmsr/ori/mtmsr or
mfmsr/rlwinm/mtmsr.

All 8xx?  What other models?  (5xx for example).

+/* Special MSR manipulation registers */
+#define SPRN_EIE	80	/* External interrupt enable (EE=1, RI=1) */
+#define SPRN_EID	81	/* External interrupt disable (EE=0, RI=1) */
+#define SPRN_NRI	81	/* Non Recoverable interrupt (EE=0, RI=0) */

This is wrong (NRI is 82).  Don't write code you cannot test / don't submit
code you haven't tested?  :-)


Segher

Le 18/08/2016 à 18:34, Segher Boessenkool a écrit :

On Thu, Aug 18, 2016 at 05:56:02PM +0200, Christophe Leroy wrote:

quoted

The 8xx has two special registers called EID (External Interrupt
Disable) and EIE (External Interrupt Enable) for clearing/setting
EE in MSR. It avoids the three instructions set mfmsr/ori/mtmsr or
mfmsr/rlwinm/mtmsr.

All 8xx?  What other models?  (5xx for example).

At least 823, 860, 866 and 885 have it.

Looks like the 5xx have it too (at least the 565). Does Linux supports 
that one at all ?

8272 and 8323 don't have it.

quoted

+/* Special MSR manipulation registers */
+#define SPRN_EIE	80	/* External interrupt enable (EE=1, RI=1) */
+#define SPRN_EID	81	/* External interrupt disable (EE=0, RI=1) */
+#define SPRN_NRI	81	/* Non Recoverable interrupt (EE=0, RI=0) */

This is wrong (NRI is 82).  Don't write code you cannot test / don't submit
code you haven't tested?  :-)

Oops. You're right, copy/paste failure.
Was tested on an 885. Unfortunatly SPRN_NRI is not used (yet) :-(

Christophe

On Thu, Aug 18, 2016 at 06:52:47PM +0200, Christophe Leroy wrote:

Le 18/08/2016 à 18:34, Segher Boessenkool a écrit :

quoted

On Thu, Aug 18, 2016 at 05:56:02PM +0200, Christophe Leroy wrote:

quoted

The 8xx has two special registers called EID (External Interrupt
Disable) and EIE (External Interrupt Enable) for clearing/setting
EE in MSR. It avoids the three instructions set mfmsr/ori/mtmsr or
mfmsr/rlwinm/mtmsr.

All 8xx?  What other models?  (5xx for example).

At least 823, 860, 866 and 885 have it.

I haven't been able to find a manual for all 8xx.  But there is AN2055,
which suggests EIE etc. is for all 8xx indeed.

Looks like the 5xx have it too (at least the 565). Does Linux supports 
that one at all ?

All 5xx have it, there is a manual for *that* ("RCPU") :-)

quoted

quoted

+/* Special MSR manipulation registers */
+#define SPRN_EIE	80	/* External interrupt enable (EE=1, RI=1) */
+#define SPRN_EID	81	/* External interrupt disable (EE=0, RI=1) */
+#define SPRN_NRI	81	/* Non Recoverable interrupt (EE=0, RI=0) */

Is it correct to set RI in all places you do now?

quoted

This is wrong (NRI is 82).  Don't write code you cannot test / don't submit
code you haven't tested?  :-)

Oops. You're right, copy/paste failure.
Was tested on an 885. Unfortunatly SPRN_NRI is not used (yet) :-(

Well, that was my point!


Segher

Le 18/08/2016 à 19:54, Segher Boessenkool a écrit :

On Thu, Aug 18, 2016 at 06:52:47PM +0200, Christophe Leroy wrote:

quoted

Le 18/08/2016 à 18:34, Segher Boessenkool a écrit :

quoted

On Thu, Aug 18, 2016 at 05:56:02PM +0200, Christophe Leroy wrote:

quoted

The 8xx has two special registers called EID (External Interrupt
Disable) and EIE (External Interrupt Enable) for clearing/setting
EE in MSR. It avoids the three instructions set mfmsr/ori/mtmsr or
mfmsr/rlwinm/mtmsr.

All 8xx?  What other models?  (5xx for example).

At least 823, 860, 866 and 885 have it.

I haven't been able to find a manual for all 8xx.  But there is AN2055,
which suggests EIE etc. is for all 8xx indeed.

quoted

Looks like the 5xx have it too (at least the 565). Does Linux supports
that one at all ?

All 5xx have it, there is a manual for *that* ("RCPU") :-)

quoted

quoted

quoted

+/* Special MSR manipulation registers */
+#define SPRN_EIE	80	/* External interrupt enable (EE=1, RI=1) */
+#define SPRN_EID	81	/* External interrupt disable (EE=0, RI=1) */
+#define SPRN_NRI	81	/* Non Recoverable interrupt (EE=0, RI=0) */

Is it correct to set RI in all places you do now?

MSR_KERNEL contains the RI bit.
MSR_KERNEL less MSR_IR and MSR_DR is loaded into MSR in 
EXCEPTION_PROLOG_2() in head_8xx.S
Then reloaded with MSR_KERNEL in some places in entry_32.S

And MSR_RI is cleared in restore: in entry_32.S a few insns before the RFI.

So in all C functions, MSR_RI is set.

Christophe

quoted

quoted

This is wrong (NRI is 82).  Don't write code you cannot test / don't submit
code you haven't tested?  :-)

Oops. You're right, copy/paste failure.
Was tested on an 885. Unfortunatly SPRN_NRI is not used (yet) :-(

Well, that was my point!


Segher