Hi Ian,

It looks good, just one question:

+/* XSL registers (Mellanox CX4) */
+static const cxl_p1_reg_t CXL_XSL_Timebase  = {0x0100};
+static const cxl_p1_reg_t CXL_XSL_TB_CTLSTAT = {0x0108};
+static const cxl_p1_reg_t CXL_XSL_FEC       = {0x0158};
+static const cxl_p1_reg_t CXL_XSL_DSNCTL    = {0x0168};

Out of curiosity, in which document did you get those offsets from? I 
remember there used to be some confusion about it. All I could find was 
the internal offsets the firmware remaps those to (in xsl databook).

Feel free to grab the "From:", since the patch has evolved since I 
worked on it. I don't care.

   Fred