[RFC PATCH 0/9] powerpc/mm: Restructure Linux PTE on Book3S/64 to radix format

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25 messages, 5 authors, 2016-02-22 · open the first message on its own page

[RFC PATCH 0/9] powerpc/mm: Restructure Linux PTE on Book3S/64 to radix format

From: Paul Mackerras <hidden>
Date: 2016-02-20 06:12:54 

This patch series modifies the Linux PTE format used on 64-bit Book3S
processors (i.e. POWER server processors) to make the bits line up
with the PTE format used in the radix trees defined in PowerISA v3.0.
This will reduce the amount of further change required to make a
kernel that can run with either a radix MMU or a hashed page table
(HPT) MMU.

This also changes the upper levels of the tree to use real addresses
rather than kernel virtual addresses - that is, we no longer have the
0xc000... at the top of each PGD/PUD/PMD entry.  I made this change
for all 64-bit machines, both embedded and server.

The patch series is against v4.5-rc4 plus Aneesh's "powerpc/mm/hash:
Clear the invalid slot information correctly" patch.

I have compiled this for all the defconfigs in the tree, without
error.  I have tested this, with the fixes branch of the powerpc tree
merged in, both running bare-metal on a POWER8 and in a KVM guest on
that POWER8 system.  In the guest I tested both 4k and 64k configs,
with THP enabled; in the host I tested with 64k page size and THP
enabled.  All these tests ran fine, including running a KVM guest on
the bare-metal system.  So far I have done kernel compiles in a loop
as the test, but I plan to run LTP and possibly some other tests.

Comments welcome.

Paul.

 arch/powerpc/include/asm/book3s/64/hash-4k.h    |  5 ++-
 arch/powerpc/include/asm/book3s/64/hash-64k.h   | 24 ++++++-----
 arch/powerpc/include/asm/book3s/64/hash.h       | 54 ++++++++++++-------------
 arch/powerpc/include/asm/book3s/64/pgtable.h    |  6 +--
 arch/powerpc/include/asm/nohash/64/pgtable-4k.h |  2 +-
 arch/powerpc/include/asm/nohash/64/pgtable.h    | 10 ++---
 arch/powerpc/include/asm/pgalloc-64.h           | 16 ++++----
 arch/powerpc/mm/hash64_64k.c                    |  3 +-
 arch/powerpc/mm/hash_utils_64.c                 | 10 ++---
 arch/powerpc/mm/hugetlbpage-hash64.c            |  5 ++-
 arch/powerpc/mm/mmu_decl.h                      |  2 +-
 arch/powerpc/mm/pgtable_64.c                    |  4 +-
 12 files changed, 71 insertions(+), 70 deletions(-)

[RFC PATCH 1/9] powerpc/mm/book3s-64: Clean up some obsolete or misleading comments

From: Paul Mackerras <hidden>
Date: 2016-02-20 06:13:10 

No code changes.

Signed-off-by: Paul Mackerras <redacted>
---
 arch/powerpc/include/asm/book3s/64/hash.h | 13 ++++++-------
 arch/powerpc/mm/hash64_64k.c              |  3 +--
 arch/powerpc/mm/hash_utils_64.c           | 10 +++++-----
 3 files changed, 12 insertions(+), 14 deletions(-)

diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index 8d1c816..9a0a4ef 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -4,8 +4,7 @@
 
 /*
  * Common bits between 4K and 64K pages in a linux-style PTE.
- * These match the bits in the (hardware-defined) PowerPC PTE as closely
- * as possible. Additional bits may be defined in pgtable-hash64-*.h
+ * Additional bits may be defined in pgtable-hash64-*.h
  *
  * Note: We only support user read/write permissions. Supervisor always
  * have full read/write to pages above PAGE_OFFSET (pages below that
@@ -14,13 +13,13 @@
  * We could create separate kernel read-only if we used the 3 PP bits
  * combinations that newer processors provide but we currently don't.
  */
-#define _PAGE_PTE		0x00001
+#define _PAGE_PTE		0x00001	/* distinguishes PTEs from pointers */
 #define _PAGE_PRESENT		0x00002 /* software: pte contains a translation */
 #define _PAGE_BIT_SWAP_TYPE	2
-#define _PAGE_USER		0x00004 /* matches one of the PP bits */
-#define _PAGE_EXEC		0x00008 /* No execute on POWER4 and newer (we invert) */
-#define _PAGE_GUARDED		0x00010
-/* We can derive Memory coherence from _PAGE_NO_CACHE */
+#define _PAGE_USER		0x00004 /* page may be accessed by userspace */
+#define _PAGE_EXEC		0x00008 /* execute permission */
+#define _PAGE_GUARDED		0x00010 /* G: guarded (side-effect) page */
+/* M (memory coherence) is always set in the HPTE, so we don't need it here */
 #define _PAGE_COHERENT		0x0
 #define _PAGE_NO_CACHE		0x00020 /* I: cache inhibit */
 #define _PAGE_WRITETHRU		0x00040 /* W: cache write-through */
diff --git a/arch/powerpc/mm/hash64_64k.c b/arch/powerpc/mm/hash64_64k.c
index b389572..b2d659c 100644
--- a/arch/powerpc/mm/hash64_64k.c
+++ b/arch/powerpc/mm/hash64_64k.c
@@ -249,8 +249,7 @@ int __hash_page_64K(unsigned long ea, unsigned long access,
 			return 0;
 		/*
 		 * Try to lock the PTE, add ACCESSED and DIRTY if it was
-		 * a write access. Since this is 4K insert of 64K page size
-		 * also add _PAGE_COMBO
+		 * a write access.
 		 */
 		new_pte = old_pte | _PAGE_BUSY | _PAGE_ACCESSED;
 		if (access & _PAGE_RW)
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c
index ba59d59..47a0bc1 100644
--- a/arch/powerpc/mm/hash_utils_64.c
+++ b/arch/powerpc/mm/hash_utils_64.c
@@ -168,11 +168,11 @@ unsigned long htab_convert_pte_flags(unsigned long pteflags)
 		rflags |= HPTE_R_N;
 	/*
 	 * PP bits:
-	 * Linux use slb key 0 for kernel and 1 for user.
-	 * kernel areas are mapped by PP bits 00
-	 * and and there is no kernel RO (_PAGE_KERNEL_RO).
-	 * User area mapped by 0x2 and read only use by
-	 * 0x3.
+	 * Linux uses slb key 0 for kernel and 1 for user.
+	 * kernel areas are mapped with PP=00
+	 * and there is no kernel RO (_PAGE_KERNEL_RO).
+	 * User area is mapped with PP=0x2 for read/write
+	 * or PP=0x3 for read-only (including writeable but clean pages).
 	 */
 	if (pteflags & _PAGE_USER) {
 		rflags |= 0x2;
-- 
2.5.0

[RFC PATCH 2/9] powerpc/mm/book3s-64: Free up 7 high-order bits in the Linux PTE

From: Paul Mackerras <hidden>
Date: 2016-02-20 06:13:12 

This frees up bits 57-63 in the Linux PTE on 64-bit Book 3S machines.
In the 4k page case, this is done just by reducing the size of the
RPN field to 39 bits, giving 51-bit real addresses.  In the 64k page
case, we had 10 unused bits in the middle of the PTE, so this moves
the RPN field down 10 bits to make use of those unused bits.  This
means the RPN field is now 3 bits larger at 37 bits, giving 53-bit
real addresses in the normal case, or 49-bit real addresses for the
special 4k PFN case.

We are doing this in order to be able to move some other PTE bits
into the positions where PowerISA V3.0 processors will expect to
find them in radix-tree mode.  Ultimately we will be able to move
the RPN field to lower bit positions and make it larger.

Signed-off-by: Paul Mackerras <redacted>
---
 arch/powerpc/include/asm/book3s/64/hash-4k.h  |  1 +
 arch/powerpc/include/asm/book3s/64/hash-64k.h | 10 ++++++----
 arch/powerpc/include/asm/book3s/64/hash.h     |  6 +++---
 arch/powerpc/include/asm/book3s/64/pgtable.h  |  6 +++---
 arch/powerpc/mm/pgtable_64.c                  |  2 +-
 5 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h
index ea0414d..bee3643 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h
@@ -53,6 +53,7 @@
 
 /* shift to put page number into pte */
 #define PTE_RPN_SHIFT	(18)
+#define PTE_RPN_SIZE	(39)	/* gives 51-bit real addresses */
 
 #define _PAGE_4K_PFN		0
 #ifndef __ASSEMBLY__
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
index 849bbec..a8c4c2a 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
@@ -39,10 +39,12 @@
 
 /* Shift to put page number into pte.
  *
- * That gives us a max RPN of 34 bits, which means a max of 50 bits
- * of addressable physical space, or 46 bits for the special 4k PFNs.
+ * That gives us a max RPN of 37 bits, which means a max of 53 bits
+ * of addressable physical space, or 49 bits for the special 4k PFNs.
  */
-#define PTE_RPN_SHIFT	(30)
+#define PTE_RPN_SHIFT	(20)
+#define PTE_RPN_SIZE	(37)
+
 /*
  * we support 16 fragments per PTE page of 64K size.
  */
@@ -120,7 +122,7 @@ extern bool __rpte_sub_valid(real_pte_t rpte, unsigned long index);
 	(((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
 
 #define remap_4k_pfn(vma, addr, pfn, prot)				\
-	(WARN_ON(((pfn) >= (1UL << (64 - PTE_RPN_SHIFT)))) ? -EINVAL :	\
+	(WARN_ON(((pfn) >= (1UL << PTE_RPN_SIZE))) ? -EINVAL :	\
 		remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE,	\
 			__pgprot(pgprot_val((prot)) | _PAGE_4K_PFN)))
 
diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index 9a0a4ef..64eff40 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -131,7 +131,7 @@
  * The mask convered by the RPN must be a ULL on 32-bit platforms with
  * 64-bit PTEs
  */
-#define PTE_RPN_MASK	(~((1UL << PTE_RPN_SHIFT) - 1))
+#define PTE_RPN_MASK	(((1UL << PTE_RPN_SIZE) - 1) << PTE_RPN_SHIFT)
 /*
  * _PAGE_CHG_MASK masks of bits that are to be preserved across
  * pgprot changes
@@ -412,13 +412,13 @@ static inline int pte_present(pte_t pte)
  */
 static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
 {
-	return __pte(((pte_basic_t)(pfn) << PTE_RPN_SHIFT) |
+	return __pte((((pte_basic_t)(pfn) << PTE_RPN_SHIFT) & PTE_RPN_MASK) |
 		     pgprot_val(pgprot));
 }
 
 static inline unsigned long pte_pfn(pte_t pte)
 {
-	return pte_val(pte) >> PTE_RPN_SHIFT;
+	return (pte_val(pte) & PTE_RPN_MASK) >> PTE_RPN_SHIFT;
 }
 
 /* Generic modifiers for PTE bits */
diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h
index 8d1c41d..ab83892 100644
--- a/arch/powerpc/include/asm/book3s/64/pgtable.h
+++ b/arch/powerpc/include/asm/book3s/64/pgtable.h
@@ -154,10 +154,10 @@ static inline void pgd_set(pgd_t *pgdp, unsigned long val)
 #define SWP_TYPE_BITS 5
 #define __swp_type(x)		(((x).val >> _PAGE_BIT_SWAP_TYPE) \
 				& ((1UL << SWP_TYPE_BITS) - 1))
-#define __swp_offset(x)		((x).val >> PTE_RPN_SHIFT)
+#define __swp_offset(x)		(((x).val & PTE_RPN_MASK) >> PTE_RPN_SHIFT)
 #define __swp_entry(type, offset)	((swp_entry_t) { \
-					((type) << _PAGE_BIT_SWAP_TYPE) \
-					| ((offset) << PTE_RPN_SHIFT) })
+				((type) << _PAGE_BIT_SWAP_TYPE) \
+				| (((offset) << PTE_RPN_SHIFT) & PTE_RPN_MASK)})
 /*
  * swp_entry_t must be independent of pte bits. We build a swp_entry_t from
  * swap type and offset we get from swap and convert that to pte to find a
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 3124a20..950c572 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -717,7 +717,7 @@ pmd_t pfn_pmd(unsigned long pfn, pgprot_t pgprot)
 {
 	unsigned long pmdv;
 
-	pmdv = pfn << PTE_RPN_SHIFT;
+	pmdv = (pfn << PTE_RPN_SHIFT) & PTE_RPN_MASK;
 	return pmd_set_protbits(__pmd(pmdv), pgprot);
 }
 
-- 
2.5.0

Re: [RFC PATCH 2/9] powerpc/mm/book3s-64: Free up 7 high-order bits in the Linux PTE

From: Aneesh Kumar K.V <hidden>
Date: 2016-02-20 16:16:30 

Paul Mackerras [off-list ref] writes:

This frees up bits 57-63 in the Linux PTE on 64-bit Book 3S machines.
In the 4k page case, this is done just by reducing the size of the
RPN field to 39 bits, giving 51-bit real addresses.  In the 64k page
case, we had 10 unused bits in the middle of the PTE, so this moves
the RPN field down 10 bits to make use of those unused bits.  This
means the RPN field is now 3 bits larger at 37 bits, giving 53-bit
real addresses in the normal case, or 49-bit real addresses for the
special 4k PFN case.

Is it ok to have different real address bits between 4k and 64k linux
config ?

-aneesh

Re: [RFC PATCH 2/9] powerpc/mm/book3s-64: Free up 7 high-order bits in the Linux PTE

From: Paul Mackerras <hidden>
Date: 2016-02-21 22:46:13 

On Sat, Feb 20, 2016 at 09:46:19PM +0530, Aneesh Kumar K.V wrote:
Paul Mackerras [off-list ref] writes:
quoted
This frees up bits 57-63 in the Linux PTE on 64-bit Book 3S machines.
In the 4k page case, this is done just by reducing the size of the
RPN field to 39 bits, giving 51-bit real addresses.  In the 64k page
case, we had 10 unused bits in the middle of the PTE, so this moves
the RPN field down 10 bits to make use of those unused bits.  This
means the RPN field is now 3 bits larger at 37 bits, giving 53-bit
real addresses in the normal case, or 49-bit real addresses for the
special 4k PFN case.

Is it ok to have different real address bits between 4k and 64k linux
config ?
Do you mean a different number of address bits, or a different
location?  In fact both were different before this patch anyway.

Paul.

[RFC PATCH 3/9] powerpc/mm/64: Use physical addresses in upper page table tree levels

From: Paul Mackerras <hidden>
Date: 2016-02-20 06:13:14 

This changes the Linux page tables to store physical addresses
rather than kernel virtual addresses in the upper levels of the
tree (pgd, pud and pmd) for all 64-bit machines.

This frees up some high order bits, and will be needed with book3s
PowerISA v3.0 machines which read the page table tree in hardware
in radix mode.

Signed-off-by: Paul Mackerras <redacted>
---
 arch/powerpc/include/asm/book3s/64/hash-4k.h    |  2 +-
 arch/powerpc/include/asm/book3s/64/hash.h       | 10 ++++------
 arch/powerpc/include/asm/nohash/64/pgtable-4k.h |  2 +-
 arch/powerpc/include/asm/nohash/64/pgtable.h    | 10 ++++------
 arch/powerpc/include/asm/pgalloc-64.h           | 16 ++++++++--------
 5 files changed, 18 insertions(+), 22 deletions(-)

diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h
index bee3643..0425d3e 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h
@@ -64,7 +64,7 @@
 #define pgd_none(pgd)		(!pgd_val(pgd))
 #define pgd_bad(pgd)		(pgd_val(pgd) == 0)
 #define pgd_present(pgd)	(pgd_val(pgd) != 0)
-#define pgd_page_vaddr(pgd)	(pgd_val(pgd) & ~PGD_MASKED_BITS)
+#define pgd_page_vaddr(pgd)	__va(pgd_val(pgd) & ~PGD_MASKED_BITS)
 
 static inline void pgd_clear(pgd_t *pgdp)
 {
diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index 64eff40..fcab33f 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -222,13 +222,11 @@
 #define PUD_BAD_BITS		(PMD_TABLE_SIZE-1)
 
 #ifndef __ASSEMBLY__
-#define	pmd_bad(pmd)		(!is_kernel_addr(pmd_val(pmd)) \
-				 || (pmd_val(pmd) & PMD_BAD_BITS))
-#define pmd_page_vaddr(pmd)	(pmd_val(pmd) & ~PMD_MASKED_BITS)
+#define	pmd_bad(pmd)		(pmd_val(pmd) & PMD_BAD_BITS)
+#define pmd_page_vaddr(pmd)	__va(pmd_val(pmd) & ~PMD_MASKED_BITS)
 
-#define	pud_bad(pud)		(!is_kernel_addr(pud_val(pud)) \
-				 || (pud_val(pud) & PUD_BAD_BITS))
-#define pud_page_vaddr(pud)	(pud_val(pud) & ~PUD_MASKED_BITS)
+#define	pud_bad(pud)		(pud_val(pud) & PUD_BAD_BITS)
+#define pud_page_vaddr(pud)	__va(pud_val(pud) & ~PUD_MASKED_BITS)
 
 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
diff --git a/arch/powerpc/include/asm/nohash/64/pgtable-4k.h b/arch/powerpc/include/asm/nohash/64/pgtable-4k.h
index fc7d517..c8319e8 100644
--- a/arch/powerpc/include/asm/nohash/64/pgtable-4k.h
+++ b/arch/powerpc/include/asm/nohash/64/pgtable-4k.h
@@ -55,7 +55,7 @@
 #define pgd_none(pgd)		(!pgd_val(pgd))
 #define pgd_bad(pgd)		(pgd_val(pgd) == 0)
 #define pgd_present(pgd)	(pgd_val(pgd) != 0)
-#define pgd_page_vaddr(pgd)	(pgd_val(pgd) & ~PGD_MASKED_BITS)
+#define pgd_page_vaddr(pgd)	__va(pgd_val(pgd) & ~PGD_MASKED_BITS)
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h b/arch/powerpc/include/asm/nohash/64/pgtable.h
index b9f734d..484c0e1 100644
--- a/arch/powerpc/include/asm/nohash/64/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/64/pgtable.h
@@ -127,10 +127,9 @@ static inline pte_t pmd_pte(pmd_t pmd)
 }
 
 #define pmd_none(pmd)		(!pmd_val(pmd))
-#define	pmd_bad(pmd)		(!is_kernel_addr(pmd_val(pmd)) \
-				 || (pmd_val(pmd) & PMD_BAD_BITS))
+#define	pmd_bad(pmd)		(pmd_val(pmd) & PMD_BAD_BITS)
 #define	pmd_present(pmd)	(!pmd_none(pmd))
-#define pmd_page_vaddr(pmd)	(pmd_val(pmd) & ~PMD_MASKED_BITS)
+#define pmd_page_vaddr(pmd)	__va(pmd_val(pmd) & ~PMD_MASKED_BITS)
 extern struct page *pmd_page(pmd_t pmd);
 
 static inline void pud_set(pud_t *pudp, unsigned long val)
@@ -144,10 +143,9 @@ static inline void pud_clear(pud_t *pudp)
 }
 
 #define pud_none(pud)		(!pud_val(pud))
-#define	pud_bad(pud)		(!is_kernel_addr(pud_val(pud)) \
-				 || (pud_val(pud) & PUD_BAD_BITS))
+#define	pud_bad(pud)		(pud_val(pud) & PUD_BAD_BITS)
 #define pud_present(pud)	(pud_val(pud) != 0)
-#define pud_page_vaddr(pud)	(pud_val(pud) & ~PUD_MASKED_BITS)
+#define pud_page_vaddr(pud)	__va(pud_val(pud) & ~PUD_MASKED_BITS)
 
 extern struct page *pud_page(pud_t pud);
 
diff --git a/arch/powerpc/include/asm/pgalloc-64.h b/arch/powerpc/include/asm/pgalloc-64.h
index 69ef28a..4f4609d 100644
--- a/arch/powerpc/include/asm/pgalloc-64.h
+++ b/arch/powerpc/include/asm/pgalloc-64.h
@@ -53,7 +53,7 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
 
 #ifndef CONFIG_PPC_64K_PAGES
 
-#define pgd_populate(MM, PGD, PUD)	pgd_set(PGD, (unsigned long)PUD)
+#define pgd_populate(MM, PGD, PUD)	pgd_set(PGD, __pa(PUD))
 
 static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
@@ -68,19 +68,19 @@ static inline void pud_free(struct mm_struct *mm, pud_t *pud)
 
 static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
 {
-	pud_set(pud, (unsigned long)pmd);
+	pud_set(pud, __pa(pmd));
 }
 
 static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
 				       pte_t *pte)
 {
-	pmd_set(pmd, (unsigned long)pte);
+	pmd_set(pmd, __pa(pte));
 }
 
 static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
 				pgtable_t pte_page)
 {
-	pmd_set(pmd, (unsigned long)page_address(pte_page));
+	pmd_set(pmd, __pa(page_address(pte_page)));
 }
 
 #define pmd_pgtable(pmd) pmd_page(pmd)
@@ -171,23 +171,23 @@ extern void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int shift);
 extern void __tlb_remove_table(void *_table);
 #endif
 
-#define pud_populate(mm, pud, pmd)	pud_set(pud, (unsigned long)pmd)
+#define pud_populate(mm, pud, pmd)	pud_set(pud, __pa(pmd))
 
 static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
 				       pte_t *pte)
 {
-	pmd_set(pmd, (unsigned long)pte);
+	pmd_set(pmd, __pa(pte));
 }
 
 static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
 				pgtable_t pte_page)
 {
-	pmd_set(pmd, (unsigned long)pte_page);
+	pmd_set(pmd, __pa(pte_page));
 }
 
 static inline pgtable_t pmd_pgtable(pmd_t pmd)
 {
-	return (pgtable_t)(pmd_val(pmd) & ~PMD_MASKED_BITS);
+	return (pgtable_t)__va(pmd_val(pmd) & ~PMD_MASKED_BITS);
 }
 
 static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
-- 
2.5.0

Re: [RFC PATCH 3/9] powerpc/mm/64: Use physical addresses in upper page table tree levels

From: Aneesh Kumar K.V <hidden>
Date: 2016-02-20 16:36:08 

Paul Mackerras [off-list ref] writes:

This changes the Linux page tables to store physical addresses
rather than kernel virtual addresses in the upper levels of the
tree (pgd, pud and pmd) for all 64-bit machines.

This frees up some high order bits, and will be needed with book3s
PowerISA v3.0 machines which read the page table tree in hardware
in radix mode.

Should we not update pmd_pgtable ? I have the below patch in my series.

http://mid.gmane.org/1455814254-10226-13-git-send-email-aneesh.kumar@linux.vnet.ibm.com
quoted hunk
Signed-off-by: Paul Mackerras <redacted>
---
 arch/powerpc/include/asm/book3s/64/hash-4k.h    |  2 +-
 arch/powerpc/include/asm/book3s/64/hash.h       | 10 ++++------
 arch/powerpc/include/asm/nohash/64/pgtable-4k.h |  2 +-
 arch/powerpc/include/asm/nohash/64/pgtable.h    | 10 ++++------
 arch/powerpc/include/asm/pgalloc-64.h           | 16 ++++++++--------
 5 files changed, 18 insertions(+), 22 deletions(-)

diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h
index bee3643..0425d3e 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h
@@ -64,7 +64,7 @@
 #define pgd_none(pgd)		(!pgd_val(pgd))
 #define pgd_bad(pgd)		(pgd_val(pgd) == 0)
 #define pgd_present(pgd)	(pgd_val(pgd) != 0)
-#define pgd_page_vaddr(pgd)	(pgd_val(pgd) & ~PGD_MASKED_BITS)
+#define pgd_page_vaddr(pgd)	__va(pgd_val(pgd) & ~PGD_MASKED_BITS)

 static inline void pgd_clear(pgd_t *pgdp)
 {
diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index 64eff40..fcab33f 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -222,13 +222,11 @@
 #define PUD_BAD_BITS		(PMD_TABLE_SIZE-1)

 #ifndef __ASSEMBLY__
-#define	pmd_bad(pmd)		(!is_kernel_addr(pmd_val(pmd)) \
-				 || (pmd_val(pmd) & PMD_BAD_BITS))
-#define pmd_page_vaddr(pmd)	(pmd_val(pmd) & ~PMD_MASKED_BITS)
+#define	pmd_bad(pmd)		(pmd_val(pmd) & PMD_BAD_BITS)
+#define pmd_page_vaddr(pmd)	__va(pmd_val(pmd) & ~PMD_MASKED_BITS)

-#define	pud_bad(pud)		(!is_kernel_addr(pud_val(pud)) \
-				 || (pud_val(pud) & PUD_BAD_BITS))
-#define pud_page_vaddr(pud)	(pud_val(pud) & ~PUD_MASKED_BITS)
+#define	pud_bad(pud)		(pud_val(pud) & PUD_BAD_BITS)
+#define pud_page_vaddr(pud)	__va(pud_val(pud) & ~PUD_MASKED_BITS)

 #define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & (PTRS_PER_PGD - 1))
 #define pmd_index(address) (((address) >> (PMD_SHIFT)) & (PTRS_PER_PMD - 1))
diff --git a/arch/powerpc/include/asm/nohash/64/pgtable-4k.h b/arch/powerpc/include/asm/nohash/64/pgtable-4k.h
index fc7d517..c8319e8 100644
--- a/arch/powerpc/include/asm/nohash/64/pgtable-4k.h
+++ b/arch/powerpc/include/asm/nohash/64/pgtable-4k.h
@@ -55,7 +55,7 @@
 #define pgd_none(pgd)		(!pgd_val(pgd))
 #define pgd_bad(pgd)		(pgd_val(pgd) == 0)
 #define pgd_present(pgd)	(pgd_val(pgd) != 0)
-#define pgd_page_vaddr(pgd)	(pgd_val(pgd) & ~PGD_MASKED_BITS)
+#define pgd_page_vaddr(pgd)	__va(pgd_val(pgd) & ~PGD_MASKED_BITS)

 #ifndef __ASSEMBLY__

diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h b/arch/powerpc/include/asm/nohash/64/pgtable.h
index b9f734d..484c0e1 100644
--- a/arch/powerpc/include/asm/nohash/64/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/64/pgtable.h
@@ -127,10 +127,9 @@ static inline pte_t pmd_pte(pmd_t pmd)
 }

 #define pmd_none(pmd)		(!pmd_val(pmd))
-#define	pmd_bad(pmd)		(!is_kernel_addr(pmd_val(pmd)) \
-				 || (pmd_val(pmd) & PMD_BAD_BITS))
+#define	pmd_bad(pmd)		(pmd_val(pmd) & PMD_BAD_BITS)
 #define	pmd_present(pmd)	(!pmd_none(pmd))
-#define pmd_page_vaddr(pmd)	(pmd_val(pmd) & ~PMD_MASKED_BITS)
+#define pmd_page_vaddr(pmd)	__va(pmd_val(pmd) & ~PMD_MASKED_BITS)
 extern struct page *pmd_page(pmd_t pmd);

 static inline void pud_set(pud_t *pudp, unsigned long val)
@@ -144,10 +143,9 @@ static inline void pud_clear(pud_t *pudp)
 }

 #define pud_none(pud)		(!pud_val(pud))
-#define	pud_bad(pud)		(!is_kernel_addr(pud_val(pud)) \
-				 || (pud_val(pud) & PUD_BAD_BITS))
+#define	pud_bad(pud)		(pud_val(pud) & PUD_BAD_BITS)
 #define pud_present(pud)	(pud_val(pud) != 0)
-#define pud_page_vaddr(pud)	(pud_val(pud) & ~PUD_MASKED_BITS)
+#define pud_page_vaddr(pud)	__va(pud_val(pud) & ~PUD_MASKED_BITS)

 extern struct page *pud_page(pud_t pud);

diff --git a/arch/powerpc/include/asm/pgalloc-64.h b/arch/powerpc/include/asm/pgalloc-64.h
index 69ef28a..4f4609d 100644
--- a/arch/powerpc/include/asm/pgalloc-64.h
+++ b/arch/powerpc/include/asm/pgalloc-64.h
@@ -53,7 +53,7 @@ static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)

 #ifndef CONFIG_PPC_64K_PAGES

-#define pgd_populate(MM, PGD, PUD)	pgd_set(PGD, (unsigned long)PUD)
+#define pgd_populate(MM, PGD, PUD)	pgd_set(PGD, __pa(PUD))

 static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
@@ -68,19 +68,19 @@ static inline void pud_free(struct mm_struct *mm, pud_t *pud)

 static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
 {
-	pud_set(pud, (unsigned long)pmd);
+	pud_set(pud, __pa(pmd));
 }

 static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
 				       pte_t *pte)
 {
-	pmd_set(pmd, (unsigned long)pte);
+	pmd_set(pmd, __pa(pte));
 }

 static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
 				pgtable_t pte_page)
 {
-	pmd_set(pmd, (unsigned long)page_address(pte_page));
+	pmd_set(pmd, __pa(page_address(pte_page)));
 }

 #define pmd_pgtable(pmd) pmd_page(pmd)
@@ -171,23 +171,23 @@ extern void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int shift);
 extern void __tlb_remove_table(void *_table);
 #endif

-#define pud_populate(mm, pud, pmd)	pud_set(pud, (unsigned long)pmd)
+#define pud_populate(mm, pud, pmd)	pud_set(pud, __pa(pmd))

 static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
 				       pte_t *pte)
 {
-	pmd_set(pmd, (unsigned long)pte);
+	pmd_set(pmd, __pa(pte));
 }

 static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
 				pgtable_t pte_page)
 {
-	pmd_set(pmd, (unsigned long)pte_page);
+	pmd_set(pmd, __pa(pte_page));
 }

 static inline pgtable_t pmd_pgtable(pmd_t pmd)
 {
-	return (pgtable_t)(pmd_val(pmd) & ~PMD_MASKED_BITS);
+	return (pgtable_t)__va(pmd_val(pmd) & ~PMD_MASKED_BITS);
 }

 static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
-- 
2.5.0

Re: [RFC PATCH 3/9] powerpc/mm/64: Use physical addresses in upper page table tree levels

From: Paul Mackerras <hidden>
Date: 2016-02-21 22:46:13 

On Sat, Feb 20, 2016 at 10:05:58PM +0530, Aneesh Kumar K.V wrote:
Paul Mackerras [off-list ref] writes:
quoted
This changes the Linux page tables to store physical addresses
rather than kernel virtual addresses in the upper levels of the
tree (pgd, pud and pmd) for all 64-bit machines.

This frees up some high order bits, and will be needed with book3s
PowerISA v3.0 machines which read the page table tree in hardware
in radix mode.

Should we not update pmd_pgtable ?
Not sure what you mean by this - the patch does update pmd_pgtable
for the 64k page case (the 4k case is already fine).

I have the below patch in my series.

http://mid.gmane.org/1455814254-10226-13-git-send-email-aneesh.kumar@linux.vnet.ibm.com
That looks like a reasonable thing to do.

Paul.

[RFC PATCH 4/9] powerpc/mm/book3s-64: Move _PAGE_PRESENT to the most significant bit

From: Paul Mackerras <hidden>
Date: 2016-02-20 06:13:14 

This changes _PAGE_PRESENT for 64-bit Book 3S processors from 0x2 to
0x8000_0000_0000_0000, because that is where PowerISA v3.0 CPUs in
radix mode will expect to find it.

Signed-off-by: Paul Mackerras <redacted>
---
 arch/powerpc/include/asm/book3s/64/hash-64k.h | 10 +++++-----
 arch/powerpc/include/asm/book3s/64/hash.h     |  5 +++--
 arch/powerpc/mm/mmu_decl.h                    |  2 +-
 arch/powerpc/mm/pgtable_64.c                  |  2 +-
 4 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
index a8c4c2a..ed390e1 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
@@ -210,30 +210,30 @@ static inline char *get_hpte_slot_array(pmd_t *pmdp)
 /*
  * The linux hugepage PMD now include the pmd entries followed by the address
  * to the stashed pgtable_t. The stashed pgtable_t contains the hpte bits.
- * [ 1 bit secondary | 3 bit hidx | 1 bit valid | 000]. We use one byte per
+ * [ 000 | 1 bit secondary | 3 bit hidx | 1 bit valid]. We use one byte per
  * each HPTE entry. With 16MB hugepage and 64K HPTE we need 256 entries and
  * with 4K HPTE we need 4096 entries. Both will fit in a 4K pgtable_t.
  *
- * The last three bits are intentionally left to zero. This memory location
+ * The top three bits are intentionally left as zero. This memory location
  * are also used as normal page PTE pointers. So if we have any pointers
  * left around while we collapse a hugepage, we need to make sure
  * _PAGE_PRESENT bit of that is zero when we look at them
  */
 static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index)
 {
-	return (hpte_slot_array[index] >> 3) & 0x1;
+	return hpte_slot_array[index] & 0x1;
 }
 
 static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array,
 					   int index)
 {
-	return hpte_slot_array[index] >> 4;
+	return hpte_slot_array[index] >> 1;
 }
 
 static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array,
 					unsigned int index, unsigned int hidx)
 {
-	hpte_slot_array[index] = hidx << 4 | 0x1 << 3;
+	hpte_slot_array[index] = (hidx << 1) | 0x1;
 }
 
 /*
diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index fcab33f..72ea557 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -14,7 +14,6 @@
  * combinations that newer processors provide but we currently don't.
  */
 #define _PAGE_PTE		0x00001	/* distinguishes PTEs from pointers */
-#define _PAGE_PRESENT		0x00002 /* software: pte contains a translation */
 #define _PAGE_BIT_SWAP_TYPE	2
 #define _PAGE_USER		0x00004 /* page may be accessed by userspace */
 #define _PAGE_EXEC		0x00008 /* execute permission */
@@ -39,6 +38,8 @@
 #define _PAGE_SOFT_DIRTY	0x00000
 #endif
 
+#define _PAGE_PRESENT		(1ul << 63)	/* pte contains a translation */
+
 /*
  * We need to differentiate between explicit huge page and THP huge
  * page, since THP huge page also need to track real subpage details
@@ -399,7 +400,7 @@ static inline int pte_protnone(pte_t pte)
 
 static inline int pte_present(pte_t pte)
 {
-	return pte_val(pte) & _PAGE_PRESENT;
+	return !!(pte_val(pte) & _PAGE_PRESENT);
 }
 
 /* Conversion functions: convert a page and protection to a page entry,
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index 9f58ff4..92da107 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -110,7 +110,7 @@ extern unsigned long Hash_size, Hash_mask;
 #endif /* CONFIG_PPC32 */
 
 #ifdef CONFIG_PPC64
-extern int map_kernel_page(unsigned long ea, unsigned long pa, int flags);
+extern int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t flags);
 #endif /* CONFIG_PPC64 */
 
 extern unsigned long ioremap_bot;
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 950c572..c50d9a2 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -88,7 +88,7 @@ static __ref void *early_alloc_pgtable(unsigned long size)
  * map_kernel_page adds an entry to the ioremap page table
  * and adds an entry to the HPT, possibly bolting it
  */
-int map_kernel_page(unsigned long ea, unsigned long pa, int flags)
+int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t flags)
 {
 	pgd_t *pgdp;
 	pud_t *pudp;
-- 
2.5.0

Re: [RFC PATCH 4/9] powerpc/mm/book3s-64: Move _PAGE_PRESENT to the most significant bit

From: kbuild test robot <hidden>
Date: 2016-02-20 08:34:42 

Hi Paul,

[auto build test ERROR on powerpc/next]
[also build test ERROR on v4.5-rc4 next-20160219]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]

url:    https://github.com/0day-ci/linux/commits/Paul-Mackerras-via-Linuxppc-dev/powerpc-mm-Restructure-Linux-PTE-on-Book3S-64-to-radix-format/20160220-143050
base:   https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git next
config: powerpc-allmodconfig (attached as .config)
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=powerpc 

All error/warnings (new ones prefixed by >>):

   In file included from arch/powerpc/include/asm/thread_info.h:34:0,
                    from include/linux/thread_info.h:54,
                    from include/asm-generic/preempt.h:4,
                    from arch/powerpc/include/generated/asm/preempt.h:1,
                    from include/linux/preempt.h:59,
                    from include/linux/spinlock.h:50,
                    from include/linux/seqlock.h:35,
                    from include/linux/time.h:5,
                    from include/uapi/linux/timex.h:56,
                    from include/linux/timex.h:56,
                    from include/linux/sched.h:19,
                    from arch/powerpc/mm/pgtable_64.c:25:
   arch/powerpc/mm/pgtable_64.c: In function 'map_kernel_page':
quoted
arch/powerpc/include/asm/page.h:335:35: error: incompatible types when initializing type 'long unsigned int' using type 'pgprot_t {aka struct <anonymous>}'
    #define __pgprot(x) ((pgprot_t) { (x) })
                                      ^
quoted
arch/powerpc/mm/pgtable_64.c:110:10: note: in expansion of macro '__pgprot'
             __pgprot(flags)));
             ^
quoted
arch/powerpc/mm/pgtable_64.c:143:49: error: incompatible type for argument 4 of 'htab_bolt_mapping'
      if (htab_bolt_mapping(ea, ea + PAGE_SIZE, pa, flags,
                                                    ^
   In file included from arch/powerpc/include/asm/mmu.h:185:0,
                    from arch/powerpc/include/asm/lppaca.h:36,
                    from arch/powerpc/include/asm/paca.h:21,
                    from arch/powerpc/include/asm/hw_irq.h:42,
                    from arch/powerpc/include/asm/irqflags.h:11,
                    from include/linux/irqflags.h:15,
                    from include/linux/spinlock.h:53,
                    from include/linux/seqlock.h:35,
                    from include/linux/time.h:5,
                    from include/uapi/linux/timex.h:56,
                    from include/linux/timex.h:56,
                    from include/linux/sched.h:19,
                    from arch/powerpc/mm/pgtable_64.c:25:
   arch/powerpc/include/asm/mmu-hash64.h:358:12: note: expected 'long unsigned int' but argument is of type 'pgprot_t {aka struct <anonymous>}'
    extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
               ^
   arch/powerpc/mm/pgtable_64.c: In function '__ioremap_at':
quoted
arch/powerpc/mm/pgtable_64.c:183:50: error: incompatible type for argument 3 of 'map_kernel_page'
      if (map_kernel_page((unsigned long)ea+i, pa+i, flags))
                                                     ^
   arch/powerpc/mm/pgtable_64.c:91:5: note: expected 'pgprot_t {aka struct <anonymous>}' but argument is of type 'long unsigned int'
    int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t flags)
        ^

vim +/htab_bolt_mapping +143 arch/powerpc/mm/pgtable_64.c

14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   19   *  as published by the Free Software Foundation; either version
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   20   *  2 of the License, or (at your option) any later version.
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   21   *
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   22   */
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   23  
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   24  #include <linux/signal.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  @25  #include <linux/sched.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   26  #include <linux/kernel.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   27  #include <linux/errno.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   28  #include <linux/string.h>
66b15db6 arch/powerpc/mm/pgtable_64.c Paul Gortmaker                  2011-05-27   29  #include <linux/export.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   30  #include <linux/types.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   31  #include <linux/mman.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   32  #include <linux/mm.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   33  #include <linux/swap.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   34  #include <linux/stddef.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   35  #include <linux/vmalloc.h>
95f72d1e arch/powerpc/mm/pgtable_64.c Yinghai Lu                      2010-07-12   36  #include <linux/memblock.h>
5a0e3ad6 arch/powerpc/mm/pgtable_64.c Tejun Heo                       2010-03-24   37  #include <linux/slab.h>
06743521 arch/powerpc/mm/pgtable_64.c Aneesh Kumar K.V                2014-11-05   38  #include <linux/hugetlb.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   39  
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   40  #include <asm/pgalloc.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   41  #include <asm/page.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   42  #include <asm/prom.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   43  #include <asm/io.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   44  #include <asm/mmu_context.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   45  #include <asm/pgtable.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   46  #include <asm/mmu.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   47  #include <asm/smp.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   48  #include <asm/machdep.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   49  #include <asm/tlb.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   50  #include <asm/processor.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   51  #include <asm/cputable.h>
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   52  #include <asm/sections.h>
5e203d68 arch/powerpc/mm/pgtable_64.c Stephen Rothwell                2006-09-25   53  #include <asm/firmware.h>
68cf0d64 arch/powerpc/mm/pgtable_64.c Anton Blanchard                 2014-09-17   54  #include <asm/dma.h>
800fc3ee arch/powerpc/mm/pgtable_64.c David Gibson                    2005-11-16   55  
800fc3ee arch/powerpc/mm/pgtable_64.c David Gibson                    2005-11-16   56  #include "mmu_decl.h"
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   57  
9e813308 arch/powerpc/mm/pgtable_64.c Aneesh Kumar K.V                2014-08-13   58  #define CREATE_TRACE_POINTS
9e813308 arch/powerpc/mm/pgtable_64.c Aneesh Kumar K.V                2014-08-13   59  #include <trace/events/thp.h>
9e813308 arch/powerpc/mm/pgtable_64.c Aneesh Kumar K.V                2014-08-13   60  
78f1dbde arch/powerpc/mm/pgtable_64.c Aneesh Kumar K.V                2012-09-10   61  /* Some sanity checking */
78f1dbde arch/powerpc/mm/pgtable_64.c Aneesh Kumar K.V                2012-09-10   62  #if TASK_SIZE_USER64 > PGTABLE_RANGE
78f1dbde arch/powerpc/mm/pgtable_64.c Aneesh Kumar K.V                2012-09-10   63  #error TASK_SIZE_USER64 exceeds pagetable range
78f1dbde arch/powerpc/mm/pgtable_64.c Aneesh Kumar K.V                2012-09-10   64  #endif
78f1dbde arch/powerpc/mm/pgtable_64.c Aneesh Kumar K.V                2012-09-10   65  
78f1dbde arch/powerpc/mm/pgtable_64.c Aneesh Kumar K.V                2012-09-10   66  #ifdef CONFIG_PPC_STD_MMU_64
af81d787 arch/powerpc/mm/pgtable_64.c Aneesh Kumar K.V                2013-03-13   67  #if TASK_SIZE_USER64 > (1UL << (ESID_BITS + SID_SHIFT))
78f1dbde arch/powerpc/mm/pgtable_64.c Aneesh Kumar K.V                2012-09-10   68  #error TASK_SIZE_USER64 exceeds user VSID range
78f1dbde arch/powerpc/mm/pgtable_64.c Aneesh Kumar K.V                2012-09-10   69  #endif
78f1dbde arch/powerpc/mm/pgtable_64.c Aneesh Kumar K.V                2012-09-10   70  #endif
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   71  
78f1dbde arch/powerpc/mm/pgtable_64.c Aneesh Kumar K.V                2012-09-10   72  unsigned long ioremap_bot = IOREMAP_BASE;
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23   73  
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23   74  #ifdef CONFIG_PPC_MMU_NOHASH
7d176221 arch/powerpc/mm/pgtable_64.c Scott Wood                      2014-08-01   75  static __ref void *early_alloc_pgtable(unsigned long size)
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23   76  {
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23   77  	void *pt;
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23   78  
10239733 arch/powerpc/mm/pgtable_64.c Anton Blanchard                 2014-09-17   79  	pt = __va(memblock_alloc_base(size, size, __pa(MAX_DMA_ADDRESS)));
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23   80  	memset(pt, 0, size);
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23   81  
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23   82  	return pt;
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23   83  }
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23   84  #endif /* CONFIG_PPC_MMU_NOHASH */
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23   85  
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   86  /*
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23   87   * map_kernel_page currently only called by __ioremap
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23   88   * map_kernel_page adds an entry to the ioremap page table
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   89   * and adds an entry to the HPT, possibly bolting it
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   90   */
be212f32 arch/powerpc/mm/pgtable_64.c Paul Mackerras via Linuxppc-dev 2016-02-20   91  int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t flags)
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   92  {
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   93  	pgd_t *pgdp;
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   94  	pud_t *pudp;
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   95  	pmd_t *pmdp;
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   96  	pte_t *ptep;
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   97  
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23   98  	if (slab_is_available()) {
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26   99  		pgdp = pgd_offset_k(ea);
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  100  		pudp = pud_alloc(&init_mm, pgdp, ea);
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  101  		if (!pudp)
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  102  			return -ENOMEM;
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  103  		pmdp = pmd_alloc(&init_mm, pudp, ea);
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  104  		if (!pmdp)
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  105  			return -ENOMEM;
23fd0775 arch/powerpc/mm/pgtable_64.c Paul Mackerras                  2005-10-31  106  		ptep = pte_alloc_kernel(pmdp, ea);
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  107  		if (!ptep)
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  108  			return -ENOMEM;
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  109  		set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT,
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26 @110  							  __pgprot(flags)));
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  111  	} else {
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  112  #ifdef CONFIG_PPC_MMU_NOHASH
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  113  		pgdp = pgd_offset_k(ea);
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  114  #ifdef PUD_TABLE_SIZE
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  115  		if (pgd_none(*pgdp)) {
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  116  			pudp = early_alloc_pgtable(PUD_TABLE_SIZE);
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  117  			BUG_ON(pudp == NULL);
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  118  			pgd_populate(&init_mm, pgdp, pudp);
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  119  		}
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  120  #endif /* PUD_TABLE_SIZE */
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  121  		pudp = pud_offset(pgdp, ea);
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  122  		if (pud_none(*pudp)) {
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  123  			pmdp = early_alloc_pgtable(PMD_TABLE_SIZE);
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  124  			BUG_ON(pmdp == NULL);
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  125  			pud_populate(&init_mm, pudp, pmdp);
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  126  		}
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  127  		pmdp = pmd_offset(pudp, ea);
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  128  		if (!pmd_present(*pmdp)) {
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  129  			ptep = early_alloc_pgtable(PAGE_SIZE);
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  130  			BUG_ON(ptep == NULL);
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  131  			pmd_populate_kernel(&init_mm, pmdp, ptep);
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  132  		}
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  133  		ptep = pte_offset_kernel(pmdp, ea);
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  134  		set_pte_at(&init_mm, ea, ptep, pfn_pte(pa >> PAGE_SHIFT,
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  135  							  __pgprot(flags)));
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  136  #else /* CONFIG_PPC_MMU_NOHASH */
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  137  		/*
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  138  		 * If the mm subsystem is not fully up, we cannot create a
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  139  		 * linux page table entry for this mapping.  Simply bolt an
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  140  		 * entry in the hardware page table.
3c726f8d arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2005-11-07  141  		 *
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  142  		 */
1189be65 arch/powerpc/mm/pgtable_64.c Paul Mackerras                  2007-10-11 @143  		if (htab_bolt_mapping(ea, ea + PAGE_SIZE, pa, flags,
1189be65 arch/powerpc/mm/pgtable_64.c Paul Mackerras                  2007-10-11  144  				      mmu_io_psize, mmu_kernel_ssize)) {
77ac166f arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2005-11-10  145  			printk(KERN_ERR "Failed to do bolted mapping IO "
77ac166f arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2005-11-10  146  			       "memory at %016lx !\n", pa);
77ac166f arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2005-11-10  147  			return -ENOMEM;
77ac166f arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2005-11-10  148  		}
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23  149  #endif /* !CONFIG_PPC_MMU_NOHASH */
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  150  	}
47ce8af4 arch/powerpc/mm/pgtable_64.c Scott Wood                      2013-10-11  151  
47ce8af4 arch/powerpc/mm/pgtable_64.c Scott Wood                      2013-10-11  152  	smp_wmb();
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  153  	return 0;
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  154  }
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  155  
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  156  
3d5134ee arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2007-06-04  157  /**
3d5134ee arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2007-06-04  158   * __ioremap_at - Low level function to establish the page tables
3d5134ee arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2007-06-04  159   *                for an IO mapping
3d5134ee arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2007-06-04  160   */
3d5134ee arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2007-06-04  161  void __iomem * __ioremap_at(phys_addr_t pa, void *ea, unsigned long size,
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  162  			    unsigned long flags)
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  163  {
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  164  	unsigned long i;
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  165  
a1f242ff arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2008-07-23  166  	/* Make sure we have the base flags */
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  167  	if ((flags & _PAGE_PRESENT) == 0)
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  168  		flags |= pgprot_val(PAGE_KERNEL);
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  169  
a1f242ff arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2008-07-23  170  	/* Non-cacheable page cannot be coherent */
a1f242ff arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2008-07-23  171  	if (flags & _PAGE_NO_CACHE)
a1f242ff arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2008-07-23  172  		flags &= ~_PAGE_COHERENT;
a1f242ff arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2008-07-23  173  
a1f242ff arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2008-07-23  174  	/* We don't support the 4K PFN hack with ioremap */
a1f242ff arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2008-07-23  175  	if (flags & _PAGE_4K_PFN)
a1f242ff arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2008-07-23  176  		return NULL;
a1f242ff arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2008-07-23  177  
3d5134ee arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2007-06-04  178  	WARN_ON(pa & ~PAGE_MASK);
3d5134ee arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2007-06-04  179  	WARN_ON(((unsigned long)ea) & ~PAGE_MASK);
3d5134ee arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2007-06-04  180  	WARN_ON(size & ~PAGE_MASK);
3d5134ee arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2007-06-04  181  
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  182  	for (i = 0; i < size; i += PAGE_SIZE)
a245067e arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2009-07-23 @183  		if (map_kernel_page((unsigned long)ea+i, pa+i, flags))
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  184  			return NULL;
14cf11af arch/powerpc/mm/pgtable64.c  Paul Mackerras                  2005-09-26  185  
3d5134ee arch/powerpc/mm/pgtable_64.c Benjamin Herrenschmidt          2007-06-04  186  	return (void __iomem *)ea;

:::::: The code at line 143 was first introduced by commit
:::::: 1189be6508d45183013ddb82b18f4934193de274 [POWERPC] Use 1TB segments

:::::: TO: Paul Mackerras [off-list ref]
:::::: CC: Paul Mackerras [off-list ref]

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

Re: [RFC PATCH 4/9] powerpc/mm/book3s-64: Move _PAGE_PRESENT to the most significant bit

From: Aneesh Kumar K.V <hidden>
Date: 2016-02-20 16:41:24 

Paul Mackerras [off-list ref] writes:

This changes _PAGE_PRESENT for 64-bit Book 3S processors from 0x2 to
0x8000_0000_0000_0000, because that is where PowerISA v3.0 CPUs in
radix mode will expect to find it.
All the changes in this patch related to _PAGE_PRESENT movement or are
they cleanup that got added to this patch. I am looking at the hpte slot
array changes and wondering how that is related to _PAGE_PRESENT.
quoted hunk
Signed-off-by: Paul Mackerras <redacted>
---
 arch/powerpc/include/asm/book3s/64/hash-64k.h | 10 +++++-----
 arch/powerpc/include/asm/book3s/64/hash.h     |  5 +++--
 arch/powerpc/mm/mmu_decl.h                    |  2 +-
 arch/powerpc/mm/pgtable_64.c                  |  2 +-
 4 files changed, 10 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
index a8c4c2a..ed390e1 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
@@ -210,30 +210,30 @@ static inline char *get_hpte_slot_array(pmd_t *pmdp)
 /*
  * The linux hugepage PMD now include the pmd entries followed by the address
  * to the stashed pgtable_t. The stashed pgtable_t contains the hpte bits.
- * [ 1 bit secondary | 3 bit hidx | 1 bit valid | 000]. We use one byte per
+ * [ 000 | 1 bit secondary | 3 bit hidx | 1 bit valid]. We use one byte per
  * each HPTE entry. With 16MB hugepage and 64K HPTE we need 256 entries and
  * with 4K HPTE we need 4096 entries. Both will fit in a 4K pgtable_t.
  *
- * The last three bits are intentionally left to zero. This memory location
+ * The top three bits are intentionally left as zero. This memory location
  * are also used as normal page PTE pointers. So if we have any pointers
  * left around while we collapse a hugepage, we need to make sure
  * _PAGE_PRESENT bit of that is zero when we look at them
  */
 static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index)
 {
-	return (hpte_slot_array[index] >> 3) & 0x1;
+	return hpte_slot_array[index] & 0x1;
 }

 static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array,
 					   int index)
 {
-	return hpte_slot_array[index] >> 4;
+	return hpte_slot_array[index] >> 1;
 }

 static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array,
 					unsigned int index, unsigned int hidx)
 {
-	hpte_slot_array[index] = hidx << 4 | 0x1 << 3;
+	hpte_slot_array[index] = (hidx << 1) | 0x1;
 }

 /*
diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index fcab33f..72ea557 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -14,7 +14,6 @@
  * combinations that newer processors provide but we currently don't.
  */
 #define _PAGE_PTE		0x00001	/* distinguishes PTEs from pointers */
-#define _PAGE_PRESENT		0x00002 /* software: pte contains a translation */
 #define _PAGE_BIT_SWAP_TYPE	2
 #define _PAGE_USER		0x00004 /* page may be accessed by userspace */
 #define _PAGE_EXEC		0x00008 /* execute permission */
@@ -39,6 +38,8 @@
 #define _PAGE_SOFT_DIRTY	0x00000
 #endif

+#define _PAGE_PRESENT		(1ul << 63)	/* pte contains a translation */
+
 /*
  * We need to differentiate between explicit huge page and THP huge
  * page, since THP huge page also need to track real subpage details
@@ -399,7 +400,7 @@ static inline int pte_protnone(pte_t pte)

 static inline int pte_present(pte_t pte)
 {
-	return pte_val(pte) & _PAGE_PRESENT;
+	return !!(pte_val(pte) & _PAGE_PRESENT);
 }

 /* Conversion functions: convert a page and protection to a page entry,
diff --git a/arch/powerpc/mm/mmu_decl.h b/arch/powerpc/mm/mmu_decl.h
index 9f58ff4..92da107 100644
--- a/arch/powerpc/mm/mmu_decl.h
+++ b/arch/powerpc/mm/mmu_decl.h
@@ -110,7 +110,7 @@ extern unsigned long Hash_size, Hash_mask;
 #endif /* CONFIG_PPC32 */

 #ifdef CONFIG_PPC64
-extern int map_kernel_page(unsigned long ea, unsigned long pa, int flags);
+extern int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t flags);
 #endif /* CONFIG_PPC64 */

 extern unsigned long ioremap_bot;
diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c
index 950c572..c50d9a2 100644
--- a/arch/powerpc/mm/pgtable_64.c
+++ b/arch/powerpc/mm/pgtable_64.c
@@ -88,7 +88,7 @@ static __ref void *early_alloc_pgtable(unsigned long size)
  * map_kernel_page adds an entry to the ioremap page table
  * and adds an entry to the HPT, possibly bolting it
  */
-int map_kernel_page(unsigned long ea, unsigned long pa, int flags)
+int map_kernel_page(unsigned long ea, unsigned long pa, pgprot_t flags)
 {
 	pgd_t *pgdp;
 	pud_t *pudp;
-- 
2.5.0

Re: [RFC PATCH 4/9] powerpc/mm/book3s-64: Move _PAGE_PRESENT to the most significant bit

From: Paul Mackerras <hidden>
Date: 2016-02-21 22:46:13 

On Sat, Feb 20, 2016 at 10:11:14PM +0530, Aneesh Kumar K.V wrote:
Paul Mackerras [off-list ref] writes:
quoted
This changes _PAGE_PRESENT for 64-bit Book 3S processors from 0x2 to
0x8000_0000_0000_0000, because that is where PowerISA v3.0 CPUs in
radix mode will expect to find it.
All the changes in this patch related to _PAGE_PRESENT movement or are
they cleanup that got added to this patch. I am looking at the hpte slot
array changes and wondering how that is related to _PAGE_PRESENT.
I was preserving the property mentioned in this comment:
quoted
 /*
  * The linux hugepage PMD now include the pmd entries followed by the address
  * to the stashed pgtable_t. The stashed pgtable_t contains the hpte bits.
- * [ 1 bit secondary | 3 bit hidx | 1 bit valid | 000]. We use one byte per
+ * [ 000 | 1 bit secondary | 3 bit hidx | 1 bit valid]. We use one byte per
  * each HPTE entry. With 16MB hugepage and 64K HPTE we need 256 entries and
  * with 4K HPTE we need 4096 entries. Both will fit in a 4K pgtable_t.
  *
- * The last three bits are intentionally left to zero. This memory location
+ * The top three bits are intentionally left as zero. This memory location
  * are also used as normal page PTE pointers. So if we have any pointers
  * left around while we collapse a hugepage, we need to make sure
  * _PAGE_PRESENT bit of that is zero when we look at them
I don't know if this comment still applies, but now that _PAGE_PRESENT
is the top bit of a byte rather than one of the low bits, then to avoid
having _PAGE_PRESENT overlap these HPTE location bits in a byte, we
need to move the location bits.

It seems pretty bogus to me that we might interpret an array of these
bytes as a PTE, and if you're sure we never do that, we can drop this
change (and the now-misleading comment).

Paul.

[RFC PATCH 5/9] powerpc/mm/book3s-64: Move _PAGE_PTE to 2nd most significant bit

From: Paul Mackerras <hidden>
Date: 2016-02-20 06:13:15 

This changes _PAGE_PTE for 64-bit Book 3S processors from 0x1 to
0x4000_0000_0000_0000, because that bit is used as the L (leaf)
bit by PowerISA v3.0 CPUs in radix mode.  The "leaf" bit indicates
that the PTE points to a page directly rather than another radix
level, which is what the _PAGE_PTE bit means.

Signed-off-by: Paul Mackerras <redacted>
---
 arch/powerpc/include/asm/book3s/64/hash.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index 72ea557..8f077c1 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -13,7 +13,6 @@
  * We could create separate kernel read-only if we used the 3 PP bits
  * combinations that newer processors provide but we currently don't.
  */
-#define _PAGE_PTE		0x00001	/* distinguishes PTEs from pointers */
 #define _PAGE_BIT_SWAP_TYPE	2
 #define _PAGE_USER		0x00004 /* page may be accessed by userspace */
 #define _PAGE_EXEC		0x00008 /* execute permission */
@@ -38,6 +37,7 @@
 #define _PAGE_SOFT_DIRTY	0x00000
 #endif
 
+#define _PAGE_PTE		(1ul << 62)	/* distinguishes PTEs from pointers */
 #define _PAGE_PRESENT		(1ul << 63)	/* pte contains a translation */
 
 /*
-- 
2.5.0

[RFC PATCH 6/9] powerpc/mm/book3s-64: Move HPTE-related bits in PTE to upper end

From: Paul Mackerras <hidden>
Date: 2016-02-20 06:13:16 

This moves the _PAGE_HASHPTE, _PAGE_F_GIX and _PAGE_F_SECOND fields in
the Linux PTE on 64-bit Book 3S systems to the most significant byte.
Of the 5 bits, one is a software-use bit and the other four are
reserved bit positions in the PowerISA v3.0 radix PTE format.
Using these bits is OK because these bits are all to do with tracking
the HPTE(s) associated with the Linux PTE, and therefore won't be
needed in radix mode.  This frees up bit positions in the lower two
bytes.

Signed-off-by: Paul Mackerras <redacted>
---
 arch/powerpc/include/asm/book3s/64/hash.h | 8 ++++----
 arch/powerpc/mm/hugetlbpage-hash64.c      | 5 +++--
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index 8f077c1..c8eba0e 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -24,11 +24,7 @@
 #define _PAGE_DIRTY		0x00080 /* C: page changed */
 #define _PAGE_ACCESSED		0x00100 /* R: page referenced */
 #define _PAGE_RW		0x00200 /* software: user write access allowed */
-#define _PAGE_HASHPTE		0x00400 /* software: pte has an associated HPTE */
 #define _PAGE_BUSY		0x00800 /* software: PTE & hash are busy */
-#define _PAGE_F_GIX		0x07000 /* full page: hidx bits */
-#define _PAGE_F_GIX_SHIFT	12
-#define _PAGE_F_SECOND		0x08000 /* Whether to use secondary hash or not */
 #define _PAGE_SPECIAL		0x10000 /* software: special page */
 
 #ifdef CONFIG_MEM_SOFT_DIRTY
@@ -37,6 +33,10 @@
 #define _PAGE_SOFT_DIRTY	0x00000
 #endif
 
+#define _PAGE_F_GIX_SHIFT	57
+#define _PAGE_F_GIX		(7ul << 57)	/* HPTE index within HPTEG */
+#define _PAGE_F_SECOND		(1ul << 60)	/* HPTE is in 2ndary HPTEG */
+#define _PAGE_HASHPTE		(1ul << 61)	/* PTE has associated HPTE */
 #define _PAGE_PTE		(1ul << 62)	/* distinguishes PTEs from pointers */
 #define _PAGE_PRESENT		(1ul << 63)	/* pte contains a translation */
 
diff --git a/arch/powerpc/mm/hugetlbpage-hash64.c b/arch/powerpc/mm/hugetlbpage-hash64.c
index e2138c7..8555fce 100644
--- a/arch/powerpc/mm/hugetlbpage-hash64.c
+++ b/arch/powerpc/mm/hugetlbpage-hash64.c
@@ -76,7 +76,7 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
 		if (old_pte & _PAGE_F_SECOND)
 			hash = ~hash;
 		slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
-		slot += (old_pte & _PAGE_F_GIX) >> 12;
+		slot += (old_pte & _PAGE_F_GIX) >> _PAGE_F_GIX_SHIFT;
 
 		if (ppc_md.hpte_updatepp(slot, rflags, vpn, mmu_psize,
 					 mmu_psize, ssize, flags) == -1)
@@ -105,7 +105,8 @@ int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
 			return -1;
 		}
 
-		new_pte |= (slot << 12) & (_PAGE_F_SECOND | _PAGE_F_GIX);
+		new_pte |= (slot << _PAGE_F_GIX_SHIFT) &
+			(_PAGE_F_SECOND | _PAGE_F_GIX);
 	}
 
 	/*
-- 
2.5.0

[RFC PATCH 7/9] powerpc/mm/book3s-64: Shuffle read, write, execute and user bits in PTE

From: Paul Mackerras <hidden>
Date: 2016-02-20 06:13:17 

This moves the _PAGE_EXEC, _PAGE_RW and _PAGE_USER bits around in
the Linux PTE on 64-bit Book 3S systems to correspond with the bit
positions used in radix mode by PowerISA v3.0 CPUs.  This also adds
a _PAGE_READ bit corresponding to the read permission bit in the
radix PTE.  _PAGE_READ is currently unused but could possibly be used
in future to improve pte_protnone().

Signed-off-by: Paul Mackerras <redacted>
---
 arch/powerpc/include/asm/book3s/64/hash.h | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index c8eba0e..0fc750c 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -13,9 +13,12 @@
  * We could create separate kernel read-only if we used the 3 PP bits
  * combinations that newer processors provide but we currently don't.
  */
-#define _PAGE_BIT_SWAP_TYPE	2
-#define _PAGE_USER		0x00004 /* page may be accessed by userspace */
-#define _PAGE_EXEC		0x00008 /* execute permission */
+#define _PAGE_BIT_SWAP_TYPE	0
+
+#define _PAGE_EXEC		0x00001 /* execute permission */
+#define _PAGE_RW		0x00002 /* read & write access allowed */
+#define _PAGE_READ		0x00004	/* read access allowed */
+#define _PAGE_USER		0x00008 /* page may be accessed by userspace */
 #define _PAGE_GUARDED		0x00010 /* G: guarded (side-effect) page */
 /* M (memory coherence) is always set in the HPTE, so we don't need it here */
 #define _PAGE_COHERENT		0x0
@@ -23,7 +26,6 @@
 #define _PAGE_WRITETHRU		0x00040 /* W: cache write-through */
 #define _PAGE_DIRTY		0x00080 /* C: page changed */
 #define _PAGE_ACCESSED		0x00100 /* R: page referenced */
-#define _PAGE_RW		0x00200 /* software: user write access allowed */
 #define _PAGE_BUSY		0x00800 /* software: PTE & hash are busy */
 #define _PAGE_SPECIAL		0x10000 /* software: special page */
 
-- 
2.5.0

Re: [RFC PATCH 7/9] powerpc/mm/book3s-64: Shuffle read, write, execute and user bits in PTE

From: Aneesh Kumar K.V <hidden>
Date: 2016-02-21 07:31:04 

Paul Mackerras [off-list ref] writes:
quoted hunk
This moves the _PAGE_EXEC, _PAGE_RW and _PAGE_USER bits around in
the Linux PTE on 64-bit Book 3S systems to correspond with the bit
positions used in radix mode by PowerISA v3.0 CPUs.  This also adds
a _PAGE_READ bit corresponding to the read permission bit in the
radix PTE.  _PAGE_READ is currently unused but could possibly be used
in future to improve pte_protnone().

Signed-off-by: Paul Mackerras <redacted>
---
 arch/powerpc/include/asm/book3s/64/hash.h | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index c8eba0e..0fc750c 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -13,9 +13,12 @@
  * We could create separate kernel read-only if we used the 3 PP bits
  * combinations that newer processors provide but we currently don't.
  */
-#define _PAGE_BIT_SWAP_TYPE	2
-#define _PAGE_USER		0x00004 /* page may be accessed by userspace */
-#define _PAGE_EXEC		0x00008 /* execute permission */
+#define _PAGE_BIT_SWAP_TYPE	0
+
+#define _PAGE_EXEC		0x00001 /* execute permission */
+#define _PAGE_RW		0x00002 /* read & write access allowed */
+#define _PAGE_READ		0x00004	/* read access allowed */
+#define _PAGE_USER		0x00008 /* page may be accessed by userspace */
 #define _PAGE_GUARDED		0x00010 /* G: guarded (side-effect) page */
 /* M (memory coherence) is always set in the HPTE, so we don't need it here */
 #define _PAGE_COHERENT		0x0
@@ -23,7 +26,6 @@
 #define _PAGE_WRITETHRU		0x00040 /* W: cache write-through */
 #define _PAGE_DIRTY		0x00080 /* C: page changed */
 #define _PAGE_ACCESSED		0x00100 /* R: page referenced */
-#define _PAGE_RW		0x00200 /* software: user write access allowed */
 #define _PAGE_BUSY		0x00800 /* software: PTE & hash are busy */
 #define _PAGE_SPECIAL		0x10000 /* software: special page */

For radix, _PAGE_USER is the inverse of this right ?. Ie, we set that
bit position to 1 to indicate privileged access only.

Also can you use constants like
#define _PAGE_USER PPC_BIT(60)

-aneesh

Re: [RFC PATCH 7/9] powerpc/mm/book3s-64: Shuffle read, write, execute and user bits in PTE

From: Paul Mackerras <hidden>
Date: 2016-02-21 22:46:13 

On Sun, Feb 21, 2016 at 01:00:54PM +0530, Aneesh Kumar K.V wrote:
Paul Mackerras [off-list ref] writes:
quoted
This moves the _PAGE_EXEC, _PAGE_RW and _PAGE_USER bits around in
the Linux PTE on 64-bit Book 3S systems to correspond with the bit
positions used in radix mode by PowerISA v3.0 CPUs.  This also adds
a _PAGE_READ bit corresponding to the read permission bit in the
radix PTE.  _PAGE_READ is currently unused but could possibly be used
in future to improve pte_protnone().

Signed-off-by: Paul Mackerras <redacted>
---
 arch/powerpc/include/asm/book3s/64/hash.h | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index c8eba0e..0fc750c 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -13,9 +13,12 @@
  * We could create separate kernel read-only if we used the 3 PP bits
  * combinations that newer processors provide but we currently don't.
  */
-#define _PAGE_BIT_SWAP_TYPE	2
-#define _PAGE_USER		0x00004 /* page may be accessed by userspace */
-#define _PAGE_EXEC		0x00008 /* execute permission */
+#define _PAGE_BIT_SWAP_TYPE	0
+
+#define _PAGE_EXEC		0x00001 /* execute permission */
+#define _PAGE_RW		0x00002 /* read & write access allowed */
+#define _PAGE_READ		0x00004	/* read access allowed */
+#define _PAGE_USER		0x00008 /* page may be accessed by userspace */
 #define _PAGE_GUARDED		0x00010 /* G: guarded (side-effect) page */
 /* M (memory coherence) is always set in the HPTE, so we don't need it here */
 #define _PAGE_COHERENT		0x0
@@ -23,7 +26,6 @@
 #define _PAGE_WRITETHRU		0x00040 /* W: cache write-through */
 #define _PAGE_DIRTY		0x00080 /* C: page changed */
 #define _PAGE_ACCESSED		0x00100 /* R: page referenced */
-#define _PAGE_RW		0x00200 /* software: user write access allowed */
 #define _PAGE_BUSY		0x00800 /* software: PTE & hash are busy */
 #define _PAGE_SPECIAL		0x10000 /* software: special page */

For radix, _PAGE_USER is the inverse of this right ?. Ie, we set that
bit position to 1 to indicate privileged access only.
Right, we'll need a follow-on patch that changes this to a _PAGE_PRIV
bit and changes the logic that uses _PAGE_USER either that or a
_PAGE_PRIV bit.  But at least we have the bit position reserved now.

Also can you use constants like
#define _PAGE_USER PPC_BIT(60)
I'd really rather not - that is harder for the casual reader to parse,
because they then have to go off and find out what exactly PPC_BIT
does.  The only time that using PPC_BIT would help is when checking
that the bit definitions match the Power ISA, and that's presumably
done by intelligent people that can handle backwards bit numbering in
their heads. :)

Paul.

Re: [RFC PATCH 7/9] powerpc/mm/book3s-64: Shuffle read, write, execute and user bits in PTE

From: Michael Ellerman <mpe@ellerman.id.au>
Date: 2016-02-22 00:27:37 

On Mon, 2016-02-22 at 09:36 +1100, Paul Mackerras wrote:
On Sun, Feb 21, 2016 at 01:00:54PM +0530, Aneesh Kumar K.V wrote:
quoted
Paul Mackerras [off-list ref] writes:

Also can you use constants like
#define _PAGE_USER PPC_BIT(60)
I'd really rather not - that is harder for the casual reader to parse,
because they then have to go off and find out what exactly PPC_BIT
does.  The only time that using PPC_BIT would help is when checking
that the bit definitions match the Power ISA, and that's presumably
done by intelligent people that can handle backwards bit numbering in
their heads. :)
Yep agree 100%.

Using PPC_BIT() means every time someone sees that defintion they need to think
about what the conversion is and whether it's right, ie. for the entire future
history of this code.

On the other hand not using PPC_BIT() means the person who writes the
definition needs to think about it and do the correct conversion, but only
once.

cheers

[RFC PATCH 8/9] powerpc/mm/book3s-64: Move software-used bits in PTE

From: Paul Mackerras <hidden>
Date: 2016-02-20 06:13:18 

This moves the _PAGE_BUSY, _PAGE_SPECIAL and _PAGE_SOFT_DIRTY bits
in the Linux PTE on 64-bit Book 3S systems to bit positions which
are designated for software use in the radix PTE format used by
PowerISA v3.0 CPUs in radix mode.

Signed-off-by: Paul Mackerras <redacted>
---
 arch/powerpc/include/asm/book3s/64/hash.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h
index 0fc750c..f355a8b 100644
--- a/arch/powerpc/include/asm/book3s/64/hash.h
+++ b/arch/powerpc/include/asm/book3s/64/hash.h
@@ -26,11 +26,11 @@
 #define _PAGE_WRITETHRU		0x00040 /* W: cache write-through */
 #define _PAGE_DIRTY		0x00080 /* C: page changed */
 #define _PAGE_ACCESSED		0x00100 /* R: page referenced */
-#define _PAGE_BUSY		0x00800 /* software: PTE & hash are busy */
-#define _PAGE_SPECIAL		0x10000 /* software: special page */
+#define _PAGE_BUSY		0x00200 /* software: PTE & hash are busy */
+#define _PAGE_SPECIAL		0x00400 /* software: special page */
 
 #ifdef CONFIG_MEM_SOFT_DIRTY
-#define _PAGE_SOFT_DIRTY	0x20000 /* software: software dirty tracking */
+#define _PAGE_SOFT_DIRTY	0x00800 /* software: software dirty tracking */
 #else
 #define _PAGE_SOFT_DIRTY	0x00000
 #endif
-- 
2.5.0

[RFC PATCH 9/9] powerpc/mm/book3s-64: Expand the real page number field of the Linux PTE

From: Paul Mackerras <hidden>
Date: 2016-02-20 06:13:18 

Now that other PTE fields have been moved out of the way, we can
expand the RPN field of the PTE on 64-bit Book 3S systems and align
it with the RPN field in the radix PTE format used by PowerISA v3.0
CPUs in radix mode.  For 64k page size, this means we need to move
the _PAGE_COMBO and _PAGE_4K_PFN bits.

Signed-off-by: Paul Mackerras <redacted>
---
 arch/powerpc/include/asm/book3s/64/hash-4k.h  |  4 ++--
 arch/powerpc/include/asm/book3s/64/hash-64k.h | 12 ++++++------
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/include/asm/book3s/64/hash-4k.h
index 0425d3e..7f60f7e 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h
@@ -52,8 +52,8 @@
 			 _PAGE_F_SECOND | _PAGE_F_GIX)
 
 /* shift to put page number into pte */
-#define PTE_RPN_SHIFT	(18)
-#define PTE_RPN_SIZE	(39)	/* gives 51-bit real addresses */
+#define PTE_RPN_SHIFT	(12)
+#define PTE_RPN_SIZE	(45)	/* gives 57-bit real addresses */
 
 #define _PAGE_4K_PFN		0
 #ifndef __ASSEMBLY__
diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc/include/asm/book3s/64/hash-64k.h
index ed390e1..8bb0325 100644
--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h
@@ -25,8 +25,8 @@
 #define PGDIR_SIZE	(1UL << PGDIR_SHIFT)
 #define PGDIR_MASK	(~(PGDIR_SIZE-1))
 
-#define _PAGE_COMBO	0x00040000 /* this is a combo 4k page */
-#define _PAGE_4K_PFN	0x00080000 /* PFN is for a single 4k page */
+#define _PAGE_COMBO	0x00001000 /* this is a combo 4k page */
+#define _PAGE_4K_PFN	0x00002000 /* PFN is for a single 4k page */
 /*
  * Used to track subpage group valid if _PAGE_COMBO is set
  * This overloads _PAGE_F_GIX and _PAGE_F_SECOND
@@ -39,11 +39,11 @@
 
 /* Shift to put page number into pte.
  *
- * That gives us a max RPN of 37 bits, which means a max of 53 bits
- * of addressable physical space, or 49 bits for the special 4k PFNs.
+ * That gives us a max RPN of 41 bits, which means a max of 57 bits
+ * of addressable physical space, or 53 bits for the special 4k PFNs.
  */
-#define PTE_RPN_SHIFT	(20)
-#define PTE_RPN_SIZE	(37)
+#define PTE_RPN_SHIFT	(16)
+#define PTE_RPN_SIZE	(41)
 
 /*
  * we support 16 fragments per PTE page of 64K size.
-- 
2.5.0

Re: [RFC PATCH 0/9] powerpc/mm: Restructure Linux PTE on Book3S/64 to radix format

From: Aneesh Kumar K.V <hidden>
Date: 2016-02-20 14:40:34 

Paul Mackerras [off-list ref] writes:

This patch series modifies the Linux PTE format used on 64-bit Book3S
processors (i.e. POWER server processors) to make the bits line up
with the PTE format used in the radix trees defined in PowerISA v3.0.
This will reduce the amount of further change required to make a
kernel that can run with either a radix MMU or a hashed page table
(HPT) MMU.

This also changes the upper levels of the tree to use real addresses
rather than kernel virtual addresses - that is, we no longer have the
0xc000... at the top of each PGD/PUD/PMD entry.  I made this change
for all 64-bit machines, both embedded and server.

The patch series is against v4.5-rc4 plus Aneesh's "powerpc/mm/hash:
Clear the invalid slot information correctly" patch.

I have compiled this for all the defconfigs in the tree, without
error.  I have tested this, with the fixes branch of the powerpc tree
merged in, both running bare-metal on a POWER8 and in a KVM guest on
that POWER8 system.  In the guest I tested both 4k and 64k configs,
with THP enabled; in the host I tested with 64k page size and THP
enabled.  All these tests ran fine, including running a KVM guest on
the bare-metal system.  So far I have done kernel compiles in a loop
as the test, but I plan to run LTP and possibly some other tests.

Comments welcome.
I was expecting some complex changes in asm and other part of the code. That
is one of the reason I was holding of a series like this till I get the
radix merged. I should have really tried the radix/hash linux page table 
consolidation to see the impact.

Now how do we want to go with this series ?. If we are taking this
series before the books3 hash linux abstraction series, I will have to
redo that series now on top of this.

-aneesh

Re: [RFC PATCH 0/9] powerpc/mm: Restructure Linux PTE on Book3S/64 to radix format

From: Aneesh Kumar K.V <hidden>
Date: 2016-02-20 15:32:37 

"Aneesh Kumar K.V" [off-list ref] writes:

Paul Mackerras [off-list ref] writes:
quoted
This patch series modifies the Linux PTE format used on 64-bit Book3S
processors (i.e. POWER server processors) to make the bits line up
with the PTE format used in the radix trees defined in PowerISA v3.0.
This will reduce the amount of further change required to make a
kernel that can run with either a radix MMU or a hashed page table
(HPT) MMU.

This also changes the upper levels of the tree to use real addresses
rather than kernel virtual addresses - that is, we no longer have the
0xc000... at the top of each PGD/PUD/PMD entry.  I made this change
for all 64-bit machines, both embedded and server.

The patch series is against v4.5-rc4 plus Aneesh's "powerpc/mm/hash:
Clear the invalid slot information correctly" patch.

I have compiled this for all the defconfigs in the tree, without
error.  I have tested this, with the fixes branch of the powerpc tree
merged in, both running bare-metal on a POWER8 and in a KVM guest on
that POWER8 system.  In the guest I tested both 4k and 64k configs,
with THP enabled; in the host I tested with 64k page size and THP
enabled.  All these tests ran fine, including running a KVM guest on
the bare-metal system.  So far I have done kernel compiles in a loop
as the test, but I plan to run LTP and possibly some other tests.

Comments welcome.
I was expecting some complex changes in asm and other part of the code. That
is one of the reason I was holding of a series like this till I get the
radix merged. I should have really tried the radix/hash linux page table 
consolidation to see the impact.

Now how do we want to go with this series ?. If we are taking this
series before the books3 hash linux abstraction series, I will have to
redo that series now on top of this.
Another option is to do this on top of book3s hash linux abstraction
series. I can drop the core patch 

mm: Some arch may want to use HPAGE_PMD related values as variables

and rest goes in as it is. Later with this patch series we undo some of
abstraction added. With that approach with each pte bit that we are
moving we also document which part of radix won't need an update.

-aneesh

Re: [RFC PATCH 0/9] powerpc/mm: Restructure Linux PTE on Book3S/64 to radix format

From: Aneesh Kumar K.V <hidden>
Date: 2016-02-21 07:41:27 

"Aneesh Kumar K.V" [off-list ref] writes:

Paul Mackerras [off-list ref] writes:
quoted
This patch series modifies the Linux PTE format used on 64-bit Book3S
processors (i.e. POWER server processors) to make the bits line up
with the PTE format used in the radix trees defined in PowerISA v3.0.
This will reduce the amount of further change required to make a
kernel that can run with either a radix MMU or a hashed page table
(HPT) MMU.

This also changes the upper levels of the tree to use real addresses
rather than kernel virtual addresses - that is, we no longer have the
0xc000... at the top of each PGD/PUD/PMD entry.  I made this change
for all 64-bit machines, both embedded and server.

The patch series is against v4.5-rc4 plus Aneesh's "powerpc/mm/hash:
Clear the invalid slot information correctly" patch.

I have compiled this for all the defconfigs in the tree, without
error.  I have tested this, with the fixes branch of the powerpc tree
merged in, both running bare-metal on a POWER8 and in a KVM guest on
that POWER8 system.  In the guest I tested both 4k and 64k configs,
with THP enabled; in the host I tested with 64k page size and THP
enabled.  All these tests ran fine, including running a KVM guest on
the bare-metal system.  So far I have done kernel compiles in a loop
as the test, but I plan to run LTP and possibly some other tests.

Comments welcome.
I was expecting some complex changes in asm and other part of the code. That
is one of the reason I was holding of a series like this till I get the
radix merged. I should have really tried the radix/hash linux page table 
consolidation to see the impact.
One of the details that i hit last time with _PAGE_PTE was the usage of
@h symbol in asm code. I did a quick look and I guess we are ok. But it
will be good to double check. pmdp_splitting_flush (which got removed)
had usages like %4@h etc

-aneesh

Re: [RFC PATCH 0/9] powerpc/mm: Restructure Linux PTE on Book3S/64 to radix format

From: Paul Mackerras <hidden>
Date: 2016-02-21 22:46:13 

On Sun, Feb 21, 2016 at 01:11:17PM +0530, Aneesh Kumar K.V wrote:
"Aneesh Kumar K.V" [off-list ref] writes:
quoted
Paul Mackerras [off-list ref] writes:
quoted
This patch series modifies the Linux PTE format used on 64-bit Book3S
processors (i.e. POWER server processors) to make the bits line up
with the PTE format used in the radix trees defined in PowerISA v3.0.
This will reduce the amount of further change required to make a
kernel that can run with either a radix MMU or a hashed page table
(HPT) MMU.

This also changes the upper levels of the tree to use real addresses
rather than kernel virtual addresses - that is, we no longer have the
0xc000... at the top of each PGD/PUD/PMD entry.  I made this change
for all 64-bit machines, both embedded and server.

The patch series is against v4.5-rc4 plus Aneesh's "powerpc/mm/hash:
Clear the invalid slot information correctly" patch.

I have compiled this for all the defconfigs in the tree, without
error.  I have tested this, with the fixes branch of the powerpc tree
merged in, both running bare-metal on a POWER8 and in a KVM guest on
that POWER8 system.  In the guest I tested both 4k and 64k configs,
with THP enabled; in the host I tested with 64k page size and THP
enabled.  All these tests ran fine, including running a KVM guest on
the bare-metal system.  So far I have done kernel compiles in a loop
as the test, but I plan to run LTP and possibly some other tests.

Comments welcome.
I was expecting some complex changes in asm and other part of the code. That
is one of the reason I was holding of a series like this till I get the
radix merged. I should have really tried the radix/hash linux page table 
consolidation to see the impact.
One of the details that i hit last time with _PAGE_PTE was the usage of
@h symbol in asm code. I did a quick look and I guess we are ok. But it
will be good to double check. pmdp_splitting_flush (which got removed)
had usages like %4@h etc
I have done some pretty thorough grepping in arch/powerpc.  There is
no assembly code left that manipulates Linux PTEs (on 64-bit Book 3S,
that is), because you converted it all to C code. :)  There are a
couple of bits of inline asm, but the only bit that is used as an
immediate value is _PAGE_BUSY, which goes from 0x800 to 0x200, and
could actually stay at 0x800 in fact.

Paul.

Re: [RFC PATCH 0/9] powerpc/mm: Restructure Linux PTE on Book3S/64 to radix format

From: Michael Ellerman <mpe@ellerman.id.au>
Date: 2016-02-22 00:30:47 

On Sat, 2016-02-20 at 20:10 +0530, Aneesh Kumar K.V wrote:
Paul Mackerras [off-list ref] writes:
quoted
This patch series modifies the Linux PTE format used on 64-bit Book3S
processors (i.e. POWER server processors) to make the bits line up
with the PTE format used in the radix trees defined in PowerISA v3.0.
This will reduce the amount of further change required to make a
kernel that can run with either a radix MMU or a hashed page table
(HPT) MMU.

This also changes the upper levels of the tree to use real addresses
rather than kernel virtual addresses - that is, we no longer have the
0xc000... at the top of each PGD/PUD/PMD entry.  I made this change
for all 64-bit machines, both embedded and server.

The patch series is against v4.5-rc4 plus Aneesh's "powerpc/mm/hash:
Clear the invalid slot information correctly" patch.

I have compiled this for all the defconfigs in the tree, without
error.  I have tested this, with the fixes branch of the powerpc tree
merged in, both running bare-metal on a POWER8 and in a KVM guest on
that POWER8 system.  In the guest I tested both 4k and 64k configs,
with THP enabled; in the host I tested with 64k page size and THP
enabled.  All these tests ran fine, including running a KVM guest on
the bare-metal system.  So far I have done kernel compiles in a loop
as the test, but I plan to run LTP and possibly some other tests.

Comments welcome.
I was expecting some complex changes in asm and other part of the code. That
is one of the reason I was holding of a series like this till I get the
radix merged.
Yeah, but you actually rewrote most/all of that code in C as part of your
earlier refactoring :)

Now how do we want to go with this series ?. If we are taking this
series before the books3 hash linux abstraction series, I will have to
redo that series now on top of this.
I'd prefer to merge this first.

I know you'll have to redo your series, but hopefully some of your series can
just go away, because we don't need to abstract the PTE bits anymore.

cheers
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